Re: [coreboot] vx800 Example Board Patch
Dear Bari, thanks for your patch. I am really looking forward to get my hands on one of those boards. Do you have any information, when this board will be available? Am Samstag, den 18.07.2009, 14:32 -0500 schrieb bari: […] Yes, it needs some work. I'm just passing it along from the developers. I don't know the reasons why they decided on some of the changes you mentioned. We will probably never know, other than it was just how they got it working in their spare time in a land far far away. At least it's free to be used by everyone now. So what is the best way to proceed. If the patches are cleaned up would the developers, you got the patches from, incorporate them into their tree and base their other patches on this code base or would they just ignore them? Would they also test the altered changes and answer some questions? Bests and please say a thanks to the developers, Paul signature.asc Description: Dies ist ein digital signierter Nachrichtenteil -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Gigabyte GA-MA74GM-S2H rev2
Hello Coreboot team! I have a Gigabyte GA-MA74GM-S2H http://tinyurl.com/GA-MA74GM-S2H* *Mainboard and I have a little hope that this MB is supported?? or maybe even in the near future??.. The Mainboard has an AMD740G /SB700 Chipset, according to the wiki I am posting here my output's from Flashrom,lspci,superiotool,dmidecode I am not sure if I am doing this right, dont want to flood the message so I put the output logs to a pastebin. Output Flashrom -V: http://filebin.ca/bjkzfx/flashrom_V.txt Output lspci -nnvvv : http://filebin.ca/zxxfba/lspci_nnvvvxxx.txt Output dmidecode: http://filebin.ca/kxrdaa/dmidecode.txt Output superiotool: http://filebin.ca/kkpkdw/superiotool_edV.txt Hope this information was helpful, and hope for some help on this.. Thanks Jason -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Gigabyte GA-MA74GM-S2H rev2
Dear Jason, Am Sonntag, den 19.07.2009, 11:48 +0200 schrieb Jason Scurtu: […] I have a Gigabyte GA-MA74GM-S2H http://tinyurl.com/GA-MA74GM-S2H Mainboard and I have a little hope that this MB is supported?? […] Hope this information was helpful, and hope for some help on this.. Right now your board is not supported. But stay tuned. It looks like we will be getting code from the great guys at AMD soon [1]. Is the 740G chipset similar to the 780G? Bests, Paul [1] http://coreboot.org/pipermail/coreboot/2009-July/050625.html signature.asc Description: Dies ist ein digital signierter Nachrichtenteil -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Gigabyte GA-MA74GM-S2H rev2
Hi Paul Is the 740G chipset similar to the 780G? Well the 780G has a HD based graphics core and the 740G is X-Series based I think (X700) they just call it 2100 .. So there is a difference.. you can see it on http://en.wikipedia.org/wiki/AMD_7-Series_Chipsets Jason -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Gigabyte GA-MA74GM-S2H rev2
Hi, On 19.07.2009 12:34, Paul Menzel wrote: Am Sonntag, den 19.07.2009, 11:48 +0200 schrieb Jason Scurtu: I have a Gigabyte GA-MA74GM-S2H http://tinyurl.com/GA-MA74GM-S2H Mainboard and I have a little hope that this MB is supported?? I think this board might be a good candidate once the SB700 code is available. Right now your board is not supported. But stay tuned. It looks like we will be getting code from the great guys at AMD soon [1]. Is the 740G chipset similar to the 780G? The 740G is basically the 690G with better graphics, so that part is already supported (except for the PCI ID of the graphics engine). Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] non static 0x1000 IO space can be broken
Hi, Kevin just noticed that recent change in devices.c removed the IO alloc start on IO port address 0x1000, so all code which relies on the fact that 0x1000 and down can be done for static device allocation like in vt8237r.h and k8t890.h will fail now. This needs to be fixed with proper static resource to the read_resources. I'm trying to fix this together with Kevin. Maybe other chipsets/boards will need similar fixups! Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] non static 0x1000 IO space can be broken
On Sun, Jul 19, 2009 at 09:13:20PM +0200, Rudolf Marek wrote:
Hi,
Kevin just noticed that recent change in devices.c removed the IO alloc
start on IO port address 0x1000, so all code which relies on the fact
that 0x1000 and down can be done for static device allocation like in
vt8237r.h and k8t890.h will fail now. This needs to be fixed with proper
static resource to the read_resources. I'm trying to fix this together
with Kevin.
Maybe other chipsets/boards will need similar fixups!
The patch Rudolf and I made is attached. On IRC though, Rudolf noted
that we aren't explicilty allocating 0xcf8 and other crucial
resources. Maybe we should just add a generic resource for everything
under 0x1000?
-Kevin
Index: vt8237r_lpc.c
===
--- vt8237r_lpc.c (revision 4441)
+++ vt8237r_lpc.c (working copy)
@@ -421,8 +421,8 @@
{
struct resource *res;
+ /* Fixed APIC resource */
pci_dev_read_resources(dev);
- /* Fixed APIC resource */
res = new_resource(dev, 0x44);
res-base = VT8237R_APIC_BASE;
res-size = 256;
@@ -431,6 +431,50 @@
res-gran = 8;
res-flags = IORESOURCE_MEM | IORESOURCE_FIXED |
IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+ /* Fixed SPI resource */
+ pci_dev_read_resources(dev);
+ res = new_resource(dev, 0xbe);
+ res-base = VT8237S_SPI_MEM_BASE;
+ res-size = 256;
+ res-limit = res-base + res-size - 1;
+ res-align = 8;
+ res-gran = 8;
+ res-flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+ /* Fixed HPET resource */
+ pci_dev_read_resources(dev);
+ res = new_resource(dev, 0x69);
+ res-base = VT8237R_HPET_ADDR;
+ res-size = 1024;
+ res-limit = res-base + res-size - 1;
+ res-align = 8;
+ res-gran = 8;
+ res-flags = IORESOURCE_MEM | IORESOURCE_FIXED |
+IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+ /* Fixed smbus resource */
+ pci_dev_read_resources(dev);
+ res = new_resource(dev, 0xd0);
+ res-base = VT8237R_SMBUS_IO_BASE;
+ res-size = 16;
+ res-limit = res-base + res-size - 1;
+ res-align = 8;
+ res-gran = 8;
+ res-flags = IORESOURCE_IO | IORESOURCE_FIXED |
+IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+
+ pci_dev_read_resources(dev);
+ /* Fixed pmio resource */
+ res = new_resource(dev, 0x88);
+ res-base = VT8237R_ACPI_IO_BASE;
+ res-size = 128;
+ res-limit = res-base + res-size - 1;
+ res-align = 8;
+ res-gran = 8;
+ res-flags = IORESOURCE_IO | IORESOURCE_FIXED |
+IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
/**
--
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Re: [coreboot] non static 0x1000 IO space can be broken
resources. Maybe we should just add a generic resource for everything under 0x1000? Yes maybe or we can try to fix the stuff which is non trivial :) Here is the list of omitted resources in the patch (specifc to vt8237): 0x00 - 0xdf - legacy resources 0x4d0/0x4d1 - EISA level/edge stuff 0xcf8-0xcff - PCI also the 0x378+0x400 = 0x778 for parallel port ECP dont know if superio handles that. Some other random ports on other chipsets: the SB600 has something at 0xc00 K8M890 has something for S3 NVRAM at 0xf00 Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Board Specific vgahooks.c for vx800 Eaxmple Board
On Sat, Jul 18, 2009 at 11:26:50AM -0500, bari wrote: This version of vgahooks.c was used for the vx800 example board. It makes some changes to int15 support. -Bari The only thing that looked noteworthy was the vx855 memory size and speed detection. I've added that to the latest seabios git. It would help if someone can test it on a real board. -Kevin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] fam10/h8dmr: extreme slowness in CBFS memset / memcpy
Hi all, I'm working on a fam10 tree for supermicro h8dmr. I'm using CBFS. It boots, but I'm struggling with some extreme slowness during boot. In particular, the memset function in src/lib/memset.c takes *minutes* to clear 1.2MB of ram. A little further CBFS does a memcpy which takes another 20 or 30 seconds: Stage: load fallback/coreboot_ram @ 2097152/1245184 bytes, enter @ 20 LOONG pause Stage: after memset on-stack variables at 00ffbec8 and 00ffbed4 cbfs_decompress: algo: 0 cbfs_decompress: uncompressed another lengthy pause cbfs_decompress: memcpy from 0xffbecc to 0xffbed0 for 0x2d304 bytes done Stage: done loading. The first, lengthly pause is new; it is apparently caused by something introduced between r4368 and r4440. The second pause was there already in r4368. I understand this may have something to do with MTRRs - looking at the logs it seems MTRRs are not set up until well after CBFS has dealt with coreboot_ram. This box has 32GB of ram, in case that makes a difference. Any suggestions? Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2
According to the Revision Guide, I think there might be several kinds of 0x100F42 RB-C2. They are AM2r2, AM3, F1207. The actual socket type should be read from CPUID_8001_EBX. Right? Zheng -Original Message- From: Ward Vandewege [mailto:w...@gnu.org] Sent: Friday, July 17, 2009 11:42 PM To: Bao, Zheng Cc: Coreboot Subject: Re: [coreboot] [patch] [AMD Fam10] Fix confused RB-C2 and DA-C2 On Fri, Jul 17, 2009 at 10:01:35AM +0800, Bao, Zheng wrote: RB-C2 probably uses socket type AM3, which is not supported in Coreboot currently. I wonder if your board can go through the whole image. Hmm, I think there is some confusion here. If RB-C2 is really 0x100F42, then we are most certainly talking about Socket F. I have a few Opteron 2372 HE CPUs that are 0x100F42. You can contact tim.per...@amd.com about the patch releasing. Thank you, I have done so. Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
