[coreboot] [v2] r4464 - trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se
Author: ruik
Date: 2009-07-23 10:10:51 +0200 (Thu, 23 Jul 2009)
New Revision: 4464
Modified:
trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/acpi_tables.c
trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c
Log:
We did together some patch which makes finally a MMCONFIG workable in
linux out of the box. There were two problems. First was that the
mmconfig ACPI structure was empty because of cut and paste (PCI ID of
K8M890 is different).
Second problem is now nicely solvable by add_region. Linux expects that
the mmconfig region is found as reserved memory. Otherwise it does not
trust it.
Signed-off-by: Rudolf Marek r.ma...@assembler.cz
Acked-by: Luc Verhaegen l...@skynet.be
Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/acpi_tables.c
===
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/acpi_tables.c
2009-07-22 12:26:18 UTC (rev 4463)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/acpi_tables.c
2009-07-23 08:10:51 UTC (rev 4464)
@@ -40,7 +40,7 @@
device_t dev;
struct resource *res;
- dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8T890CE_5,
0);
+ dev = dev_find_device(PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_K8M890CE_5,
0);
if (!dev)
return current;
Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c
===
--- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c 2009-07-22
12:26:18 UTC (rev 4463)
+++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/mainboard.c 2009-07-23
08:10:51 UTC (rev 4464)
@@ -22,9 +22,22 @@
#include device/pci_ids.h
#include boot/tables.h
#include chip.h
+#include ../../../southbridge/via/k8t890/k8t890.h
int add_mainboard_resources(struct lb_memory *mem)
{
+ device_t dev;
+
+ dev = dev_find_device(PCI_VENDOR_ID_VIA,
+ PCI_DEVICE_ID_VIA_K8M890CE_5, 0);
+ if (dev) {
+ struct resource *res =
+ find_resource(dev, K8T890_MMCONFIG_MBAR);
+ if (res)
+ lb_add_memory_range(mem, LB_MEM_RESERVED, res-base,
+ res-size);
+ }
+
#if CONFIG_HAVE_ACPI_RESUME == 1
lb_add_memory_range(mem, LB_MEM_RESERVED,
CONFIG_RAMBASE, ((CONFIG_LB_MEM_TOPK10) - CONFIG_RAMBASE));
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Asus M2V-MX SE enable MMConfig.
Its in as Committed revision 4464. R. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dell latitude c610
CybFr wrote: Le vendredi 10 juillet 2009 15:51:11, Joseph Smith a écrit : PS: Uwe, I don't know if you received my mail with pictures (sent last monday) BTW I put them there http://www.miradou.com/spip/spip.php?article14 Nice pics :-) Thanks Right now the i830 is only setup for onboard graphics not AGP. Let me know when your ready and I would be glad to help you get it working. I think I'll have my bios socketed on wednesday, in between I try to build my arch coreboot. I think I'll need your help. Thank you. I have a Latitude c400 that I can take apart if needed. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] coreboot cbfs incorrect bootblock size
Hello, I am trying to compile coreboot with cbfs support, everything goes well until it tries to create the cbfs image. ./cbfs/cbfstool ./coreboot.rom create 2097152 131072 ./coreboot.rom.bootlock (cbfstool) E: The bootblock size is not correct (2097152 vs 131072) 131072 is 128kB and 2097152 is 2MB. These are the settings I have in my target's confg.lb file. option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 option CONFIG_ROM_SIZE = 2 * 1024 * 1024 Anyone knows what I am not doing or not doing correctly? Thank you! Arnaud * * -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [patch] sb/via/k8t890: add vga textmode code for k8m890 chrome igp.
Luc Verhaegen wrote: sb/via/k8t890: add vga textmode code for k8m890 chrome igp. Add initialisation for the VIA Chrome 9 IGP on the k8m890 through native code and through the general vga infrastructure i committed a month or two ago. Add videoram_size option for k8m890 and the Asus M2V-MX SE. Now the Asus M2V-MX SE will magically come up with a working standard VGA 80x25 textmode. Many thanks to the people who worked hard on the Asus M2V-MX SE, and all of its components; this vga bringup was a breeze thanks to your hard work for this excellently supported board. And separate thanks to Rudolf Marek for spurring me on and for providing a register dump. Signed-off-by: Luc Verhaegen l...@skynet.be Acked-by: Peter Stuge pe...@stuge.se -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot cbfs incorrect bootblock size
Hi Arnaud, On Thu, Jul 23, 2009 at 02:37:52PM +0200, Arnaud Maye wrote: I am trying to compile coreboot with cbfs support, everything goes well until it tries to create the cbfs image. ./cbfs/cbfstool ./coreboot.rom create 2097152 131072 ./coreboot.rom.bootlock (cbfstool) E: The bootblock size is not correct (2097152 vs 131072) 131072 is 128kB and 2097152 is 2MB. These are the settings I have in my target's confg.lb file. option CONFIG_ROM_IMAGE_SIZE = 128 * 1024 option CONFIG_ROM_SIZE = 2 * 1024 * 1024 Anyone knows what I am not doing or not doing correctly? See http://www.coreboot.org/pipermail/coreboot/2009-June/049363.html where Patrick explained how to convert a board to CBFS. I've used those instructions with success before. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] IOAPIC Initialisation - How much do you have to do ??
Hi Guys, I've mad a fair bit of progress (for me!!) on the EPIA-N(L)/CN400 build. I've got to within a Gnat's proverbial of getting a linux distro to boot. I'm still missing something to get the IRQs through to the CPU, or at least I think that's what's going on. Below are the initial debug/info messages from the kernel (up to the first point where things look suspicious i.e. Timer not connected to IOAPIC). Up to this point things look (almost)identical to the dmesg when booting from Award. *-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*-*- Initializing cgroup subsys cpuset Initializing cgroup subsys cpu Linux version 2.6.25-14.fc9.i686 (mockbuild@) (gcc version 4.3.0 20080428 (Red Hat 4.3.0-8) (GCC) ) #1 SMP Thu May 1 06:28:41 EDT 20 08 BIOS-provided physical RAM map: BIOS-e820: - 1000 type 16 BIOS-e820: 1000 - 000a (usable) BIOS-e820: 0010 - 3bff (usable) BIOS-e820: 3bff - 3c00 type 16 BIOS-e820: fec0 - fec01000 (reserved) BIOS-e820: fee0 - fee01000 (reserved) 63MB HIGHMEM available. 896MB LOWMEM available. Scan SMP from c000 for 1024 bytes. Scan SMP from c009fc00 for 1024 bytes. Scan SMP from c00f for 65536 bytes. Using x86 segment limits to approximate NX protection Entering add_active_range(0, 0, 245744) 0 entries of 256 used Zone PFN ranges: DMA 0 - 4096 Normal 4096 - 229376 HighMem229376 - 245744 Movable zone start PFN for each node early_node_map[1] active PFN ranges 0:0 - 245744 On node 0 totalpages: 245744 DMA zone: 32 pages used for memmap DMA zone: 0 pages reserved DMA zone: 4064 pages, LIFO batch:0 Normal zone: 1760 pages used for memmap Normal zone: 223520 pages, LIFO batch:31 HighMem zone: 127 pages used for memmap HighMem zone: 16241 pages, LIFO batch:3 Movable zone: 0 pages used for memmap DMI not present or invalid. Using APIC driver default ACPI: RSDP 000F0400, 0024 (r2 CORE ) ACPI: RSDT 3BFF0424, 002C (r1 CORE RSDT0 CORE0) ACPI: FACP 3BFF14C1, 00F4 (r4 COREBO COREBOOT0 CORE 2A) ACPI: DSDT 3BFF04C0, 1001 (r1 CBT-V2 CBT-DSDT1 INTL 20061109) ACPI: FACS 3BFF0480, 0040 ACPI: APIC 3BFF15B5, 005A (r1 CORE MADT0 CORE0) ACPI: no DMI BIOS year, acpi=force is required to enable ACPI ACPI: acpi=force override ACPI: PM-Timer IO Port: 0x408 ACPI: Local APIC address 0xfee0 ACPI: LAPIC (acpi_id[0x00] lapic_id[0x00] enabled) Processor #0 6:9 APIC version 17 ACPI: LAPIC_NMI (acpi_id[0x00] high edge lint[0x1]) ACPI: IOAPIC (id[0x02] address[0xfec0] gsi_base[0]) IOAPIC[0]: apic_id 2, version 3, address 0xfec0, GSI 0-23 ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) ACPI: INT_SRC_OVR (bus 0 bus_irq 9 global_irq 9 low level) ACPI: IRQ0 used by override. ACPI: IRQ2 used by override. ACPI: IRQ9 used by override. Enabling APIC mode: Flat. Using 1 I/O APICs Using ACPI (MADT) for SMP configuration information Allocating PCI resources starting at 4000 (gap: 3c00:c2c0) PM: Registered nosave memory: 000a - 0010 Built 1 zonelists in Zone order, mobility grouping on. Total pages: 243825 Kernel command line: ro root=/dev/sda5 acpi=force console=ttyS0,115200n8 debug mapped APIC to b000 (fee0) mapped IOAPIC to a000 (fec0) Enabling fast FPU save and restore... done. Enabling unmasked SIMD FPU exception support... done. Initializing CPU#0 CPU 0 irqstacks, hard=c07b9000 soft=c0799000 PID hash table entries: 4096 (order: 12, 16384 bytes) Detected 800.042 MHz processor. Console: colour VGA+ 80x25 console [ttyS0] enabled Dentry cache hash table entries: 131072 (order: 7, 524288 bytes) Inode-cache hash table entries: 65536 (order: 6, 262144 bytes) Memory: 966672k/982976k available (2236k kernel code, 15640k reserved, 1121k data, 284k init, 65472k highmem) virtual kernel memory layout: fixmap : 0xffc53000 - 0xf000 (3760 kB) pkmap : 0xff40 - 0xff80 (4096 kB) vmalloc : 0xf880 - 0xff3fe000 ( 107 MB) lowmem : 0xc000 - 0xf800 ( 896 MB) .init : 0xc074f000 - 0xc0796000 ( 284 kB) .data : 0xc062f37d - 0xc0747800 (1121 kB) .text : 0xc040 - 0xc062f37d (2236 kB) Checking if this processor honours the WP bit even in supervisor mode...Ok. CPA: page pool initialized 1 of 1 pages preallocated SLUB: Genslabs=12, HWalign=32, Order=0-1, MinObjects=4, CPUs=1, Nodes=1 Calibrating delay using timer specific routine.. 1602.08 BogoMIPS (lpj=801043) Security Framework initialized SELinux: Initializing. SELinux: Starting in permissive mode selinux_register_security: Registering secondary module capability Capability LSM initialized as secondary Mount-cache hash table entries: 512 Initializing cgroup subsys ns Initializing cgroup subsys cpuacct CPU: L1 I Cache: 64K (32 bytes/line), D cache 64K (32
Re: [coreboot] [patch] sb/via/k8t890: add vga textmode code for k8m890 chrome igp.
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Luc, looks fine. Please check the vga_init.c as we discussed on IRC. Also, maybe you can develop simple patch that will write the memsize and speedgrade to scratch registers. Thanks, Rudolf -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkpogb0ACgkQ3J9wPJqZRNV2TwCfT8WRySZRMmKmjbNBY6zKLSXd w6UAoJ3m2n9JDmaUrGUpljM5VwtQxTjZ =HiAA -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [patch] sb/via/k8t890: add vga textmode code for k8m890 chrome igp.
On Thu, Jul 23, 2009 at 05:29:01PM +0200, Rudolf Marek wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Luc, looks fine. Please check the vga_init.c as we discussed on IRC. For that, we need to figure out what these two registers really do depend on and what their effect is. Also, maybe you can develop simple patch that will write the memsize and speedgrade to scratch registers. Tell you what; i'll go off for two days, and develop the solid PLL calculation routine needed to bring up the k8m890 in my unichrome driver. Luc Verhaegen. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4465 - in trunk/coreboot-v2/src: mainboard/asus/m2v-mx_se southbridge/via/k8t890
Author: libv Date: 2009-07-23 18:04:58 +0200 (Thu, 23 Jul 2009) New Revision: 4465 Added: trunk/coreboot-v2/src/southbridge/via/k8t890/k8m890_chrome.c Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout trunk/coreboot-v2/src/southbridge/via/k8t890/Config.lb trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890.h trunk/coreboot-v2/src/southbridge/via/k8t890/k8t890_dram.c Log: sb/via/k8t890: add vga textmode code for k8m890 chrome igp. Add initialisation for the VIA Chrome 9 IGP on the k8m890 through native code and through the general vga infrastructure i committed a month or two ago. Add videoram_size option for k8m890 and the Asus M2V-MX SE. Now the Asus M2V-MX SE will magically come up with a working standard VGA 80x25 textmode. Many thanks to the people who worked hard on the Asus M2V-MX SE, and all of its components; this vga bringup was a breeze thanks to your hard work for this excellently supported board. And separate thanks to Rudolf Marek for spurring me on and for providing a register dump. Signed-off-by: Luc Verhaegen l...@skynet.be Acked-by: Peter Stuge pe...@stuge.se Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb === --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-07-23 08:10:51 UTC (rev 4464) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/Options.lb 2009-07-23 16:04:58 UTC (rev 4465) @@ -44,7 +44,7 @@ uses CONFIG_XIP_ROM_BASE uses CONFIG_STACK_SIZE uses CONFIG_HEAP_SIZE -# uses CONFIG_USE_OPTION_TABLE +uses CONFIG_USE_OPTION_TABLE uses CONFIG_LB_MEM_TOPK uses CONFIG_HAVE_ACPI_TABLES uses CONFIG_HAVE_MAINBOARD_RESOURCES @@ -74,6 +74,7 @@ uses CONFIG_CONSOLE_SERIAL8250 uses CONFIG_HAVE_INIT_TIMER uses CONFIG_GDB_STUB +uses CONFIG_VGA uses CONFIG_CONSOLE_VGA uses CONFIG_PCI_ROM_RUN # bx_b001- uses K8_HW_MEM_HOLE_SIZEK @@ -101,7 +102,7 @@ default CONFIG_HAVE_PIRQ_TABLE = 0 default CONFIG_IRQ_SLOT_COUNT = 11 # FIXME? default CONFIG_HAVE_MP_TABLE = 0 -default CONFIG_HAVE_OPTION_TABLE = 0 # FIXME +default CONFIG_HAVE_OPTION_TABLE = 1 # FIXME # Move the default coreboot CMOS range off of AMD RTC registers. default CONFIG_LB_CKS_RANGE_START = 49 default CONFIG_LB_CKS_RANGE_END = 122 @@ -136,6 +137,7 @@ # Only offset for SB chain?, default is yes(1). default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY = 0 +default CONFIG_VGA = 1 default CONFIG_CONSOLE_VGA = 1 # Needed for VGA. default CONFIG_PCI_ROM_RUN = 0 # Needed for VGA. default CONFIG_USE_DCACHE_RAM = 1 @@ -157,6 +159,7 @@ default CONFIG_LB_MEM_TOPK = 32768 # to 1MB default CONFIG_RAMBASE = 0x1F0 +default CONFIG_USE_OPTION_TABLE = 0 # default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE default CONFIG_ROM_PAYLOAD = 1 default CC = $(CONFIG_CROSS_COMPILE)gcc -m32 Modified: trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout === --- trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout 2009-07-23 08:10:51 UTC (rev 4464) +++ trunk/coreboot-v2/src/mainboard/asus/m2v-mx_se/cmos.layout 2009-07-23 16:04:58 UTC (rev 4465) @@ -43,6 +43,7 @@ 440 4 e 9slow_cpu 444 1 e 1nmi 445 1 e 1iommu +448 3 e 10 videoram_size 728256 h 0user_data 984 16 h 0check_sum # Reserve the extended AMD configuration registers @@ -90,6 +91,13 @@ 9 5 37.5% 9 6 25.0% 9 7 12.5% +# videoram_size: mimics the bits in the ramcontroller. +10 1 8MB +10 2 16MB +10 3 32MB +10 4 64MB +10 5 128MB +10 6 256MB checksums Modified: trunk/coreboot-v2/src/southbridge/via/k8t890/Config.lb === --- trunk/coreboot-v2/src/southbridge/via/k8t890/Config.lb 2009-07-23 08:10:51 UTC (rev 4464) +++ trunk/coreboot-v2/src/southbridge/via/k8t890/Config.lb 2009-07-23 16:04:58 UTC (rev 4465) @@ -25,3 +25,4 @@ driver k8t890_pcie.o driver k8t890_traf_ctrl.o driver k8t890_error.o +driver k8m890_chrome.o Added: trunk/coreboot-v2/src/southbridge/via/k8t890/k8m890_chrome.c === --- trunk/coreboot-v2/src/southbridge/via/k8t890/k8m890_chrome.c (rev 0) +++ trunk/coreboot-v2/src/southbridge/via/k8t890/k8m890_chrome.c 2009-07-23 16:04:58 UTC (rev 4465) @@ -0,0 +1,179 @@ +/* + * Copyright (C) 2007-2009 Luc Verhaegen l...@skynet.be + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or
Re: [coreboot] IOAPIC Initialisation - How much do you have to do ??
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi, I will leave for a holiday today. Its difficult to answer that without the patch at hand. The ..TIMER: vector=0x31 apic1=0 pin1=2 apic2=-1 pin2=-1 ..MP-BIOS bug: 8254 timer not connected to IO-APIC Means that: ACPI: INT_SRC_OVR (bus 0 bus_irq 0 global_irq 2 dfl dfl) For some reason this is wrong. You have same line in the orig bios? If yes there is still smth wrong with APIC. Please check: Assigned: PCI: 00:10.4 10 * [0xfebffd00 - 0xfebffdff] mem Assigned: PCI: 00:10.5 10 * [0xfebffe00 - 0xfebffeff] mem Assigned: PCI: 00:12.0 14 * [0xfebfff00 - 0xfebf] mem PCI_DOMAIN: allocate_resources_mem: next_base: fec0 size: 300 align: 8 gran: 0 done This looks like the mem resources are setup from too high overlaping the IOAPIC with some hardware. No good. Move all resource bases bellow f000. You will need to adjust the northbridge.c and put the PCI resource limit to the address above most likely. Others can help here. Also it seems that you created something in half: ACPI: PCI Interrupt Link [LNKA] (IRQs 3 4 6 7 *10 11 12) ACPI: PCI Interrupt Link [LNKB] (IRQs 3 4 6 7 10 *11 12) ACPI: PCI Interrupt Link [LNKC] (IRQs 3 4 6 7 10 11 *12) ACPI: PCI Interrupt Link [LNKD] (IRQs 3 4 6 7 10 *11 12), disabled. ACPI: PCI Interrupt Link [ATAI] (IRQs *20) ACPI: PCI Interrupt Link [USBI] (IRQs *21) ACPI: PCI Interrupt Link [VT8I] (IRQs *22) ACPI: PCI Interrupt Link [NICI] (IRQs *23) This means you route half of IRQs through APIC and second half through the 8259. Why not route all of them through APIC. Check M2V-MX se board _PRT methods. INTA# to IRQ16 INTB# to IRQ17 INTC# to IRQ18 INTD# to IRQ19 uhci_hcd :00:10.0: Unlink after no-IRQ? Controller is probably using the wrong IRQ. Whoops !! Yes maybe but I think all USBs are routed to IRQ21 so it must be smth else. Like the resource conflict I mentioned above. If VT8237R apic is enabled (and it is) this is routed like this: IDE (Native Mode)/SATA IRQ INTE to IRQ20 USB IRQ (all 5 functions) and INTF to IRQ21 AC'97 / MC'97 IRQ and INTG to IRQ22 LAN IRQ and INTH to IRQ23 So I would recommend to boot now with init=/bin/bash and provide cat /proc/iomem cat /proc/interrupts lspci -vvvxxx I'm going to be most likely AFK for a week so hopefully others can try to help. Most likely is the resource conflict in game. Also check if the APIC messages should be routed by extra bus or as part of FSB messages (there is some bit for that on 0xfec000smth) I think FSB routing is fine for VIA CPU too but not sure. rest looks OK to me. Please provide the WIP patch next time so one can see how you set things up. Thanks, Rudolf -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkpoijwACgkQ3J9wPJqZRNUqUACgqTxXlnbgyQa2jrFkwrECogh8 iKAAn2TtACws0090J7KhBbC3fSE1Nprc =eOhh -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [patch] sb/via/k8t890: add vga textmode code for k8m890 chrome igp.
On Thu, Jul 23, 2009 at 03:18:49PM +0200, Peter Stuge wrote: Luc Verhaegen wrote: sb/via/k8t890: add vga textmode code for k8m890 chrome igp. Add initialisation for the VIA Chrome 9 IGP on the k8m890 through native code and through the general vga infrastructure i committed a month or two ago. Add videoram_size option for k8m890 and the Asus M2V-MX SE. Now the Asus M2V-MX SE will magically come up with a working standard VGA 80x25 textmode. Many thanks to the people who worked hard on the Asus M2V-MX SE, and all of its components; this vga bringup was a breeze thanks to your hard work for this excellently supported board. And separate thanks to Rudolf Marek for spurring me on and for providing a register dump. Signed-off-by: Luc Verhaegen l...@skynet.be Acked-by: Peter Stuge pe...@stuge.se Thanks: - r4465 Luc Verhaegen. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] #144: TYAN S7012 support
#144: TYAN S7012 support +--- Reporter: j...@…| Owner: somebody Type: defect| Status: new Priority: major | Milestone: Component: flashrom |Version: v2 Keywords: TYAN S7012 Intel ICH10R SST SST25VF032B | Dependencies: Patchstatus: there is no patch | +--- I'm unable to flash a system that runs on a TYAN S7012 motherboard. # flashrom -w bios.bin flashrom v0.9.0-r659 No coreboot table found. Found chipset Intel ICH10R, enabling flash write... OK. This chipset supports the following protocols: LPC,FWH,SPI. Calibrating delay loop... OK. Found chip SST SST25VF032B (4096 KB, SPI) at physical address 0xffc0. Flash image seems to be a legacy BIOS. Disabling checks. Writing flash chip... COMPLETE. Verifying flash... VERIFY FAILED at 0x2000! Expected=0x00, Read=0xff Running it with verbose the following error messages are printed out (repeating). Writing flash chip... Invalid OPCODE 0x06 due to SPI master limitation, ignoring and hoping it will be run as PREOP Transaction error! run OPCODE 0x02 failed spi_byte_program failed during command execution Invalid OPCODE 0x06 due to SPI master limitation, ignoring and hoping it will be run as PREOP Transaction error! run OPCODE 0x02 failed spi_byte_program failed during command execution Invalid OPCODE 0x06 CONFIG_STRICT_DEVMEM is not set in my kernel. Anything I should try out? -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/144 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dell latitude c610
On Thu, 23 Jul 2009 10:40:58 +0100, Ryan McLean pvtryan...@googlemail.com wrote: CybFr wrote: Le vendredi 10 juillet 2009 15:51:11, Joseph Smith a écrit : PS: Uwe, I don't know if you received my mail with pictures (sent last monday) BTW I put them there http://www.miradou.com/spip/spip.php?article14 Nice pics :-) Thanks Right now the i830 is only setup for onboard graphics not AGP. Let me know when your ready and I would be glad to help you get it working. I think I'll have my bios socketed on wednesday, in between I try to build my arch coreboot. I think I'll need your help. Thank you. I have a Latitude c400 that I can take apart if needed. Ah, the C400 is a little different. It uses onboard i830 graphics where the C610 uses external AGP graphics. I would give my left arm to see coreboot running on both of these units :-) -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4466 - in trunk/coreboot-v2: src/arch/i386 src/arch/i386/init src/boot src/lib util/cbfstool
Author: oxygene
Date: 2009-07-24 00:03:14 +0200 (Fri, 24 Jul 2009)
New Revision: 4466
Modified:
trunk/coreboot-v2/src/arch/i386/Config.lb
trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb
trunk/coreboot-v2/src/boot/elfboot.c
trunk/coreboot-v2/src/boot/selfboot.c
trunk/coreboot-v2/src/lib/cbfs.c
trunk/coreboot-v2/util/cbfstool/fs.c
Log:
CBFS stuff:
- update, add, and improve comments
- whitespace here and there
- remove unused or write-only variables
- improve debug output
- only build payload.{nrv2b,lzma} for non-cbfs
- improved error checking in cbfstool
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Peter Stuge pe...@stuge.se
Modified: trunk/coreboot-v2/src/arch/i386/Config.lb
===
--- trunk/coreboot-v2/src/arch/i386/Config.lb 2009-07-23 16:04:58 UTC (rev
4465)
+++ trunk/coreboot-v2/src/arch/i386/Config.lb 2009-07-23 22:03:14 UTC (rev
4466)
@@ -5,6 +5,7 @@
uses CONFIG_HAVE_FAILOVER_BOOT
uses CONFIG_USE_FAILOVER_IMAGE
uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_CBFS
init init/crt0.S.lb
@@ -82,9 +83,12 @@
# catch the case where there is no compression
makedefine PAYLOAD-1:=payload
+if CONFIG_CBFS
+else
# match the case where a compression type is specified.
makedefine PAYLOAD-$(CONFIG_COMPRESSED_PAYLOAD_NRV2B):=payload.nrv2b
makedefine PAYLOAD-$(CONFIG_COMPRESSED_PAYLOAD_LZMA):=payload.lzma
+end
# catch the case where there is precompression. Yes, this bites.
if CONFIG_PRECOMPRESSED_PAYLOAD
Modified: trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb
===
--- trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb 2009-07-23 16:04:58 UTC
(rev 4465)
+++ trunk/coreboot-v2/src/arch/i386/init/crt0.S.lb 2009-07-23 22:03:14 UTC
(rev 4466)
@@ -142,7 +142,7 @@
#else
str_copying_to_ram: .string Copying coreboot to RAM.\r\n
#endif
-#if CONFIG_CBFS
+#if CONFIG_CBFS == 1
# if CONFIG_USE_FALLBACK_IMAGE == 1
str_coreboot_ram_name: .string fallback/coreboot_ram
# else
Modified: trunk/coreboot-v2/src/boot/elfboot.c
===
--- trunk/coreboot-v2/src/boot/elfboot.c2009-07-23 16:04:58 UTC (rev
4465)
+++ trunk/coreboot-v2/src/boot/elfboot.c2009-07-23 22:03:14 UTC (rev
4466)
@@ -107,11 +107,11 @@
* a machine, and implementing general relocation is hard.
*
* The solution:
- * - Allocate a buffer twice the size of the coreboot image.
- * - Anything that would overwrite coreboot copy into the lower half of
+ * - Allocate a buffer the size of the coreboot image plus additional
+ * required space.
+ * - Anything that would overwrite coreboot copy into the lower part of
* the buffer.
- * - After loading an ELF image copy coreboot to the upper half of the
- * buffer.
+ * - After loading an ELF image copy coreboot to the top of the buffer.
* - Then jump to the loaded image.
*
* Benefits:
Modified: trunk/coreboot-v2/src/boot/selfboot.c
===
--- trunk/coreboot-v2/src/boot/selfboot.c 2009-07-23 16:04:58 UTC (rev
4465)
+++ trunk/coreboot-v2/src/boot/selfboot.c 2009-07-23 22:03:14 UTC (rev
4466)
@@ -74,15 +74,13 @@
void * cbfs_load_payload(struct lb_memory *lb_mem, const char *name)
{
int selfboot(struct lb_memory *mem, struct cbfs_payload *payload);
- struct cbfs_payload *payload = (struct cbfs_payload *)
- cbfs_find_file(name, CBFS_TYPE_PAYLOAD);
+ struct cbfs_payload *payload;
- struct cbfs_payload_segment *segment, *first_segment;
-
+ payload = (struct cbfs_payload *)cbfs_find_file(name,
CBFS_TYPE_PAYLOAD);
if (payload == NULL)
return (void *) -1;
printk_debug(Got a payload\n);
- first_segment = segment = payload-segments;
+
selfboot(lb_mem, payload);
printk_emerg(SELFBOOT RETURNED!\n);
@@ -95,11 +93,11 @@
* a machine, and implementing general relocation is hard.
*
* The solution:
- * - Allocate a buffer twice the size of the coreboot image.
- * - Anything that would overwrite coreboot copy into the lower half of
+ * - Allocate a buffer the size of the coreboot image plus additional
+ * required space.
+ * - Anything that would overwrite coreboot copy into the lower part of
* the buffer.
- * - After loading an ELF image copy coreboot to the upper half of the
- * buffer.
+ * - After loading an ELF image copy coreboot to the top of the buffer.
* - Then jump to the loaded image.
*
* Benefits:
@@ -270,9 +268,9 @@
new-s_dstaddr,
new-s_dstaddr + new-s_filesz,
new-s_dstaddr + new-s_memsz);
- }
+ }
- /* Slice off a piece at the end
+ /* Slice off a piece at
