Re: [coreboot] abuild: building ROMs with payloads?
Cristi Magherusan schrieb: What do you think about enhancing abuild to optionally support building ROM images containing payloads? There's buildrom for that. If you only want to build a whole set of images with a single given payload, look at abuild's -p option. Also, I'm not sure if time is well spent on big enhancements to the current build infrastructure as it's supposed to be deprecated soonish. Patrick -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] abuild: building ROMs with payloads?
On Mon, 2009-07-27 at 09:16 +0200, Patrick Georgi wrote: Cristi Magherusan schrieb: What do you think about enhancing abuild to optionally support building ROM images containing payloads? There's buildrom for that. If you only want to build a whole set of images with a single given payload, look at abuild's -p option. Okay. Also, I'm not sure if time is well spent on big enhancements to the current build infrastructure as it's supposed to be deprecated soonish. Sure, I overlooked this aspect, but when the new buildsystem is in place it would be nice if we could do it so that the users will be able to try coreboot easier and get real functionality in a few seconds. Cristi -- Ing. Cristi Măgherușan, System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247 signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] IOAPIC Initialisation - How much do you have to do ??
Bit 7 of 48h is not set, to match Award, but I figured that this wouldn't make much difference anyway as this board is not using the FSB for interrupt delivery to the Local APIC. No harm in flipping the bit to see what hapens though. As far as I can tell the pin mux is all setup OK (58h[6] and also IOAPIC Rx3) As what are coming through are illegal vectors, I am thinking that something is generating interrupts before a handler is in place or a completely unhandled exception is being generated. If I change IOAPIC IRQ initialisation to have a vector in a legal range then the error changes The one thing that I haven't managed to get done properly is disabling the special cpu frequency change. While it's a long shot it may be that this is causing something wierd to happen. Think I'll have a closer read of the lapic spec too. Jon -Original Message- From: Rudolf Marek [mailto:r.ma...@assembler.cz] Sent: 24 July 2009 21:40 To: Harrison, Jon (SELEX GALILEO, UK) Cc: coreboot@coreboot.org Subject: Re: [coreboot] IOAPIC Initialisation - How much do you have to do ?? *** WARNING *** This message has originated outside your organisation, either from an external partner or the Global Internet. Keep this in mind if you answer this message. Harrison, Jon (SELEX GALILEO, UK) napsal(a): Sooo. I've added MPtables and masked IRQ0 from boot but still get APIC error on CPU0: 40(40) Hi, seems like I'm bit online ;) Check if bit 7 on 48h 7 APIC FSB Fixed at Low DW It changes how the APIC is delivered. Also if external bus is used, you will need to check the pin multiplexer/multifunction is setup correctly. Is there a kernel command line option that will turn on more verbose APIC output ? Yes but not help apic=debug maybe Rudolf SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England Wales. Company no. 02426132 This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] coreboot V2 with crypto library
Hi, for my Trusted Boot project with coreboot, I need to get the OpenSSL crypto library running with coreboot. I could get the modified elfboot.c compiled with the OpenSSL calls, but at the linking point with coreboot_ram.o it crashes because that has the option -nostdlibs. The library needs that standardlibs and without that option coreboot build will fail. Here is my actual gcc call: $(CC) $(DISTRO_LFLAGS) -nostdlib -nostartfiles -I /usr/include -L/usr/lib/ -lcrypto -lssl -static -o $@ -T $(TOP)/src/config/coreboot_ram.ld coreboot_ram.o Here is the output: gcc -m32 -Wl,--build-id=none -nostdlib -nostartfiles -I /usr/include -L/usr/lib/ -lcrypto -lssl -static -o coreboot_ram -T /home/sphinx/coreboot/coreboot_o/coreboot-v2/src/config/coreboot_ram.ld coreboot_ram.o coreboot_ram.o: In function `measure_elf': /home/sphinx/coreboot/coreboot_o/coreboot-v2//src/boot/elfboot.c:75: undefined reference to `EVP_sha256' /home/sphinx/coreboot/coreboot_o/coreboot-v2//src/boot/elfboot.c:75: undefined reference to `EVP_Digest' collect2: ld returned 1 exit status I need that stdlibs, without it can't find my library. Any chance how i could get this running? Regards, René -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] abuild: building ROMs with payloads?
On 7/27/09 4:59 AM, Cristi Magherusan wrote: Hello, What do you think about enhancing abuild to optionally support building ROM images containing payloads? That's possible with the current abuild. You can for example svn co svn://coreboot.org/testsystem/coreboot-payloads util/abuild/abuild -p $PWD/coreboot-payloads and abuild will run a script inside coreboot-payloads to find out which payload to add to a given mainboard. Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] IOAPIC Initialisation - How much do you have to do ??
Hi, Check the APIC bypass de assert message bit. 0x5b bit3 I think you need to put there 0. There are some registers from 0x70 - 0x7f documented in the Programming guide only. 0x7c bit 3 is hypetrtransport mode for APIC put 0 there. And 0x77 bit 5 I dont understand what exactly it is. Try flipping it too. Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] IOAPIC Initialisation - How much do you have to do ??
OK. Problem found. The IOAPIC IRQ0 setup was being zapped by some stuff I was trying to debug with! Timer now initialises OK, which makes me think that IRQs are now coming through OK. USB is now crapping out. I'll investigate further. -Original Message- From: Rudolf Marek [mailto:r.ma...@assembler.cz] Sent: 27 July 2009 13:07 To: Harrison, Jon (SELEX GALILEO, UK) Cc: coreboot@coreboot.org Subject: Re: [coreboot] IOAPIC Initialisation - How much do you have to do ?? *** WARNING *** This message has originated outside your organisation, either from an external partner or the Global Internet. Keep this in mind if you answer this message. Hi, Check the APIC bypass de assert message bit. 0x5b bit3 I think you need to put there 0. There are some registers from 0x70 - 0x7f documented in the Programming guide only. 0x7c bit 3 is hypetrtransport mode for APIC put 0 there. And 0x77 bit 5 I dont understand what exactly it is. Try flipping it too. Rudolf SELEX Sensors and Airborne Systems Limited Registered Office: Sigma House, Christopher Martin Road, Basildon, Essex SS14 3EL A company registered in England Wales. Company no. 02426132 This email and any attachments are confidential to the intended recipient and may also be privileged. If you are not the intended recipient please delete it from your system and notify the sender. You should not copy it or use it for any purpose nor disclose or distribute its contents to any other person. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Problem with objcopy: cannot generate coreboot.strip
ron minnich wrote: The cause of a 2^32 file can be that gcc has been upgraded and is generating new section names that are not covered in our ldscripts. I fixed this problem recently in another context. The new sections will get linked at address 0. I think your accidental 0 idea is correct. Can you do a readelf on the various coreboot files and look for a section name that is not in the ldscripts? ron Actually, I solved this by just making the BIOS a little bigger. Myles was right to be suspicious of the missing text sections as they were getting chopped off due to the BIOS not fitting in the space I alloted it in the Config.ld script. I just upped it from like 48k to 64k and it linked just fine. Thanks for your help though Ron! Take care, Jeffrey. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [patch] sb/via/k8t890: add vga textmode code for k8m890 chrome igp.
On Sun, Jul 26, 2009 at 02:21:34PM -0400, Kevin O'Connor wrote: On Thu, Jul 23, 2009 at 02:20:53PM +0200, Luc Verhaegen wrote: Add initialisation for the VIA Chrome 9 IGP on the k8m890 through native code and through the general vga infrastructure i committed a month or two ago. Add videoram_size option for k8m890 and the Asus M2V-MX SE. Now the Asus M2V-MX SE will magically come up with a working standard VGA 80x25 textmode. Hi Luc, With your code, will the SeaBIOS vgabios (make out/vgabios.bin) run on the board? -Kevin No; a general VGA bios is a broken concept to begin with. What you should know is that VGA is _not_ a standard, and one should never, ever try to change the mode without more detailed hw knowledge. It is only a standard through the int10 and vbe interfaces, where the manufacturers vga bios does all the vga and hw specific stuff for you. What such a general bios should do is find out, one way or another, what mode has been set and how to stuff things into the framebuffer. In this case: mode 3h: 80x25 with 8x16 fonts, with the framebuffer living at 0xB8000 and with vga standard cursor and fb offset handling. So a general int10 bios should find this out and then claim to only support this and absolutely nothing else. Everything else requires a whole bunch of hw specific code, and while you could spend the rest of your days porting graphics drivers from fb or X to this code, i think there are much better ways to spend ones time. Luc Verhaegen. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Problem jumping to Boot Loader
Hello again, Now that I've got my BIOS booting properly AFAICT, I am running into a problem when I jump to my Boot Loader. I get to the adjusted_boot_notes line, and then my Boot Loader is started, but it gets a memory map error that I don't understand and fails to load my menu.lst. This Boot Loader (FILO ver 0.5) works with an older version of CoreBoot (specifically a version from when it was called LinuxBIOS) but in my current build does not seem to work. You can see my full boot sequence at http://coreboot.pastebin.com/f4ebea109 -- the relevant lines start at line 1006: FILO version 0.5 (m...@mymachine.com) Wed Jul 15 13:14:58 EDT 2009 Can't get memory map from firmware. Using hardcoded default. Press Enter for default menu.lst (hda1:/filo/menu.lst), or Esc for prompt... 2 1 timed out menu: hda1:/filo/menu.lst Detected floating bus No drive detected on IDE channel 0 A proper boot should look like this: FILO version 0.5 (m...@mymachine.com) Sun Oct 19 14:32:35 EDT 2008 Press Enter for default menu.lst (hda1:/filo/menu.lst), or Esc for prompt... 2 1 timed out menu: hda1:/filo/menu.lst hda: LBA48 40GB: IC25N040ATMR04-0 hdb: ATAPI: MATSHITACD-RW CW-8124 Mounted ext2fs Has anyone experienced this before? Any ideas how to get FILO to recognize the mounted hardware? I'm guessing it's something I missed in my CoreBoot modifications since it clearly works in the older version. Thanks in advance, Jeffrey. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [patch] sb/via/k8t890: add vga textmode code for k8m890 chrome igp.
On Mon, Jul 27, 2009 at 04:06:45PM +0200, Luc Verhaegen wrote: No; a general VGA bios is a broken concept to begin with. What you should know is that VGA is _not_ a standard, and one should never, ever try to change the mode without more detailed hw knowledge. It is only a standard through the int10 and vbe interfaces, where the manufacturers vga bios does all the vga and hw specific stuff for you. What such a general bios should do is find out, one way or another, what mode has been set and how to stuff things into the framebuffer. In this case: mode 3h: 80x25 with 8x16 fonts, with the framebuffer living at 0xB8000 and with vga standard cursor and fb offset handling. So a general int10 bios should find this out and then claim to only support this and absolutely nothing else. Everything else requires a whole bunch of hw specific code, and while you could spend the rest of your days porting graphics drivers from fb or X to this code, i think there are much better ways to spend ones time. Luc Verhaegen. Let me further quantise this: It would be great if there was int10 infrastructure which would do just the above. * Seabios can show us its menu. * Grub will then give us its menu too. * The linux kernel will no longer think that it is talking to CGA and will use the correct fontsize while setting the cursor (so that we no longer get a floating cursor). Luc Verhaegen. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Problem jumping to Boot Loader
Jeffrey C. Jacobs schrieb: This Boot Loader (FILO ver 0.5) works with an older version of CoreBoot (specifically a version from when it was called LinuxBIOS) but in my current build does not seem to work. You can see my full boot sequence at http://coreboot.pastebin.com/f4ebea109 -- the relevant lines start at line 1006: FILO version 0.5 (m...@mymachine.com) Wed Jul 15 13:14:58 EDT 2009 Can't get memory map from firmware. Using hardcoded default. Update your FILO. coreboot now has the capability to move parts of its tables to high memory, and your FILO won't know about that. Regards, Patrick Georgi -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] abuild: building ROMs with payloads?
On Mon, Jul 27, 2009 at 4:57 AM, Stefan Reinauerste...@coresystems.de wrote: On 7/27/09 4:59 AM, Cristi Magherusan wrote: Hello, What do you think about enhancing abuild to optionally support building ROM images containing payloads? That's possible with the current abuild. You can for example svn co svn://coreboot.org/testsystem/coreboot-payloads util/abuild/abuild -p $PWD/coreboot-payloads and abuild will run a script inside coreboot-payloads to find out which payload to add to a given mainboard. Stefan sound like we need this question and answer on the wiki ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot V2 with crypto library
This is interesting, it's the second note today speculating that we need to compile with -lgcc. I think that's a bad approach, as we learned in the early days. It is too easy to link in libgcc code that expects a full OS environment and not realize you have done so. I think you should use the 'ar' tool to extract the .o files you need from libgcc and link against those. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot V2 with crypto library
On 27.07.2009 13:01, René Reuter wrote: for my Trusted Boot project with coreboot, I need to get the OpenSSL crypto library running with coreboot. I could get the modified elfboot.c compiled with the OpenSSL calls, but at the linking point with coreboot_ram.o it crashes because that has the option -nostdlibs. The library needs that standardlibs and without that option coreboot build will fail. Here is the output: gcc -m32 -Wl,--build-id=none -nostdlib -nostartfiles -I /usr/include -L/usr/lib/ -lcrypto -lssl -static -o coreboot_ram -T /home/sphinx/coreboot/coreboot_o/coreboot-v2/src/config/coreboot_ram.ld coreboot_ram.o coreboot_ram.o: In function `measure_elf': /home/sphinx/coreboot/coreboot_o/coreboot-v2//src/boot/elfboot.c:75: undefined reference to `EVP_sha256' /home/sphinx/coreboot/coreboot_o/coreboot-v2//src/boot/elfboot.c:75: undefined reference to `EVP_Digest' collect2: ld returned 1 exit status I need that stdlibs, without it can't find my library. No, stdlibs will not help. Your problem is that libcrypto is not linked in. Any chance how i could get this running? Make sure libcrypto gets linked in. Hint: with the paths you provided, it is very unlikely you get the right libcrypto. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] option rom problems with DBM690T+VT6202L
Hi all, Since DBM690T does not have UHCI controller, i bought an PCI-USB card which contained two UHCI controller. But It always caused rebooting when the option rom try to initialize the controller. I attached all of the messages, and looking for some help. Until now my doubt is the real bus/dev/func is 06/05/01, but while seabios search it as 00/05/01. -- Jason Wang Peking University coreboot-2.0.0-r4253M Tue Jul 28 03:50:01 CST 2009 starting... bsp_apicid=0x0 core0 started: 01SBLink=00 NC node|link=00 rs690_early_setup() get_cpu_rev EAX=0x60f82. CPU Rev is K8_G0. NB Revision is A12. k8_optimization() rs690_por_init sb600_early_setup() sb600_devices_por_init() sb600_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is 0x13 sb600_devices_por_init(): IDE Device, BDF:0-20-1 sb600_devices_por_init(): LPC Device, BDF:0-20-3 sb600_devices_por_init(): P2P Bridge, BDF:0-20-4 sb600_devices_por_init(): SATA Device, BDF:0-18-0 sb600_pmio_por_init() begin msr fid, vid: hi=0x32111e1e, lo=0x110d Current fid_cur: 0x0, fid_max: 0xd Requested fid_new: 0xd FidVid table step fidvid: 0xa 200MHZ step fidvid: 0xc 100MHZ step fidvid: 0xd end msr fid, vid: hi=0x32111e11, lo=0x110d000d needs_reset=0x1 ht reset - coreboot-2.0.0-r4253M Tue Jul 28 03:50:01 CST 2009 starting... bsp_apicid=0x0 core0 started: 01SBLink=00 NC node|link=00 rs690_early_setup() get_cpu_rev EAX=0x60f82. CPU Rev is K8_G0. NB Revision is A12. k8_optimization() rs690_por_init sb600_early_setup() sb600_devices_por_init() sb600_devices_por_init(): SMBus Device, BDF:0-20-0 SMBus controller enabled, sb revision is 0x13 sb600_devices_por_init(): IDE Device, BDF:0-20-1 sb600_devices_por_init(): LPC Device, BDF:0-20-3 sb600_devices_por_init(): P2P Bridge, BDF:0-20-4 sb600_devices_por_init(): SATA Device, BDF:0-18-0 sb600_pmio_por_init() begin msr fid, vid: hi=0x32111e11, lo=0x110d000d end msr fid, vid: hi=0x32111e11, lo=0x110d000d needs_reset=0x0 sysinfo-nodes: 1 sysinfo-ctrl: cf188 spd_addr: a348 Ram1.00 Ram2.00 sdram_set_spd_registers: paramx :000cece4 Unbuffered 400MHz 400MHz RAM: 0x0010 kB Ram3 sdram_enable: tsc0[8]: 000ceda4Initializing memory: done Setting variable MTRR 2, base:0MB, range: 1024MB, type WB DQS Training:RcvrEn:Pass1: 00 CTLRMaxDelay=14 done DQS Training:DQSPos: 00 TrainDQSRdWrPos: buf_a:000ce870 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 TrainDQSPos: MutualCSPassW[48] :000ce754 done DQS Training:RcvrEn:Pass2: 00 CTLRMaxDelay=2c done DQS SAVE NVRAM: c2000 DQS Training:tsc[00]=18222dc5 DQS Training:tsc[01]=193b8b80 DQS Training:tsc[02]=1942bccb DQS Training:tsc[03]=3adbbca0 DQS Training:tsc[04]=3c135061 Ram4 v_esp=000cee78 testx = 5a5a5a5a Copying data from cache to RAM -- switching to use RAM as stack... Done testx = 5a5a5a5a Disabling cache as ram now Clearing initial memory region: Done Uncompressing image to RAM. Jumping to image. coreboot-2.0.0-r4253M Tue Jul 28 03:50:01 CST 2009 booting... Enumerating buses... Mainboard DBM690T Enable. dev=0x00025690 dbm690t_enable, TOP MEM: msr.lo = 0x4000, msr.hi = 0x dbm690t_enable, TOP MEM2: msr2.lo = 0x, msr2.hi = 0x dbm690t_enable: uma size 0x0800, memory start 0x3800 enable_onboard_nic. Init adt7461 end , status 0x02 00 APIC_CLUSTER: 0 enabled PCI_DOMAIN: enabled PCI: 00:18.3 siblings=1 CPU: APIC: 00 enabled CPU: APIC: 01 enabled PCI: pci_scan_bus for bus 00 PCI: 00:18.0 [1022/1100] enabled PCI: 00:18.1 [1022/1101] enabled PCI: 00:18.2 [1022/1102] enabled PCI: 00:18.3 [1022/1103] enabled rs690_enable: dev=00027908, VID_DID=0x79101002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3() gpp_sb_init nb_dev=0x00027908, dev=0x00029b68, port=0x8 PCI: 00:00.0 [1002/7910] enabled PCI: 00:00.0 [1002/7910] enabled next_unitid: 0015 PCI: pci_scan_bus for bus 00 rs690_enable: dev=00027908, VID_DID=0x79101002 Bus-0, Dev-0, Fun-0. enable_pcie_bar3() gpp_sb_init nb_dev=0x00027908, dev=0x00029b68, port=0x8 PCI: 00:00.0 [1002/7910] enabled rs690_enable: dev=00027d54, VID_DID=0x79121002 Bus-0, Dev-1, Fun-0. PCI: 00:01.0 [1002/7912] enabled rs690_enable: dev=000281a0, VID_DID=0x79131002 Bus-0, Dev-2,3, Fun-0. enable=1 rs690_gfx_init, nb_dev=0x00027908, dev=0x000281a0, port=0x2. rs690_gfx_init step0. rs690_gfx_init step1. rs690_gfx_init step2. rs690_gfx_init step4. rs690_gfx_init step8.1. rs690_gfx_init step8.2. rs690_gfx_init step8.3. rs690_gfx_init step8.4. rs690_gfx_init step8.5. rs690_gfx_init
Re: [coreboot] coreboot V2 with crypto library
On 7/27/09 5:22 PM, ron minnich wrote: This is interesting, it's the second note today speculating that we need to compile with -lgcc. Which is especially weird since we link against libgcc already. I think that's a bad approach, as we learned in the early days. It is too easy to link in libgcc code that expects a full OS environment and not realize you have done so. Yes, we should drop libgcc linking, but x86emu wants it for the 64bit division, too.. René, interesting approach.. Are you checking signatures of the payload? Out of curiosity .. Is there a reason why the signature checking is not done in the payload itself? That might be easier... There's a grub2 version out there that we made a year or two ago that does signature checking of binaries. Back then we skipped checking the payload, since if it's possible to exchange the payload, it's possible to exchange the rest of the rom code too, in many cases. Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] option rom problems with DBM690T+VT6202L
oh... i find libpaylod usb stack hard code the bus to 0. it should display the bus number. On Mon, Jul 27, 2009 at 11:42 PM, Jason Wang wangqing...@gmail.com wrote: Hi all, Since DBM690T does not have UHCI controller, i bought an PCI-USB card which contained two UHCI controller. But It always caused rebooting when the option rom try to initialize the controller. I attached all of the messages, and looking for some help. Until now my doubt is the real bus/dev/func is 06/05/01, but while seabios search it as 00/05/01. -- Jason Wang Peking University -- Jason Wang Peking University -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot V2 with crypto library
René Reuter wrote: for my Trusted Boot project with coreboot, I need to get the OpenSSL crypto library running with coreboot. Are you really sure? There are a couple of other crypto libraries which might be easier to use in a coreboot setting. Look at LibTom[1] and cryptlib[2] for example. //Peter [1] Unmaintained since 6+ months, the PD code is available at http://home.libtom.org/lt_tree.tar.bz2 [2] http://www.cs.auckland.ac.nz/~pgut001/cryptlib/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] coreboot V2 with crypto library
On Mon, Jul 27, 2009 at 8:49 AM, Stefan Reinauerste...@coresystems.de wrote: On 7/27/09 5:22 PM, ron minnich wrote: This is interesting, it's the second note today speculating that we need to compile with -lgcc. Which is especially weird since we link against libgcc already. ow. I have not been paying attention again. I thought we did the nostdlibs thing. Sorry. Yes, we should drop libgcc linking, but x86emu wants it for the 64bit division, too.. oops. Missed that. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] non static 0x1000 IO space can be broken | (EP80579) Addition
From: Arnaud Maye [mailto:arnaud.m...@4dsp.com] Hello Gents, I've been on IRC for a GFX output issue on Friday. Actually the output is always black or full of non sense square on the screen. I have tried two graphic cards and in this respect it is fair to point the issue outside of the vgarom. The odd thing is that the PCI card am using having some IOs below 0x1000. A few other peripherals are there as well. I have attached the complete log. I am having an issue with seabios and the keyboard input.. this is part of the log as well. ... Setting resources... PCI_DOMAIN: allocate_resources_io: base:1000 size:2428 align:12 gran:0 limit: Assigned: PCI: 00:03.0 1c * [0x1000 - 0x1fff] io Assigned: PCI: 00:04.0 1c * [0x2000 - 0x2fff] io Assigned: PCI: 00:1f.0 40 * [0x3000 - 0x307f] io Assigned: PCI: 00:1f.0 48 * [0x3080 - 0x30bf] io Assigned: PCI: 00:1d.0 20 * [0x30c0 - 0x30df] io Assigned: PCI: 00:1f.3 20 * [0x30e0 - 0x30ff] io Should we not see there all the resources below 0x1000? PCI: 07:00.0 is my PCIe graphic card (PCI: 07:00.0 24 * [0x0 - 0x7f] io). You won't see all of the fixed regions in the allocator. The allocator only handles regions that can be moved. Legacy ports like VGA that are fixed are included in the 0x0 - 0x1000 fixed region in the southbridge. Your allocations look fine. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] utililty output for Asus A7V133C
Dear Corebootmembers,
herewith I submit outputs of flasrom, dmidecode, lspci and superiotool
for my motherboards at hand.
{
flashrom -V flashrom-V.txt
lspci -nnvvv lspci-nnvvv.txt
superiotool -edV superiotool-edV.txt
dmidecode dmidecode.txt
}
Is there any database|wiki which stores this data? Is an automatic
system to gather and show these data useful?
[Motherboard|Chipsets|IO|whatever needed]
I'm splitting the information over seperate emails.
Regards,
Joachim Ernst
# dmidecode 2.9
SMBIOS 2.3 present.
49 structures occupying 1397 bytes.
Table at 0x000F2940.
Handle 0x, DMI type 0, 20 bytes
BIOS Information
Vendor: Award Software, Inc.
Version: ASUS A7V133-C ACPI BIOS Revision 1010 Beta 001-B
Release Date: 02/11/2003
Address: 0xF
Runtime Size: 64 kB
ROM Size: 256 kB
Characteristics:
PCI is supported
PNP is supported
APM is supported
BIOS is upgradeable
BIOS shadowing is allowed
ESCD support is available
Boot from CD is supported
Selectable boot is supported
BIOS ROM is socketed
EDD is supported
5.25/360 KB floppy services are supported (int 13h)
5.25/1.2 MB floppy services are supported (int 13h)
3.5/720 KB floppy services are supported (int 13h)
3.5/2.88 MB floppy services are supported (int 13h)
Print screen service is supported (int 5h)
8042 keyboard services are supported (int 9h)
Serial services are supported (int 14h)
Printer services are supported (int 17h)
CGA/mono video services are supported (int 10h)
ACPI is supported
USB legacy is supported
AGP is supported
Handle 0x0001, DMI type 1, 25 bytes
System Information
Manufacturer: System Manufacturer
Product Name: System Name
Version: System Version
Serial Number: SYS-1234567890
UUID: Not Settable
Wake-up Type: Power Switch
Handle 0x0002, DMI type 2, 8 bytes
Base Board Information
Manufacturer: ASUSTeK Computer INC.
Product Name: A7V133-C
Version: REV 1.xx
Serial Number: xxx
Handle 0x0003, DMI type 3, 17 bytes
Chassis Information
Manufacturer: Chassis Manufacture
Type: Tower
Lock: Not Present
Version: Chassis Version
Serial Number: Chassis Serial Number
Asset Tag: Asset-1234567890
Boot-up State: Safe
Power Supply State: Safe
Thermal State: Safe
Security Status: Unknown
OEM Information: 0x
Handle 0x0004, DMI type 4, 32 bytes
Processor Information
Socket Designation: SOCKET A
Type: Central Processor
Family: Other
Manufacturer: AuthenticAMD
ID: 62 06 00 00 FF F9 83 03
Signature: Family 6, Model 6, Stepping 2
Flags:
FPU (Floating-point unit on-chip)
VME (Virtual mode extension)
DE (Debugging extension)
PSE (Page size extension)
TSC (Time stamp counter)
MSR (Model specific registers)
PAE (Physical address extension)
MCE (Machine check exception)
CX8 (CMPXCHG8 instruction supported)
SEP (Fast system call)
MTRR (Memory type range registers)
PGE (Page global enable)
MCA (Machine check architecture)
CMOV (Conditional move instruction supported)
PAT (Page attribute table)
PSE-36 (36-bit page size extension)
MMX (MMX technology supported)
FXSR (Fast floating-point save and restore)
SSE (Streaming SIMD extensions)
Version: AMD Athlon(TM) XP Processor
Voltage: 1.7 V
External Clock: 100 MHz
Max Speed: 1800 MHz
Current Speed: 1100 MHz
Status: Populated, Enabled
Upgrade: Other
L1 Cache Handle: 0x0009
L2 Cache Handle: 0x000A
L3 Cache Handle: Not Provided
Handle 0x0005, DMI type 5, 22 bytes
Memory Controller Information
Error Detecting Method: 64-bit ECC
Error Correcting Capabilities:
None
Supported Interleave: One-way Interleave
Current Interleave: One-way Interleave
Maximum Memory Module Size: 1024 MB
Maximum Total Memory Size: 3072 MB
Supported Speeds:
Other
Supported Memory Types:
Other
DIMM
SDRAM
Memory Module Voltage: 3.3 V
Associated Memory Slots: 3
0x0006
0x0007
0x0008
Enabled Error Correcting Capabilities:
[coreboot] utililty output for Asus K7V
# dmidecode 2.9 SMBIOS 2.3 present. 48 structures occupying 1356 bytes. Table at 0x000F2750. Handle 0x, DMI type 0, 20 bytes BIOS Information Vendor: Award Software, Inc. Version: ASUS K7V ACPI BIOS Revision 1008 Beta 001-D Release Date: 11/22/2000 Address: 0xF Runtime Size: 64 kB ROM Size: 256 kB Characteristics: PCI is supported PNP is supported APM is supported BIOS is upgradeable BIOS shadowing is allowed ESCD support is available Boot from CD is supported Selectable boot is supported BIOS ROM is socketed EDD is supported 5.25/360 KB floppy services are supported (int 13h) 5.25/1.2 MB floppy services are supported (int 13h) 3.5/720 KB floppy services are supported (int 13h) 3.5/2.88 MB floppy services are supported (int 13h) Print screen service is supported (int 5h) 8042 keyboard services are supported (int 9h) Serial services are supported (int 14h) Printer services are supported (int 17h) CGA/mono video services are supported (int 10h) ACPI is supported USB legacy is supported AGP is supported Handle 0x0001, DMI type 1, 25 bytes System Information Manufacturer: System Manufacturer Product Name: System Name Version: System Version Serial Number: SYS-1234567890 UUID: Not Settable Wake-up Type: Power Switch Handle 0x0002, DMI type 2, 8 bytes Base Board Information Manufacturer: ASUSTeK Computer INC. Product Name: K7V Version: REV 1.xx Serial Number: xxx Handle 0x0003, DMI type 3, 17 bytes Chassis Information Manufacturer: Chassis Manufacture Type: Tower Lock: Not Present Version: Chassis Version Serial Number: Chassis Serial Number Asset Tag: Asset-1234567890 Boot-up State: Safe Power Supply State: Safe Thermal State: Safe Security Status: Unknown OEM Information: 0x Handle 0x0004, DMI type 4, 32 bytes Processor Information Socket Designation: SLOT A Type: Central Processor Family: Other Manufacturer: AuthenticAMD ID: 42 06 00 00 FF F9 83 01 Signature: Family 6, Model 4, Stepping 2 Flags: FPU (Floating-point unit on-chip) VME (Virtual mode extension) DE (Debugging extension) PSE (Page size extension) TSC (Time stamp counter) MSR (Model specific registers) PAE (Physical address extension) MCE (Machine check exception) CX8 (CMPXCHG8 instruction supported) SEP (Fast system call) MTRR (Memory type range registers) PGE (Page global enable) MCA (Machine check architecture) CMOV (Conditional move instruction supported) PAT (Page attribute table) PSE-36 (36-bit page size extension) MMX (MMX technology supported) FXSR (Fast floating-point save and restore) Version: AMD Athlon(TM) Processor Voltage: 2.9 V External Clock: 100 MHz Max Speed: 1200 MHz Current Speed: 700 MHz Status: Populated, Enabled Upgrade: Other L1 Cache Handle: 0x0009 L2 Cache Handle: 0x000A L3 Cache Handle: Not Provided Handle 0x0005, DMI type 5, 22 bytes Memory Controller Information Error Detecting Method: 64-bit ECC Error Correcting Capabilities: None Supported Interleave: One-way Interleave Current Interleave: One-way Interleave Maximum Memory Module Size: 1024 MB Maximum Total Memory Size: 3072 MB Supported Speeds: Other Supported Memory Types: Other DIMM SDRAM Memory Module Voltage: 3.3 V Associated Memory Slots: 3 0x0006 0x0007 0x0008 Enabled Error Correcting Capabilities: Unknown Handle 0x0006, DMI type 6, 12 bytes Memory Module Information Socket Designation: DIMM 1 Bank Connections: 0 1 Current Speed: Unknown Type: Other DIMM SDRAM Installed Size: 256 MB (Single-bank Connection) Enabled Size: 256 MB (Single-bank Connection) Error Status: OK Handle 0x0007, DMI type 6, 12 bytes Memory Module Information Socket Designation: DIMM 2 Bank Connections: 2 3 Current Speed: Unknown Type: Other DIMM SDRAM
[coreboot] utililty output for Dell OptiPlex GX1 266L+
# dmidecode 2.9 SMBIOS 2.2 present. 64 structures occupying 2017 bytes. Table at 0x000FB5D0. Handle 0xDA00, DMI type 218, 77 bytes OEM-specific Type Header and Data: DA 4D 00 DA B2 00 17 03 00 30 00 00 80 00 80 01 00 02 80 02 80 01 00 00 A0 00 A0 01 00 05 80 05 80 01 00 00 F1 00 F1 00 00 01 F1 01 F1 00 00 07 F1 07 F1 00 00 08 F1 08 F1 00 00 10 FE 10 FE 00 00 20 FC 20 FC 00 00 FF FF 00 00 00 00 Handle 0x, DMI type 0, 19 bytes BIOS Information Vendor: Dell Computer Corporation Version: A01 Release Date: 05/11/98 Address: 0xF Runtime Size: 64 kB ROM Size: 256 kB Characteristics: ISA is supported PCI is supported PNP is supported APM is supported BIOS is upgradeable BIOS shadowing is allowed ESCD support is available Boot from CD is supported Selectable boot is supported EDD is supported Japanese floppy for Toshiba 1.2 MB is supported (int 13h) 5.25/360 KB floppy services are supported (int 13h) 5.25/1.2 MB floppy services are supported (int 13h) 3.5/720 KB floppy services are supported (int 13h) 3.5/2.88 MB floppy services are supported (int 13h) Print screen service is supported (int 5h) 8042 keyboard services are supported (int 9h) Serial services are supported (int 14h) Printer services are supported (int 17h) CGA/mono video services are supported (int 10h) AGP is supported Handle 0x0100, DMI type 1, 25 bytes System Information Manufacturer: Dell Computer Corporation Product Name: OptiPlex GX1 266L+ Version: Not Specified Serial Number: Not Specified UUID: 4E42364F-C080-5A80-5A10-82004C4C4544 Wake-up Type: Power Switch Handle 0x0300, DMI type 3, 13 bytes Chassis Information Manufacturer: Dell Computer Corporation Type: Low Profile Desktop Lock: Not Present Version: Not Specified Serial Number: NB6ZZ Asset Tag: Not Specified Boot-up State: Warning Power Supply State: Safe Thermal State: Safe Security Status: Unknown Handle 0x0400, DMI type 4, 32 bytes Processor Information Socket Designation: Microprocessor Type: Central Processor Family: Pentium II Manufacturer: Intel ID: 34 06 00 00 FF F9 80 00 Signature: Type 0, Family 6, Model 3, Stepping 4 Flags: FPU (Floating-point unit on-chip) VME (Virtual mode extension) DE (Debugging extension) PSE (Page size extension) TSC (Time stamp counter) MSR (Model specific registers) PAE (Physical address extension) MCE (Machine check exception) CX8 (CMPXCHG8 instruction supported) SEP (Fast system call) MTRR (Memory type range registers) PGE (Page global enable) MCA (Machine check architecture) CMOV (Conditional move instruction supported) MMX (MMX technology supported) Version: Not Specified Voltage: 3.3 V External Clock: 66 MHz Max Speed: 450 MHz Current Speed: 266 MHz Status: Populated, Enabled Upgrade: Slot 1 L1 Cache Handle: 0x0700 L2 Cache Handle: 0x0701 L3 Cache Handle: No L3 Cache Handle 0x0700, DMI type 7, 19 bytes Cache Information Socket Designation: Not Specified Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Unknown Location: Internal Installed Size: 32 KB Maximum Size: 32 KB Supported SRAM Types: Unknown Installed SRAM Type: Unknown Speed: Unknown Error Correction Type: Single-bit ECC System Type: Unified Associativity: Unknown Handle 0x0701, DMI type 7, 19 bytes Cache Information Socket Designation: Not Specified Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Write Back Location: External Installed Size: 512 KB Maximum Size: 512 KB Supported SRAM Types: Pipeline Burst Synchronous Installed SRAM Type: Pipeline Burst Synchronous Speed: Unknown Error Correction Type: Single-bit ECC System Type: Unified Associativity: 4-way Set-associative Handle 0x0800, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: PARALLEL Internal Connector Type: None External
[coreboot] utililty output for Gigabyte GA-686BXD
# dmidecode 2.9 Legacy DMI 2.0 present. 29 structures occupying 688 bytes. Table at 0x000F0800. Handle 0x, DMI type 0, 18 bytes BIOS Information Vendor: Award Software International, Inc. Version: 4.51 PG Release Date: 05/13/98 Address: 0xE Runtime Size: 128 kB ROM Size: 256 kB Characteristics: ISA is supported PCI is supported PNP is supported APM is supported BIOS is upgradeable BIOS shadowing is allowed ESCD support is available Boot from CD is supported Selectable boot is supported BIOS ROM is socketed EDD is supported 5.25/360 KB floppy services are supported (int 13h) 5.25/1.2 MB floppy services are supported (int 13h) 3.5/720 KB floppy services are supported (int 13h) 3.5/2.88 MB floppy services are supported (int 13h) Print screen service is supported (int 5h) 8042 keyboard services are supported (int 9h) Serial services are supported (int 14h) Printer services are supported (int 17h) CGA/mono video services are supported (int 10h) Handle 0x0001, DMI type 1, 8 bytes System Information Manufacturer: Product Name: Version: Serial Number: Handle 0x0002, DMI type 2, 8 bytes Base Board Information Manufacturer: Gigabyte Technology Co. Ltd. Product Name: i440BX-W977 Version: Serial Number: Handle 0x0003, DMI type 3, 9 bytes Chassis Information Manufacturer: Type: Unknown Lock: Not Present Version: Serial Number: Asset Tag: Handle 0x0004, DMI type 5, 23 bytes Memory Controller Information Error Detecting Method: 8-bit Parity Error Correcting Capabilities: None Supported Interleave: One-way Interleave Current Interleave: One-way Interleave Maximum Memory Module Size: 32 MB Maximum Total Memory Size: 128 MB Supported Speeds: 70 ns 60 ns Supported Memory Types: EDO SDRAM Memory Module Voltage: 3.3 V Associated Memory Slots: 4 0x0005 0x0006 0x0007 0x0008 Handle 0x0006, DMI type 6, 12 bytes Memory Module Information Socket Designation: DIMM1 Bank Connections: 2 3 Current Speed: 50 ns Type: DIMM SDRAM Installed Size: Not Installed Enabled Size: Not Installed Error Status: OK Handle 0x0007, DMI type 6, 12 bytes Memory Module Information Socket Designation: DIMM2 Bank Connections: 4 5 Current Speed: 50 ns Type: DIMM SDRAM Installed Size: 64 MB (Single-bank Connection) Enabled Size: 64 MB (Single-bank Connection) Error Status: OK Handle 0x0008, DMI type 6, 12 bytes Memory Module Information Socket Designation: DIMM3 Bank Connections: 6 7 Current Speed: 50 ns Type: DIMM SDRAM Installed Size: 64 MB (Single-bank Connection) Enabled Size: 64 MB (Single-bank Connection) Error Status: OK Handle 0x0009, DMI type 7, 15 bytes Cache Information Socket Designation: Internal Cache Configuration: Enabled, Not Socketed, Level 1 Operational Mode: Write Back Location: Internal Installed Size: 32 KB Maximum Size: 32 KB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Handle 0x000A, DMI type 7, 15 bytes Cache Information Socket Designation: External Cache Configuration: Enabled, Not Socketed, Level 2 Operational Mode: Write Back Location: External Installed Size: 512 KB Maximum Size: 512 KB Supported SRAM Types: Synchronous Installed SRAM Type: Synchronous Handle 0x000B, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: PRIMARY IDE Internal Connector Type: On Board IDE External Reference Designator: External Connector Type: None Port Type: Other Handle 0x000C, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: SECONDARY IDE Internal Connector Type: On Board IDE External Reference Designator: External Connector Type: None Port Type: Other Handle 0x000D, DMI type 8, 9 bytes Port Connector Information Internal Reference Designator: FDD Internal Connector Type: On Board Floppy External Reference Designator: External Connector Type: None Port Type: 8251 FIFO Compatible Handle
Re: [coreboot] utililty output for Asus A7V133C
Hi Joachim, thanks for your reports. Could you please rerun latest flashrom compiled from subversion (revision 667) on all these boards and mail the output to flash...@flashrom.org Thanks! Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] option rom problems with DBM690T+VT6202L
On Mon, Jul 27, 2009 at 11:42:18PM +0800, Jason Wang wrote: Hi all, Since DBM690T does not have UHCI controller, i bought an PCI-USB card which contained two UHCI controller. But It always caused rebooting when the option rom try to initialize the controller. I attached all of the messages, and looking for some help. Until now my doubt is the real bus/dev/func is 06/05/01, but while seabios search it as 00/05/01. Please post a log with the seabios debug level set to 6. -Kevin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Qemu-target ROM freeze/crash with current v2 HEAD (CBFS-enabled)
Hello, I'm getting this output when running a qemu ROM compiled using latest v2 tree, and my AVATT payload - with KVM support in qemu/kernel it freezes, and without, it crashes: Crash: http://pastebin.com/m830348a The freeze occurs just after the Jumping to boot code at 1 message is displayed. If anyone has a clue, please help me. Thanks, Cristi -- Ing. Cristi Măgherușan, System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247 signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4472 - trunk/coreboot-v2/src/mainboard/supermicro/h8dmr
Author: ward Date: 2009-07-28 03:23:32 +0200 (Tue, 28 Jul 2009) New Revision: 4472 Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb Log: Fix erroneous comment in src/mainboard/h8dmr/Options.lb This is a trivial patch. Signed-off-by: Ward Vandewege w...@gnu.org Acked-by: Ward Vandewege w...@gnu.org Modified: trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb === --- trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2009-07-27 20:51:30 UTC (rev 4471) +++ trunk/coreboot-v2/src/mainboard/supermicro/h8dmr/Options.lb 2009-07-28 01:23:32 UTC (rev 4472) @@ -332,7 +332,7 @@ ## WARNING5 warning conditions ## NOTICE 6 normal but significant condition ## INFO 7 informational -## CONFIG_DEBUG 8 debug-level messages +## DEBUG 8 debug-level messages ## SPEW 9 Way too many details ## Request this level of debugging output -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [GSoC] Qemu-target ROM freeze/crash with current v2 HEAD (CBFS-enabled)
On Mon, Jul 27, 2009 at 4:42 PM, Cristi Magherusancristi.magheru...@net.utcluj.ro wrote: Hello, I'm getting this output when running a qemu ROM compiled using latest v2 tree, and my AVATT payload - with KVM support in qemu/kernel it freezes, and without, it crashes: Crash: http://pastebin.com/m830348a The freeze occurs just after the Jumping to boot code at 1 message is displayed. I'd still like to know why it's going to 1. That is not what I ever used when I had a LAB payload. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] seabios head breaking irqs?
Hi Kevin et al, I just tried seabios head on my h8dmr fam10 system, and got rather odd results - suddenly I am seeing irq problems. I was using a seabios checkout from 20090701 before, which shows no issues. Here are boot logs: Not OK: http://ward.vandewege.net/coreboot/h8dmr/fam10/h8dmr-gf.cap OK: http://ward.vandewege.net/coreboot/h8dmr/fam10/h8dmr-gg.cap I'm not sure if this could be caused by seabios, or if perhaps it's yet another toolchain problem. When reverting to the older seabios, the irq problems went away again. Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
