Re: [coreboot] mkelfimage with CBFS?
On Sun, 2009-08-09 at 15:01 -0700, ron minnich wrote: You should not need mkelfimage, and have not needed it for a long time. I'll take a look at those images. ron Hello, I just noticed something interesting... The ROM with CBFS with vmlinux included (without using mkelfImage) seems to boot, or at least gets loaded by cbfs. After the VGA BIOS runs, the emulator shows up some kernel messages that appear when hardware discovery is performed (printed over of those of the VGA BIOS) but then it seems to hang, and the CPU is at 100% like in an infinite loop which looks much like a kernel panic. It seems there's smoething wrong in my kernel config, I'll check it again.. Cristi -- Ing. Cristi Măgherușan, System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247 signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Tyan S2912[Fam10] HTX problem
Hi all,
I am trying to get an HTX plug in card running on a Tyan S2912 Fam10 System.
I tried both Barcelona and Shanghai CPUs and both system setups ended
booting
during PCI scanning.
I am not familiar with the PCI subsystem and the procedures of coreboot
regarding
this matter, but when scanning through the code, I do not even see why
the last
line is printed out twice whereas the procedure including the printout
only gets called
once with the specified parameters. Does anyone have an idea where I
could start
searching for a possible solution to my problem.
Thanks for the help in advance,
Maximilian Thuermer
coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 15:51:58 CEST 2009
starting...
BSP Family_Model: 00100f42
*sysinfo range: [000cc000,000cdfa0]
bsp_apicid = 00
cpu_init_detectedx =
microcode: rev id not found. Skipping microcode patch!
cpuSetAMDMSR done
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 05
event: 1004
data: 04 00 00 01
AMD_CB_ManualBUIDSwapList()
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 02 ff
Exit amd_ht_init()
cpuSetAMDPCI 00
On node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0,
link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 e
cpuSetAMDPCI 01
On node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1,
link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1, link 0 e
Prep FID/VID Node:00
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c3310f24
F3xD8: 03000916
F3xDC: 5334
Prep FID/VID Node:01
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c3310f24
F3xD8: 03000916
F3xDC: 5334
setup_remote_node: 01 done
Start node 01 done.
Wait all core0s started
Core0 started on node: 01
Wait all core0s started done
start_other_cores()
init node: 00 cores: 03
Start other core - nodeid: 00 cores: 03
init node: 01 cores: 03
reexx other core - nodeid: 01 cores:cco0coorr3e
-: x::s t: a r- t--e-d - { { a { p A A
aPPApIIPCiCIIcICiDDI d D =:= = F000o12 u 3 NnNONdODO DDE3EIEI IDDD w =
=or =x
:
0rroo2o1---mm--Pm-i -ii-cc cs- trr{{r o{aooc crc
toAoAoPdAedPdIeIePde::C:C:II C I DrDrIr01e e eD v=vv=A P = ii i
ddsdc8 t 410
oo 3}}ccc}
pp odB-ddee-ee -- g-ip
na
Vccrrtt cccFhhhImmmi!Dii!!
r
n!8!nd dDoopp ccpououuModSSdSdSRee:t:t:t 0A A A
rMrxMrMeDeDecDM0vMvMv SS0 S iRiiRR1d 0 dd 0 7nnnooo1tt tF F0I dI
fXxXffoooM0Monn
coctcoawd 0.C0.C.i P P0nSiU0SUSk kt 3kiV
iVi_fe0perpirxis4isidnvni0nigogigo0 n3 n dm_m 6m
iuiaiu04ncncpcr(r0krkonoso no
is owodnddgnF ee Iee o1 oDVrppr)pa I aa ttntaDnc ococphihotht! !c!n
d
Bu
teettPetpcccpPpp ppuuo,uo01rSSr SAte
SMiMedFAAIdAM!!IMMCDD_D DM
S
! ISdR:RRDFF IIXXo0MM0nEE
eV ! FFAIPdC IoPCXX:MUPM ne0E UE!!1V
CC
nw awnongnsnUiUsiBtS o i_PVnVoe enfufr irsiudsnndvikii onokn=onndw o_
u1waunn0pn n(7kok n0rnos 0orto
tgrn1tote F1t ooos rru) s n unudapnop ppo3piottcor
trsswiutuodeper:dpkd !ppc! ooi
e
MVeFFcdIdFIo!X!I rM XDEe
sEI
o!! D FFIIC o XPCnoXPU nMM Un EEA o!!VdV ePCeCr:ePrs Pisc0UU1i
ene VVn
t Wra rusniusiiktnokon nfnno woo uunrwnnn kA konPonro rowwns nnnot
ao to gtorrse s u n1unpop:potto p raosrstpu_tuepdaeppp!pdo!o irc r
teed
En FddI !dX=! oM
e!
FFIIC
ng ko PrXXiMMUenEi aE!!tVd b _eCraCfPscPiUdikU vo V=Vine
edr_u1rssan0i1ipkon0o(nso7n tw0uuan1n
eauppken1r noo) cwow nnomna ptm ooi ornrcs u_ indpfno:piott od (
0rstps3u
drttVdcpkpF!o eoIrD
n0E )e eIF=IdDd! X! o1M
!
PX: 70 FA dCIP0o
ie UMnE e0W!aV
C
r tri sPnifiUtoo V_rne f iArusndPi kvinosntdo_w aagnun pe( konrs1o:
tanw nago tpe1_o rs)a p uapinocppioticdr sti d=uepd: p2! 8 o
t1
EFFIdIX! MDV
!ID FI CXoPnUM E!VAP eCr: Ps8Ui o1Vn
rerusniknoonw unn korn ownno t osru npopotr tsuepdp! o
te ddo! ne
uIiXnMitE_!f CiPdUvi dVe_rasp(isont augen1k)no wapni cori dn: o0t 2s
FpIpDorVtIDe do! n
AP d: o0ne2
n irt_efaidbdavicdk_ =a p2(s0t10a7g0e11)
( acpiocmimodn:_ 4f1id
1pFIaDcVkeIdD) o n= 1A0P:7 040
Wait for AP stage 1: ap_apicid = 3
readback = 3010701
common_fid(packed) = 10700
common_fid = 10700
FID Change Node:00, F3xD4: c3310f27
FID Change Node:01, F3xD4: c3310f27
End FIDVIDMSR 0xc0010071 0x0083 0x30036040
mcp55_num:01
...WARM RESET...
coreboot-2.0.0-r4380:4526M_Fallback Tue Aug 11 15:51:58 CEST 2009
starting...
BSP Family_Model: 00100f42
*sysinfo range: [000cc000,000cdfa0]
bsp_apicid = 00
cpu_init_detectedx =
microcode: rev id not found. Skipping microcode patch!
cpuSetAMDMSR done
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 05
event: 1004
data: 04 00 00 01
AMD_CB_ManualBUIDSwapList()
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 02 ff
Exit amd_ht_init()
cpuSetAMDPCI 00
On node 0, link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0,
link 0 isOn node 0, link 1 isOn node 0, link 2 isOn node 0, link 0 e
cpuSetAMDPCI 01
On node 1, link 0 isOn node 1, link 1 isOn node 1, link 2 isOn node 1,
link 0 isOn
Re: [coreboot] 10th anniversary celebration?
I wanted to come to germany for something but it seems my sched is going to make that impossible. We may have to do something in the Bay Area as well. Hoist a beer to our european friends I suppose. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Tyan S2912[Fam10] HTX problem
-Original Message- From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On Behalf Of Maximilian Thuermer Sent: Tuesday, August 11, 2009 8:13 AM To: coreboot@coreboot.org Subject: [coreboot] Tyan S2912[Fam10] HTX problem Hi all, I am trying to get an HTX plug in card running on a Tyan S2912 Fam10 System. I tried both Barcelona and Shanghai CPUs and both system setups ended booting during PCI scanning. I am not familiar with the PCI subsystem and the procedures of coreboot regarding this matter, but when scanning through the code, I do not even see why the last line is printed out twice whereas the procedure including the printout only gets called once with the specified parameters. Does anyone have an idea where I could start searching for a possible solution to my problem. I would print out the path to each bridge in the scan to see where it's getting stuck. You can get that with dev_path(bus-dev). It looks pretty normal up to that point. It looks like it found your chipset, 2 cpus, and a graphics card before it died. If that doesn't help you track it down, an lspci would be helpful with the information of which bridge it gets stuck scanning. The values of the Configuration Map registers 0xE0-EC might also help you track down where the PCI requests are being routed. PCI: pci_scan_bus returning with max=004 PCI: pci_scan_bus returning with max=004 I can't tell why it's printed twice either. Good luck, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Tyan S2912[Fam10] HTX problem
Hi Maximilian, On Tue, Aug 11, 2009 at 04:12:39PM +0200, Maximilian Thuermer wrote: I am trying to get an HTX plug in card running on a Tyan S2912 Fam10 System. I tried both Barcelona and Shanghai CPUs and both system setups ended booting during PCI scanning. Do you mean *re*booting? I've seen some of that. Are you using gcc 3.x or 4.x to compile, and on 32 or 64 bit? I've found there are issues with gcc 4.3 (even when built with the nice coresystems build-your-own-toolchain script). The most reliable compiler for coreboot in my experience is still gcc 3.4. Also, are you sure your CONFIG_HT_* settings are correct? I found that CONFIG_HT_CHAIN_UNITID_BASE really has to be 1 to get a bootable system with mcp55 on fam10. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Tyan S2912[Fam10] HTX problem
On Tue, Aug 11, 2009 at 8:16 AM, Ward Vandewegew...@gnu.org wrote: The most reliable compiler for coreboot in my experience is still gcc 3.4. This is really getting to be a problem. Is 4.4 any better? Any idea what could have caused the breakage? I think we can trust that gcc is not going to stop changing just for us :-) ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] mkelfimage with CBFS?
On Tue, Aug 11, 2009 at 2:25 AM, Cristi Magherusancristi.magheru...@net.utcluj.ro wrote: I just noticed something interesting... The ROM with CBFS with vmlinux included (without using mkelfImage) seems to boot, or at least gets loaded by cbfs. we really need to try this on simnow. Try reconfiguring your kernel again and see what goes on. Also, are you trying the experiment of loading the kernel with gpxe/filo/whatever to see if it boots? ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]Kconfig for v2
https://www.coresystems.de/~patrick/20090811-1-kconfig is an updated patch, with some AMD support by Ron. Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ASUS KFN4D16 - K8 FAM10
thanks Myles thats mostly clear but I have one question Can I start with only CPU, HTX, DIMMS and IDE listed in config.lb and then work up from there? Or do I need to list everything which is soldered to the mainboard even if I don't need them (to boot linux)? regards Tom You only need to add devices that: 1. Won't be found otherwise 2. Need some specific initialization 3. Are soldered to the mainboard Everything else will be found and initialized automatically. Good luck, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ASUS KFN4D16 - K8 FAM10
On Tue, Aug 11, 2009 at 11:17 AM, thomas ward tomwardath...@yahoo.co.ukwrote: thanks Myles thats mostly clear but I have one question Can I start with only CPU, HTX, DIMMS and IDE listed in config.lb and then work up from there? Yes. Or do I need to list everything which is soldered to the mainboard even if I don't need them (to boot linux)? No. You only need to list the things that need to be initialized by Coreboot. Devices that don't need special initialization need not be mentioned even if you need them. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4530 - trunk/coreboot-v2/src/cpu/amd/model_lx
Author: oxygene Date: 2009-08-11 19:32:26 +0200 (Tue, 11 Aug 2009) New Revision: 4530 Modified: trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc Log: cpu/amd/model_lx used its own routine for copying coreboot_ram. This change makes it use the generic infrastructure. NOTE: If you're bisecting issues on geode-lx circa jumping to coreboot_ram, this change has a high probability to break that place - so look into it. Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Ronald G. Minnich rminn...@gmail.com Modified: trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc === --- trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc 2009-08-11 15:56:18 UTC (rev 4529) +++ trunk/coreboot-v2/src/cpu/amd/model_lx/cache_as_ram.inc 2009-08-11 17:32:26 UTC (rev 4530) @@ -217,107 +217,25 @@ * the location it is compiled to run at. * Normally this is copying from FLASH ROM to RAM. */ -#if !CONFIG_COMPRESS + movl%ebp, %esi + /* FIXME: look for a proper place for the stack */ + movl$0x400, %esp + movl%esp, %ebp + pushl %esi +#if CONFIG_CBFS == 1 + pushl $str_coreboot_ram_name + call cbfs_and_run_core +#else movl$_liseg, %esi movl$_iseg, %edi movl$_eiseg, %ecx subl%edi, %ecx - movb%cl, %al - shrl$2, %ecx - andb$3, %al - rep movsl - movb%al, %cl - rep movsb -#else - leal4+_liseg, %esi - leal_iseg, %edi - movl%ebp, %esp /* preserve %ebp */ - movl$-1, %ebp /* last_m_off = -1 */ - jmp dcl1_n2b - -/* - DECOMPRESSION - - - Input: - %esi - source - %edi - dest - %ebp - -1 - cld - - Output: - %eax - 0 - %ecx - 0 -*/ - -.macro getbit bits -.if\bits == 1 - addl%ebx, %ebx - jnz 1f -.endif - movl(%esi), %ebx - subl$-4, %esi /* sets carry flag */ - adcl%ebx, %ebx -1: -.endm - -decompr_literals_n2b: - movsb - -decompr_loop_n2b: - addl%ebx, %ebx - jnz dcl2_n2b -dcl1_n2b: - getbit 32 -dcl2_n2b: - jc decompr_literals_n2b - xorl%eax, %eax - incl%eax/* m_off = 1 */ -loop1_n2b: - getbit 1 - adcl%eax, %eax /* m_off = m_off*2 + getbit() */ - getbit 1 - jnc loop1_n2b /* while(!getbit()) */ - xorl%ecx, %ecx - subl$3, %eax - jb decompr_ebpeax_n2b /* if (m_off == 2) goto decompr_ebpeax_n2b ? */ - shll$8, %eax - movb(%esi), %al /* m_off = (m_off - 3)*256 + src[ilen++] */ - incl%esi - xorl$-1, %eax - jz decompr_end_n2b /* if (m_off == 0x) goto decomp_end_n2b */ - movl%eax, %ebp /* last_m_off = m_off ?*/ -decompr_ebpeax_n2b: - getbit 1 - adcl%ecx, %ecx /* m_len = getbit() */ - getbit 1 - adcl%ecx, %ecx /* m_len = m_len*2 + getbit()) */ - jnz decompr_got_mlen_n2b/* if (m_len == 0) goto decompr_got_mlen_n2b */ - incl%ecx/* m_len++ */ -loop2_n2b: - getbit 1 - adcl%ecx, %ecx /* m_len = m_len*2 + getbit() */ - getbit 1 - jnc loop2_n2b /* while(!getbit()) */ - incl%ecx - incl%ecx/* m_len += 2 */ -decompr_got_mlen_n2b: - cmpl$-0xd00, %ebp - adcl$1, %ecx/* m_len = m_len + 1 + (last_m_off 0xd00) */ - movl%esi, %edx - leal(%edi,%ebp), %esi /* m_pos = dst + olen + -m_off */ - rep - movsb /* dst[olen++] = *m_pos++ while(m_len 0) */ - movl%edx, %esi - jmp decompr_loop_n2b -decompr_end_n2b: - intel_chip_post_macro(0x12) /* post 12 */ - - movl%esp, %ebp + pushl %ecx + pushl %edi + pushl %esi + call copy_and_run_core #endif - CONSOLE_DEBUG_TX_STRING($str_pre_main) - leal_iseg, %edi - jmp *%edi - .Lhlt: intel_chip_post_macro(0xee) /* post fail ee */ hlt @@ -377,3 +295,10 @@ .previous #endif /* ASM_CONSOLE_LOGLEVEL BIOS_DEBUG */ +#if CONFIG_CBFS == 1 +# if CONFIG_USE_FALLBACK_IMAGE == 1 +str_coreboot_ram_name: .string fallback/coreboot_ram +# else +str_coreboot_ram_name: .string normal/coreboot_ram +# endif +#endif -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Problem to build the rom image
On Tue, Aug 11, 2009 at 11:43 AM, bz bza...@web.de wrote: Hello, I just tried to build coreboot.rom for an Axus TC 320 as described in the Build tutorial. ./buildtarget axus/tc320 until here everything works fine. LANG=C make The job stop with the following messages. objdump -dS coreboot coreboot.disasm objcopy --gap-fill 0xff -O binary coreboot coreboot.strip make[1]: *** No rule to make target `../../../../../../../images/etherboot.elf', needed by `payload'. Stop. It can't find your payload. You need to change ../../../../../../../images/etherboot.elf to ../payload.elf and copy your payload (filo, SeaBIOS, etc) to targets/axus/tc320/tc320/payload.elf Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Problem to build the rom image
Hi Björn, On 11.08.2009 19:43, bz wrote: I just tried to build coreboot.rom for an Axus TC 320 as described in the Build tutorial. ./buildtarget axus/tc320 20 minutes ago Patrick committed a change to payload handling which may help you. Please retry with latest subversion. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r4531
Dear coreboot readers! This is the automatic build system of coreboot. The developer oxygene checked in revision 4531 to the coreboot repository. This caused the following changes: Change Log: Enable CBFS everywhere. All boards compiled for me (abuild tested), and we will fix issues as they appear. Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Ronald G. Minnich rminn...@gmail.com Build Log: Compilation of a-trend:atc-6220 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=atc-6220vendor=a-trendnum=2 Compilation of a-trend:atc-6240 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=atc-6240vendor=a-trendnum=2 Compilation of abit:be6-ii_v2_0 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=be6-ii_v2_0vendor=abitnum=2 Compilation of asus:p2b has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=p2bvendor=asusnum=2 Compilation of asus:p2b-d has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=p2b-dvendor=asusnum=2 Compilation of asus:p2b-ds has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=p2b-dsvendor=asusnum=2 Compilation of asus:p2b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=p2b-fvendor=asusnum=2 Compilation of asus:p3b-f has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=p3b-fvendor=asusnum=2 Compilation of azza:pt-6ibd has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=pt-6ibdvendor=azzanum=2 Compilation of biostar:m6tba has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=m6tbavendor=biostarnum=2 Compilation of compaq:deskpro_en_sff_p600 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=deskpro_en_sff_p600vendor=compaqnum=2 Compilation of embeddedplanet:ep405pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=ep405pcvendor=embeddedplanetnum=2 Compilation of gigabyte:ga-6bxc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=ga-6bxcvendor=gigabytenum=2 Compilation of iei:nova4899r has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=nova4899rvendor=ieinum=2 Compilation of motorola:sandpointx3_altimus_mpc7410 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=sandpointx3_altimus_mpc7410vendor=motorolanum=2 Compilation of msi:ms6119 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=ms6119vendor=msinum=2 Compilation of msi:ms6147 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=ms6147vendor=msinum=2 Compilation of soyo:sy-6ba-plus-iii has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=sy-6ba-plus-iiivendor=soyonum=2 Compilation of totalimpact:briq has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=briqvendor=totalimpactnum=2 Compilation of tyan:s1846 has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=s1846vendor=tyannum=2 Compilation of via:epia-m has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4531device=epia-mvendor=vianum=2 If something broke during this checkin please be a pain in oxygene's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]Kconfig for v2
Harald, there is a bit of documentation in there about usage of Kconfig and Makefile.config. It is not complete but I fill in a little each day. Please refer to it w.r.t. the use of mainboard and socket Kconfig. What if we apply this patch and get yours in next? ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]Kconfig for v2
Acked-by: Ronald G. Minnich rminn...@gmail.com Folks, please read and comment on documentation/Kconfig.tex This is a changing document but I'm happy to get any comments even in its current form. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]Kconfig for v2
On Tuesday 11 August 2009 21:35:26 ron minnich wrote: Harald, there is a bit of documentation in there about usage of Kconfig and Makefile.config. It is not complete but I fill in a little each day. Please refer to it w.r.t. the use of mainboard and socket Kconfig. What if we apply this patch and get yours in next? For my part I really welcome the Kconfig build system, and therefore I'd like to see it commited. My patch is right now not as far to get commited, I think it will take a few days more to get it in a fine shape. ron Regards, Harald -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] option rom progress and some issues
Hi all Since USB ROM has already added into the booting menu list(IPL table), and the UHCI stack can be run well in usbrom now, i have some issues to confirm, any advices are welcome. 1) Plug and Play BIOS SpecificationPage21, There is an r Return Status from Initialization Call of OPTION ROM. Which used to let the bios know the status. But it seems Seabios does not check the return code. Is that OK? 2) After Seabios make an far call into the BEV, the OPTION ROM should begin to load OS.if it failed, it can return back to BIOS. But it can not return back with my USB OPTION ROM, Is there any configuration I should set? 3) In my eyes, OPTION ROM hook int13 after jump into BEV, not in the initialization.But after that how does it jump into the booting code which located in the USB disk? BTW: Kevin: I looked the code of Seabios ata.c to learn how seabios booting OS from ata disk. some question i have: 1) ATA used add_bcv_hd to add ata disk into IPL table. it's type is IPL_TYPE_HARDDISK(0x02). It's vector is the driver id. how does seabios know the bootstrap vector based the driver ID? what does ata fill FDPT area for? Should my usbrom do the same? For my usbrom, i should not use add_bcv to add option rom into IPL ? or just take the ata as example? -- Jason Wang Peking University -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] option rom progress and some issues
Hi Kevin, On Wed, Aug 12, 2009 at 8:18 AM, Kevin O'Connor ke...@koconnor.net wrote: On Wed, Aug 12, 2009 at 03:59:02AM +0800, Jason Wang wrote: Hi all Since USB ROM has already added into the booting menu list(IPL table), and the UHCI stack can be run well in usbrom now, i have some issues to confirm, any advices are welcome. 1) Plug and Play BIOS SpecificationPage21, There is an r Return Status from Initialization Call of OPTION ROM. Which used to let the bios know the status. But it seems Seabios does not check the return code. Is that OK? SeaBIOS assumes the rom runs successfully - I think that is okay. If you wish to unload the optionrom, set its size to 0. 2) After Seabios make an far call into the BEV, the OPTION ROM should begin to load OS.if it failed, it can return back to BIOS. But it can not return back with my USB OPTION ROM, Is there any configuration I should set? You should not use BEV; you should use a BCV. I use a BCV now, sorry for messing this two types. Which i use is BCV. I tried to put only an lretw in BCV. but still failed. I don't know why you can't return - it should work. Maybe the stack or gdt/idt was changed? 3) In my eyes, OPTION ROM hook int13 after jump into BEV, not in the initialization.But after that how does it jump into the booting code which located in the USB disk? As above, define a BCV and hook int13 from the BCV handler. So, BCV handler is used to hook int13, anything else that BCV should do? SeaBIOS will make int13 calls to load the OS and boot it. As long as your rom can handle the int13 calls, SeaBIOS will be able to boot an OS from usb. BTW: Kevin: I looked the code of Seabios ata.c to learn how seabios booting OS from ata disk. some question i have: 1) ATA used add_bcv_hd to add ata disk into IPL table. it's type is IPL_TYPE_HARDDISK(0x02). It's vector is the driver id. how does seabios know the bootstrap vector based the driver ID? add_bcv_hd() adds the drive to the BCV table, not the IPL table. SeaBIOS populates the BCV table with built-in harddrives and optionroms with a BCV. what does ata fill FDPT area for? Should my usbrom do the same? It's some weird legacy thing. Nothing modern will require it. I don't know what legacy things will break without it. For my usbrom, i should not use add_bcv to add option rom into IPL ? or just take the ata as example? As above, you should use a BCV. -- Jason Wang Peking University -Kevin -- Jason Wang Peking University -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
