Re: [coreboot] BIOS RAM in AMD SB7XX southbridges ?
on 28/10/2009 06:55 Darmawan Salihun said the following: On 10/28/09, Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net wrote: On 27.10.2009 14:06, Darmawan Salihun wrote: What is the BIOS RAM in AMD SB7XX used for? Is it to buffer the BIOS contents from SPI flash chip prior to execution of the very first instruction? No. I recall that it's impossible to execute code directly in an SPI chip. Yes, but the chipset takes care of the SPI command interface and presents the contents of the SPI chip nicely memory mapped to the CPU, so the CPU can execute the ROM contents directly. I see. So, there must be some sort of independent microcontroller/microprocessor in the southbridge that fetches the contents of the SPI chip and present it in a memory-mapped way to the CPU. Probably this is how the BIOS RAM is used by the internal microcontroller/microprocessor in the southbridge. No, I think. BIOS RAM is some sort of scratch-pad memory for arbitrary use by software. I suspect this because an ex-intel engineer that I spoke to, told me that back then he was using ARM7TDMI to do the job of presenting the BIOS contents in a memory-mapped way to the CPU. These days, the function must've been integrated in the southbridge as you said. I suspect AMD do the same. Yes, most probably. But BIOS RAM has nothing to do with this. Chipset directs memory access for certain range(s) to embedded SPI controller which in turn translates them into appropriate SPI commands. -- Andriy Gapon -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] ACPI updates + S3 Resume without hole at 31MB
Rudolf Marek wrote:
Hi,
I have some questions:
1) is 0x600 as base for lowmem trampoline safe? it always makes me
wonder, this
was the reason why I did the realmode code which runs above 1MB ;)
Maybe we can
have that too and only copy the trampoline to the highmem save area
and execute
it there. This would mean all memory bellow 1MB is untouched.
It should be safe. The lower 4kb are supposed to be untouched by the OS,
according to some information I found, including an old mail of yours on
S3 Resume.
2)
You seem to follow different way how to detect S3.
Not sure I can follow. I didn't change that part of your code
I had in the code for all boards (like memory controller init)
ifdef ACPI_IS_WAKEUP_EARLY
--int suspend = acpi_is_wakeup_early();
#else
--int suspend = 0;
#endif
And for per chipset CAR code I defined a function which is doing it:
define ACPI_IS_WAKEUP_EARLY 1
int acpi_is_wakeup_early(void) {
device_t dev;
u16 tmp;
print_debug(IN TEST WAKEUP\n);
...
Since I only use the value in auto.c I did not put this into a one line
function called externally. If that is what you suggest, we can easily
do that, though.
And for the normal ram stage there is:
/* this is to be filled by SB code - startup value what was found */
u8 acpi_slp_type = 0;
int acpi_is_wakeup(void)
{
--return (acpi_slp_type == 3);
}
Which is backup what was the sleep type. I think this is how you deal
with that
using the scratchpads.
Yes, I am using your mechanism here. But since it's not safe to leave
the value in PM1_CNT (at least on i945), I had to move it somewhere
else. SKPAD seemed like a good place to get it over to stage 2.
3) I think your SMM code corrupts lowmem, or I have not seen any
backup of that
mem? Maybe I'm wrong?
No, that is true... 0x38000 + size of SMM relocator is wiped out.
4) Changes to the stack
I think you changed the stack to some other place, not sure how to
change that
for K8 CAR? Also there is an remaining issue if CAR gets flushed to
memory or
not. I think Carl-Daniel had some patch for this.
On i945 the cache as ram area is not backed by RAM, so the copy trickery
from K8 does not work here.
Stack setup is more than fishy on most platforms, but that's pretty
unrelated to my ACPI resume patch.
What patch are you referring to?
5) Don't understand much the cbmem_reinit((u64)high_ram_base)) in CAR
code, you
seem to take the TOM from PCI reg but this gets more complicated for
UMA, I dont
know how to do that for K8. Partially because the high_ram_base gets
dynamically
lowered in K8M890 resource code :/ In other words there is no easy
way for me
to find it in memory.
Very ugly. Maybe we can fix the K8M890 resource code? What factors
influence the high_ram_base on that chipset? How early can we determine
them?
Except some hacks like make the cbmem look like some
proprietary ACPI table and walk acpi tables as for we do for resume
but in car
stage just to find out where the tables are...
Speaking of hacks, we could remember the CBMEM base address in the low
4KB so we can find them again...
Stefan
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[coreboot] IBM ThinkPad X32 support status?
Hello, I'd like to know the coreboot status for the IBM ThinkPad X32 [1] laptop. Please find, attached, the lspci, superiotool and flashrom output as asked in the FAQ. Thanks for your great work! [1] http://www-307.ibm.com/pc/support/site.wss/MIGR-59144.html Bye, -- intrigeri intrig...@boum.org | GnuPG key @ https://gaffer.ptitcanardnoir.org/intrigeri/intrigeri.asc | OTR fingerprint @ https://gaffer.ptitcanardnoir.org/intrigeri/otr-fingerprint.asc flashrom v0.9.1-r736 No coreboot table found. Found chipset Intel ICH4-M, enabling flash write... BIOS Lock Enable: disabled, BIOS Write Enable: enabled, BIOS_CNTL is 0x1 OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... 465M loops per second, 100 myus = 199 us. OK. Probing for AMD Am29F010A/B, 128 KB: probe_29f040b: id1 0xb3, id2 0xb1 Probing for AMD Am29F002(N)BB, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for AMD Am29F002(N)BT, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for AMD Am29F016D, 2048 KB: probe_29f040b: id1 0xff, id2 0xff Probing for AMD Am29F040B, 512 KB: probe_29f040b: id1 0xdd, id2 0xb2 Probing for AMD Am29F080B, 1024 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for AMD Am29LV040B, 512 KB: probe_29f040b: id1 0xdd, id2 0xb2 Probing for AMD Am29LV081B, 1024 KB: probe_29f040b: id1 0x4e, id2 0x41 Probing for ASD AE49F2008, 256 KB: Chip lacks correct probe timing information, using default 10mS/40uS. probe_jedec: id1 0xbf, id2 0x5a Probing for Atmel AT25DF021, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF041A, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF081, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF321A, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25DF641, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25F512B, 64 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS010, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT25FS040, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF041, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF081A, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26DF161A, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT26F004, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT29C512, 64 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Atmel AT29C010A, 128 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Atmel AT29C020, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Atmel AT29C040A, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Atmel AT45CS1282, 16896 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB011D, 128 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB021D, 256 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB041D, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB081D, 1024 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB161D, 2048 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321C, 4224 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB321D, 4096 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT45DB642D, 8192 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for Atmel AT49BV512, 64 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Atmel AT49F002(N), 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for Atmel AT49F002(N)T, 256 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for AMIC A25L40P, 512 KB: skipped. Host bus type Non-SPI and chip bus type SPI are incompatible. Probing for AMIC A29002B, 256 KB: probe_29f002: id1 0xbf, id2 0x5a Probing for AMIC A29002T, 256 KB: probe_29f002: id1 0xbf, id2 0x5a Probing for AMIC A29040B, 512 KB: probe_29f040b: id1 0xdd, id2 0xb2 Probing for AMIC A49LF040A, 512 KB: probe_jedec: id1 0xbf, id2 0x5a Probing for EMST F49B002UA,
Re: [coreboot] [v2] r4875 - in trunk/coreboot-v2: . src/arch/i386 util/cbfstool util/sconfig
s...@coreboot.org wrote: Author: uwe Date: 2009-10-28 00:14:54 +0100 (Wed, 28 Oct 2009) New Revision: 4875 Modified: trunk/coreboot-v2/Makefile trunk/coreboot-v2/src/arch/i386/Makefile.inc trunk/coreboot-v2/util/cbfstool/Makefile.inc trunk/coreboot-v2/util/sconfig/config.g trunk/coreboot-v2/util/sconfig/parsedesc.g trunk/coreboot-v2/util/sconfig/yapps2.py Log: Prefix all build output file names of files which end up in the build directory with build/ for consistency (trivial, sort of). Not so good.. the directory might not be called build... maybe it should be $(shell basename $(obj)) or something? Also, it's kind of obvious that created file end op in %(obj) so this seems to add more output but not more information ... Can we change this to say Output directory is: $(obj) once, without repeating it for every file? I noticed that there are some hard codes of ./build in the Makefile, too. That breaks as soon as someone adjusts $(obj). Stefan -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [v2] r4874 - in trunk/coreboot-v2: . src/arch/i386/boot src/arch/i386/lib src/console src/devices src/include/device src/northbridge/intel/i440bx src/southbridge/intel/i82371eb util/rom
s...@coreboot.org wrote:
Modified: trunk/coreboot-v2/src/console/vsprintf.c
===
--- trunk/coreboot-v2/src/console/vsprintf.c 2009-10-27 16:24:22 UTC (rev
4873)
+++ trunk/coreboot-v2/src/console/vsprintf.c 2009-10-27 21:49:33 UTC (rev
4874)
@@ -48,6 +48,8 @@
return i;
}
+int sprintf(char *buf, const char *fmt, ...);
+
int sprintf(char *buf, const char *fmt, ...)
{
va_list args;
What's the reason for not just including string.h in this file?
Putting the prototype right in front of the function just shuts up the
warning. That warning's intention is to tell us that a caller of the
function might assume a wrong prototype implicitly.
I think if stuff is called externally, we should have their prototypes
in header files. Otherwise they should be defined static.
Modified: trunk/coreboot-v2/src/devices/device.c
===
--- trunk/coreboot-v2/src/devices/device.c2009-10-27 16:24:22 UTC (rev
4873)
+++ trunk/coreboot-v2/src/devices/device.c2009-10-27 21:49:33 UTC (rev
4874)
@@ -671,8 +671,11 @@
device_t vga_pri = 0;
static void set_vga_bridge_bits(void)
{
-#warning FIXME modify set_vga_bridge so it is less pci centric!
-#warning This function knows too much about PCI stuff, it should be just a
iterator/visitor.
+ /*
+ * FIXME: Modify set_vga_bridge so it is less PCI centric!
+ * This function knows too much about PCI stuff, it should be just
+ * an iterator/visitor.
+ */
/* FIXME: Handle the VGA palette snooping. */
struct device *dev, *vga, *vga_onboard, *vga_first, *vga_last;
Why was that warning removed?
Modified: trunk/coreboot-v2/src/devices/pciexp_device.c
===
--- trunk/coreboot-v2/src/devices/pciexp_device.c 2009-10-27 16:24:22 UTC
(rev 4873)
+++ trunk/coreboot-v2/src/devices/pciexp_device.c 2009-10-27 21:49:33 UTC
(rev 4874)
@@ -34,8 +34,8 @@
/* error... */
return;
}
- printk_debug(PCIe: tuning %s\n, dev_path(dev));
-#warning IMPLEMENT PCI EXPRESS TUNING
+ // printk_debug(PCIe: tuning %s\n, dev_path(dev));
+ /* TODO: Implement PCI Express tuning. */
}
unsigned int pciexp_scan_bus(struct bus *bus,
What kind of tuning should be done here?
Stefan
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Re: [coreboot] [v2] r4871 - in trunk/coreboot-v2: src/arch/i386/boot src/arch/i386/include src/arch/i386/lib src/boot src/devices src/include src/include/cpu/x86 src/include/device src/lib src/pc80 sr
s...@coreboot.org wrote:
Modified: trunk/coreboot-v2/src/arch/i386/boot/gdt.c
===
--- trunk/coreboot-v2/src/arch/i386/boot/gdt.c2009-10-27 14:05:21 UTC
(rev 4870)
+++ trunk/coreboot-v2/src/arch/i386/boot/gdt.c2009-10-27 14:29:29 UTC
(rev 4871)
@@ -33,6 +33,7 @@
} __attribute__((packed));
// Copy GDT to new location and reload it
+void move_gdt(void);
void move_gdt(void)
{
void *newgdt;
Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c
===
--- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-10-27 14:05:21 UTC
(rev 4870)
+++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-10-27 14:29:29 UTC
(rev 4871)
uint64_t high_tables_base = 0;
uint64_t high_tables_size;
void move_gdt(void);
void cbmem_arch_init(void)
{
Not so nice... This warnings should be fixed, not just shut up.
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Re: [coreboot] small patch for prototypes and unused variables
Myles Watson wrote:
Maciej,
Thanks for the patch. I think most of it is ready to be committed.
Index: src/lib/clog2.c
===
--- src/lib/clog2.c (revision 4869)
+++ src/lib/clog2.c (working copy)
@@ -7,6 +7,8 @@
/* Assume 8 bits per byte */
#define CHAR_BIT 8
+unsigned long log2(unsigned long x);
+
unsigned long log2(unsigned long x)
{
// assume 8 bits per byte.
Things like this make me wonder if we should just turn off the warning. Is
there a header file where we can put some of these prototypes?
No, we should not turn off the warning. It's the Is our API correct?
warning. We had very ugly bugs because of different prototypes in
different .c files.
Yes, there are many header files,.. check src/include for a fitting one.
If there is none, we should think about creating one.
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Re: [coreboot] [PATCH] resource allocator hole handling (simple and old)
Myles Watson wrote:
Index: src/devices/device.c
===
--- src/devices/device.c (revision 4842)
+++ src/devices/device.c (working copy)
@@ -576,7 +576,7 @@
continue;
/* Is it already outside the limits? */
- if (res-size (((res-base + res-size -1) lim-base)
||
+ if (!res-size || (((res-base + res-size -1) lim-base)
||
(res-base lim-limit)))
continue;
I think fixed resources of size 0 are broken. I'd rather fix the targets.
It's hard for the allocator to avoid size 0 resources.
Ok, this seems to be a left-over which came in through intelligent merging.
I checked the code and size 0 resources are skipped already..
if (!res-size) {
/* It makes no sense to have 0-sized, fixed
resources.*/
printk_err(skipping %...@%lx fixed resource,
size=0!\n,
dev_path(dev), res-index);
continue;
}
so generally that check for res-size could be dropped completely in
above construct, making it
/* Is it already outside the limits? */
-if (res-size (((res-base + res-size -1) lim-base) ||
- (res-base lim-limit)))
+if (((res-base + res-size -1) lim-base) || (res-base
lim-limit))
continue;
Stefan
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Re: [coreboot] [PATCH] resource allocator hole handling (simple and old)
I checked the code and size 0 resources are skipped already.. Yes, I should have remembered that. so generally that check for res-size could be dropped completely in above construct, making it /* Is it already outside the limits? */ -if (res-size (((res-base + res-size -1) lim-base) || - (res-base lim-limit))) +if (((res-base + res-size -1) lim-base) || (res-base lim-limit)) continue; That could be done. There's no functional difference as long as the check for size 0 resources stays. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] small patch for prototypes and unused variables
-Original Message-
From: Stefan Reinauer [mailto:ste...@coresystems.de]
Sent: Wednesday, October 28, 2009 4:25 AM
To: Myles Watson
Cc: 'Maciej Pijanka'; coreboot@coreboot.org
Subject: Re: [coreboot] small patch for prototypes and unused variables
Myles Watson wrote:
Maciej,
Thanks for the patch. I think most of it is ready to be committed.
Index: src/lib/clog2.c
===
--- src/lib/clog2.c (revision 4869)
+++ src/lib/clog2.c (working copy)
@@ -7,6 +7,8 @@
/* Assume 8 bits per byte */
#define CHAR_BIT 8
+unsigned long log2(unsigned long x);
+
unsigned long log2(unsigned long x)
{
// assume 8 bits per byte.
Things like this make me wonder if we should just turn off the warning.
Is
there a header file where we can put some of these prototypes?
No, we should not turn off the warning. It's the Is our API correct?
warning. We had very ugly bugs because of different prototypes in
different .c files.
In that case we ought to squash them all. Too many warnings makes it hard
to see important ones.
Yes, there are many header files,.. check src/include for a fitting one.
If there is none, we should think about creating one.
Maybe we should create src/include/lib.h for all of the missing ones from
src/lib?
Thanks,
Myles
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[coreboot] [v2] r4876 - trunk/coreboot-v2/src/devices
Author: stepan Date: 2009-10-28 15:57:14 +0100 (Wed, 28 Oct 2009) New Revision: 4876 Modified: trunk/coreboot-v2/src/devices/device.c Log: The check for zero sized resources is already done earlier. So don't redo it here. I think we don't ever want to drop the extra check, since it indicates that the components involved need fixing. Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Modified: trunk/coreboot-v2/src/devices/device.c === --- trunk/coreboot-v2/src/devices/device.c 2009-10-27 23:14:54 UTC (rev 4875) +++ trunk/coreboot-v2/src/devices/device.c 2009-10-28 14:57:14 UTC (rev 4876) @@ -576,8 +576,7 @@ continue; /* Is it already outside the limits? */ - if (res-size (((res-base + res-size -1) lim-base) || - (res-base lim-limit))) + if (((res-base + res-size -1) lim-base) || (res-base lim-limit)) continue; /* Choose to be above or below fixed resources. This -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] small patch for prototypes and unused variables
Myles Watson wrote:
-Original Message-
From: Stefan Reinauer [mailto:ste...@coresystems.de]
Sent: Wednesday, October 28, 2009 4:25 AM
To: Myles Watson
Cc: 'Maciej Pijanka'; coreboot@coreboot.org
Subject: Re: [coreboot] small patch for prototypes and unused variables
Myles Watson wrote:
Maciej,
Thanks for the patch. I think most of it is ready to be committed.
Index: src/lib/clog2.c
===
--- src/lib/clog2.c (revision 4869)
+++ src/lib/clog2.c (working copy)
@@ -7,6 +7,8 @@
/* Assume 8 bits per byte */
#define CHAR_BIT 8
+unsigned long log2(unsigned long x);
+
unsigned long log2(unsigned long x)
{
// assume 8 bits per byte.
Things like this make me wonder if we should just turn off the warning.
Is
there a header file where we can put some of these prototypes?
No, we should not turn off the warning. It's the Is our API correct?
warning. We had very ugly bugs because of different prototypes in
different .c files.
In that case we ought to squash them all. Too many warnings makes it hard
to see important ones.
Agreed. The old build system made it far to easy to ignore warnings. Now
with Kconfig we have a serious chance of detecting issues with our code. :-)
I think this is very healthy.
Yes, there are many header files,.. check src/include for a fitting one.
If there is none, we should think about creating one.
Maybe we should create src/include/lib.h for all of the missing ones from
src/lib?
Stuff like sprintf would nicely fit in stdio or string.h, so the include
file hints in the man pages for those functions kind of fit. Maybe
that's odd taste, I don't know.
All the other stuff that does not implement libc functionality (or
explicitly deserves an own include file for some reason) should go into
a lib.h.
Maybe even just having lib.h is enough.
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Re: [coreboot] [v2] r4871 - in trunk/coreboot-v2: src/arch/i386/boot src/arch/i386/include src/arch/i386/lib src/boot src/devices src/include src/include/cpu/x86 src/include/device src/lib src/pc80 sr
I think it's clear we need lib.h or something like it. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] build vs. $(obj) in Makefiles (was Re: [v2] r4875 ...)
I noticed that there are some hard codes of ./build in the Makefile,
too. That breaks as soon as someone adjusts $(obj).
Attached patch fixes all hard-coded occurrences of build/ in the Makefiles.
Signed-off-by: Myles Watson myle...@gmail.com
Thanks,
Myles
Index: svn/Makefile
===
--- svn.orig/Makefile
+++ svn/Makefile
@@ -35,7 +35,7 @@ export top := $(shell pwd)
export src := $(top)/src
export srck := $(top)/util/kconfig
export obj := $(top)/build
-export objk := $(top)/build/util/kconfig
+export objk := $(obj)/util/kconfig
export sconfig := $(top)/util/sconfig
export yapps2_py := $(sconfig)/yapps2.py
export config_g := $(sconfig)/config.g
@@ -289,8 +289,8 @@ doxygen-clean:
rm -rf $(DOXYGEN_OUTPUT_DIR)
clean: doxygen-clean
- rm -f $(allobjs) build/coreboot* .xcompile
- rm -f build/option_table.* build/crt0_includes.h build/ldscript
+ rm -f $(allobjs) $(obj)/coreboot* .xcompile
+ rm -f $(obj)/option_table.* $(obj)/crt0_includes.h $(obj)/ldscript
rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c $(obj)/mainboard/$(MAINBOARDDIR)/config.py $(obj)/mainboard/$(MAINBOARDDIR)/static.dot
rm -f $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s $(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm
rmdir -p $(alldirs) 2/dev/null /dev/null || true
@@ -300,7 +300,7 @@ distclean: clean
rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig*
update:
- dongle.py -c /dev/term/1 build/coreboot.rom EOF
+ dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF
# This include must come _before_ the pattern rules below!
# Order _does_ matter for pattern rules.
@@ -311,7 +311,7 @@ $(obj)/ldoptions: $(obj)/config.h
awk '/^#define ([^])* ([^])*$$/ {print $$2 = $$3 ;;}' $ $@
$(obj)/romcc: $(top)/util/romcc/romcc.c
- @printf HOSTCC build/romcc (this may take a while)\n
+ @printf HOSTCC $(obj)/romcc (this may take a while)\n
$(HOSTCC) -g -O2 -Wall -o $@ $
.PHONY: $(PHONY) prepare prepare2 clean distclean doxygen doxy coreboot
Index: svn/src/arch/i386/Makefile.inc
===
--- svn.orig/src/arch/i386/Makefile.inc
+++ svn/src/arch/i386/Makefile.inc
@@ -25,14 +25,13 @@ ifeq ($(CONFIG_PAYLOAD_NONE),y)
@printf PAYLOADnone (as specified by user)\n
else
@printf PAYLOAD$(CONFIG_FALLBACK_PAYLOAD_FILE) $(CBFS_PAYLOAD_COMPRESS_FLAG)\n
- $(CBFSTOOL) ./build/coreboot.rom add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) fallback/payload $(CBFS_PAYLOAD_COMPRESS_FLAG)
+ $(CBFSTOOL) $(obj)/coreboot.rom add-payload $(CONFIG_FALLBACK_PAYLOAD_FILE) fallback/payload $(CBFS_PAYLOAD_COMPRESS_FLAG)
endif
ifeq ($(CONFIG_VGA_BIOS),y)
@printf VGABIOS$(CONFIG_FALLBACK_VGA_BIOS_FILE) $(CONFIG_FALLBACK_VGA_BIOS_ID)\n
- $(CBFSTOOL) ./build/coreboot.rom add $(CONFIG_FALLBACK_VGA_BIOS_FILE) pci$(CONFIG_FALLBACK_VGA_BIOS_ID).rom optionrom
+ $(CBFSTOOL) $(obj)/coreboot.rom add $(CONFIG_FALLBACK_VGA_BIOS_FILE) pci$(CONFIG_FALLBACK_VGA_BIOS_ID).rom optionrom
endif
- @printf CBFSPRINT build/coreboot.rom\n\n
- $(CBFSTOOL) build/coreboot.rom print
+ $(CBFSTOOL) $(obj)/coreboot.rom print
###
--
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http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] build vs. $(obj) in Makefiles (was Re: [v2] r4875 ...)
Acked-by: Ronald G. Minnich rminn...@gmail.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4877 - in trunk/coreboot-v2: . src/arch/i386
Author: myles
Date: 2009-10-28 16:30:11 +0100 (Wed, 28 Oct 2009)
New Revision: 4877
Modified:
trunk/coreboot-v2/Makefile
trunk/coreboot-v2/src/arch/i386/Makefile.inc
Log:
Replace hard coded build with $(obj) paths.
Signed-off-by: Myles Watson myle...@gmail.com
Acked-by: Ronald G. Minnich rminn...@gmail.com
Modified: trunk/coreboot-v2/Makefile
===
--- trunk/coreboot-v2/Makefile 2009-10-28 14:57:14 UTC (rev 4876)
+++ trunk/coreboot-v2/Makefile 2009-10-28 15:30:11 UTC (rev 4877)
@@ -35,7 +35,7 @@
export src := $(top)/src
export srck := $(top)/util/kconfig
export obj := $(top)/build
-export objk := $(top)/build/util/kconfig
+export objk := $(obj)/util/kconfig
export sconfig := $(top)/util/sconfig
export yapps2_py := $(sconfig)/yapps2.py
export config_g := $(sconfig)/config.g
@@ -289,8 +289,8 @@
rm -rf $(DOXYGEN_OUTPUT_DIR)
clean: doxygen-clean
- rm -f $(allobjs) build/coreboot* .xcompile
- rm -f build/option_table.* build/crt0_includes.h build/ldscript
+ rm -f $(allobjs) $(obj)/coreboot* .xcompile
+ rm -f $(obj)/option_table.* $(obj)/crt0_includes.h $(obj)/ldscript
rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c
$(obj)/mainboard/$(MAINBOARDDIR)/config.py
$(obj)/mainboard/$(MAINBOARDDIR)/static.dot
rm -f $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc
$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s
$(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm
rmdir -p $(alldirs) 2/dev/null /dev/null || true
@@ -300,7 +300,7 @@
rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig*
update:
- dongle.py -c /dev/term/1 build/coreboot.rom EOF
+ dongle.py -c /dev/term/1 $(obj)/coreboot.rom EOF
# This include must come _before_ the pattern rules below!
# Order _does_ matter for pattern rules.
@@ -311,7 +311,7 @@
awk '/^#define ([^])* ([^])*$$/ {print $$2 = $$3 ;;}' $ $@
$(obj)/romcc: $(top)/util/romcc/romcc.c
- @printf HOSTCC build/romcc (this may take a while)\n
+ @printf HOSTCC $(obj)/romcc (this may take a while)\n
$(HOSTCC) -g -O2 -Wall -o $@ $
.PHONY: $(PHONY) prepare prepare2 clean distclean doxygen doxy coreboot
Modified: trunk/coreboot-v2/src/arch/i386/Makefile.inc
===
--- trunk/coreboot-v2/src/arch/i386/Makefile.inc2009-10-28 14:57:14 UTC
(rev 4876)
+++ trunk/coreboot-v2/src/arch/i386/Makefile.inc2009-10-28 15:30:11 UTC
(rev 4877)
@@ -25,14 +25,13 @@
@printf PAYLOADnone (as specified by user)\n
else
@printf PAYLOAD$(CONFIG_FALLBACK_PAYLOAD_FILE)
$(CBFS_PAYLOAD_COMPRESS_FLAG)\n
- $(CBFSTOOL) ./build/coreboot.rom add-payload
$(CONFIG_FALLBACK_PAYLOAD_FILE) fallback/payload $(CBFS_PAYLOAD_COMPRESS_FLAG)
+ $(CBFSTOOL) $(obj)/coreboot.rom add-payload
$(CONFIG_FALLBACK_PAYLOAD_FILE) fallback/payload $(CBFS_PAYLOAD_COMPRESS_FLAG)
endif
ifeq ($(CONFIG_VGA_BIOS),y)
@printf VGABIOS$(CONFIG_FALLBACK_VGA_BIOS_FILE)
$(CONFIG_FALLBACK_VGA_BIOS_ID)\n
- $(CBFSTOOL) ./build/coreboot.rom add $(CONFIG_FALLBACK_VGA_BIOS_FILE)
pci$(CONFIG_FALLBACK_VGA_BIOS_ID).rom optionrom
+ $(CBFSTOOL) $(obj)/coreboot.rom add $(CONFIG_FALLBACK_VGA_BIOS_FILE)
pci$(CONFIG_FALLBACK_VGA_BIOS_ID).rom optionrom
endif
- @printf CBFSPRINT build/coreboot.rom\n\n
- $(CBFSTOOL) build/coreboot.rom print
+ $(CBFSTOOL) $(obj)/coreboot.rom print
###
--
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http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] build vs. $(obj) in Makefiles (was Re: [v2] r4875 ...)
Myles Watson wrote: I noticed that there are some hard codes of ./build in the Makefile, too. That breaks as soon as someone adjusts $(obj). Attached patch fixes all hard-coded occurrences of build/ in the Makefiles. Signed-off-by: Myles Watson myle...@gmail.com mailto:myle...@gmail.com Acked-by: Stefan Reinauer ste...@coresystems.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] build vs. $(obj) in Makefiles (was Re: [v2] r4875 ...)
On Wed, Oct 28, 2009 at 9:27 AM, ron minnich rminn...@gmail.com wrote: Acked-by: Ronald G. Minnich rminn...@gmail.com Rev 4877. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] build vs. $(obj) in Makefiles (was Re: [v2] r4875 ...)
On Wed, Oct 28, 2009 at 09:44:24AM -0600, Myles Watson wrote: On Wed, Oct 28, 2009 at 9:27 AM, ron minnich rminn...@gmail.com wrote: Acked-by: Ronald G. Minnich rminn...@gmail.com Rev 4877. Thanks! I have a patch to drop the build/ prefixes everywhere, will post soon. Uwe. -- http://www.hermann-uwe.de | http://www.randomprojects.org http://www.crazy-hacks.org | http://www.unmaintained-free-software.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] Add lib.h
This patch creates lib.h for homeless prototypes.
Signed-off-by: Myles Watson myle...@gmail.com
It also looks like xmodem.c could be dropped.
Thanks,
Myles
Index: svn/src/include/lib.h
===
--- /dev/null
+++ svn/src/include/lib.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009, Myles Watson myle...@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+/* This file is for nuisance prototypes that have no other home. */
+
+/* Defined in src/lib/clog2.c */
+unsigned long log2(unsigned long x);
+
+/* Defined in src/lib/lzma.c */
+unsigned long ulzma(unsigned char *src, unsigned char *dst);
+
+/* Defined in src/arch/i386/boot/gdt.c */
+void move_gdt(void);
+
Index: svn/src/lib/clog2.c
===
--- svn.orig/src/lib/clog2.c
+++ svn/src/lib/clog2.c
@@ -4,11 +4,11 @@
#include console/console.h
#endif
+#include lib.h
+
/* Assume 8 bits per byte */
#define CHAR_BIT 8
-unsigned long log2(unsigned long x);
-
unsigned long log2(unsigned long x)
{
// assume 8 bits per byte.
Index: svn/src/lib/cbfs.c
===
--- svn.orig/src/lib/cbfs.c
+++ svn/src/lib/cbfs.c
@@ -21,6 +21,7 @@
#include string.h
#include console/console.h
#include cbfs.h
+#include lib.h
#ifndef CONFIG_BIG_ENDIAN
#define ntohl(x) ( ((x0xff)24) | ((x0xff00)8) | \
@@ -29,8 +30,6 @@
#define ntohl(x) (x)
#endif
-unsigned long ulzma(unsigned char *src, unsigned char *dst);
-
int cbfs_decompress(int algo, void *src, void *dst, int len)
{
switch(algo) {
Index: svn/src/arch/i386/boot/gdt.c
===
--- svn.orig/src/arch/i386/boot/gdt.c
+++ svn/src/arch/i386/boot/gdt.c
@@ -20,6 +20,7 @@
#include types.h
#include string.h
#include cbmem.h
+#include lib.h
#include console/console.h
// Global Descriptor Table, defined in c_start.S
@@ -33,7 +34,6 @@ struct gdtarg {
} __attribute__((packed));
// Copy GDT to new location and reload it
-void move_gdt(void);
void move_gdt(void)
{
void *newgdt;
Index: svn/src/arch/i386/boot/tables.c
===
--- svn.orig/src/arch/i386/boot/tables.c
+++ svn/src/arch/i386/boot/tables.c
@@ -30,11 +30,11 @@
#include cpu/x86/multiboot.h
#include coreboot_table.h
#include cbmem.h
+#include lib.h
uint64_t high_tables_base = 0;
uint64_t high_tables_size;
-void move_gdt(void);
void cbmem_arch_init(void)
{
/* defined in gdt.c */
Index: svn/src/boot/selfboot.c
===
--- svn.orig/src/boot/selfboot.c
+++ svn/src/boot/selfboot.c
@@ -28,6 +28,7 @@
#include stdlib.h
#include string.h
#include cbfs.h
+#include lib.h
#ifndef CONFIG_BIG_ENDIAN
#define ntohl(x) ( ((x0xff)24) | ((x0xff00)8) | \
@@ -462,7 +463,6 @@ static int load_self_segments(
switch(ptr-compression) {
case CBFS_COMPRESS_LZMA: {
printk_debug(using LZMA\n);
- unsigned long ulzma(unsigned char *src, unsigned char *dst);
len = ulzma(src, dest);
break;
}
Index: svn/src/lib/lzma.c
===
--- svn.orig/src/lib/lzma.c
+++ svn/src/lib/lzma.c
@@ -13,8 +13,7 @@ SDK 4.42, which is written and distribut
#include lzmadecode.c
#include console/console.h
#include string.h
-
-unsigned long ulzma(unsigned char * src, unsigned char * dst);
+#include lib.h
unsigned long ulzma(unsigned char * src, unsigned char * dst)
{
Index: svn/src/lib/xmodem.c
===
--- svn.orig/src/lib/xmodem.c
+++ svn/src/lib/xmodem.c
@@ -19,10 +19,7 @@
#include string.h
#include delay.h
-
-extern void uart8250_tx_byte(unsigned, unsigned char);
-extern int uart8250_can_rx_byte(unsigned);
-extern unsigned char uart8250_rx_byte(unsigned);
+#include uart8250.h
static int _inbyte(int msec)
{
Index: svn/src/console/vsprintf.c
===
--- svn.orig/src/console/vsprintf.c
+++ svn/src/console/vsprintf.c
@@ -20,6 +20,7 @@
*/
#include stdarg.h
+#include string.h
#include smp/spinlock.h
#include
Re: [coreboot] [PATCH] Add lib.h
On Wed, Oct 28, 2009 at 9:09 AM, Myles Watson myle...@gmail.com wrote: It also looks like xmodem.c could be dropped. There was at some point in the v3 discussions (3 years ago!) some idea that the Ultimate Recovery would be via serial line. But since we've never used xmodem.c AFAICT ... ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Add lib.h
Acked-by: Ronald G. Minnich rminn...@gmail.com Always good to find a home for lost prototypes. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Add lib.h
On Wed, Oct 28, 2009 at 10:11 AM, ron minnich rminn...@gmail.com wrote: On Wed, Oct 28, 2009 at 9:09 AM, Myles Watson myle...@gmail.com wrote: It also looks like xmodem.c could be dropped. There was at some point in the v3 discussions (3 years ago!) some idea that the Ultimate Recovery would be via serial line. But since we've never used xmodem.c AFAICT ... It's not that important to me. It's small and never compiled. Maybe someone will pick it up in the future. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4878 - in trunk/coreboot-v2/src: arch/i386/boot boot console include lib
Author: myles
Date: 2009-10-28 17:13:28 +0100 (Wed, 28 Oct 2009)
New Revision: 4878
Added:
trunk/coreboot-v2/src/include/lib.h
Modified:
trunk/coreboot-v2/src/arch/i386/boot/gdt.c
trunk/coreboot-v2/src/arch/i386/boot/tables.c
trunk/coreboot-v2/src/boot/selfboot.c
trunk/coreboot-v2/src/console/vsprintf.c
trunk/coreboot-v2/src/lib/cbfs.c
trunk/coreboot-v2/src/lib/clog2.c
trunk/coreboot-v2/src/lib/lzma.c
trunk/coreboot-v2/src/lib/xmodem.c
Log:
Create lib.h for homeless prototypes.
Signed-off-by: Myles Watson myle...@gmail.com
Acked-by: Ronald G. Minnich rminn...@gmail.com
Modified: trunk/coreboot-v2/src/arch/i386/boot/gdt.c
===
--- trunk/coreboot-v2/src/arch/i386/boot/gdt.c 2009-10-28 15:30:11 UTC (rev
4877)
+++ trunk/coreboot-v2/src/arch/i386/boot/gdt.c 2009-10-28 16:13:28 UTC (rev
4878)
@@ -20,6 +20,7 @@
#include types.h
#include string.h
#include cbmem.h
+#include lib.h
#include console/console.h
// Global Descriptor Table, defined in c_start.S
@@ -33,7 +34,6 @@
} __attribute__((packed));
// Copy GDT to new location and reload it
-void move_gdt(void);
void move_gdt(void)
{
void *newgdt;
Modified: trunk/coreboot-v2/src/arch/i386/boot/tables.c
===
--- trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-10-28 15:30:11 UTC
(rev 4877)
+++ trunk/coreboot-v2/src/arch/i386/boot/tables.c 2009-10-28 16:13:28 UTC
(rev 4878)
@@ -30,11 +30,11 @@
#include cpu/x86/multiboot.h
#include coreboot_table.h
#include cbmem.h
+#include lib.h
uint64_t high_tables_base = 0;
uint64_t high_tables_size;
-void move_gdt(void);
void cbmem_arch_init(void)
{
/* defined in gdt.c */
Modified: trunk/coreboot-v2/src/boot/selfboot.c
===
--- trunk/coreboot-v2/src/boot/selfboot.c 2009-10-28 15:30:11 UTC (rev
4877)
+++ trunk/coreboot-v2/src/boot/selfboot.c 2009-10-28 16:13:28 UTC (rev
4878)
@@ -28,6 +28,7 @@
#include stdlib.h
#include string.h
#include cbfs.h
+#include lib.h
#ifndef CONFIG_BIG_ENDIAN
#define ntohl(x) ( ((x0xff)24) | ((x0xff00)8) | \
@@ -462,7 +463,6 @@
switch(ptr-compression) {
case CBFS_COMPRESS_LZMA: {
printk_debug(using LZMA\n);
- unsigned long ulzma(unsigned char *src,
unsigned char *dst);
len = ulzma(src, dest);
break;
}
Modified: trunk/coreboot-v2/src/console/vsprintf.c
===
--- trunk/coreboot-v2/src/console/vsprintf.c2009-10-28 15:30:11 UTC (rev
4877)
+++ trunk/coreboot-v2/src/console/vsprintf.c2009-10-28 16:13:28 UTC (rev
4878)
@@ -20,6 +20,7 @@
*/
#include stdarg.h
+#include string.h
#include smp/spinlock.h
#include console/vtxprintf.h
@@ -48,8 +49,6 @@
return i;
}
-int sprintf(char *buf, const char *fmt, ...);
-
int sprintf(char *buf, const char *fmt, ...)
{
va_list args;
Added: trunk/coreboot-v2/src/include/lib.h
===
--- trunk/coreboot-v2/src/include/lib.h (rev 0)
+++ trunk/coreboot-v2/src/include/lib.h 2009-10-28 16:13:28 UTC (rev 4878)
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009, Myles Watson myle...@gmail.com
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
+ */
+
+/* This file is for nuisance prototypes that have no other home. */
+
+/* Defined in src/lib/clog2.c */
+unsigned long log2(unsigned long x);
+
+/* Defined in src/lib/lzma.c */
+unsigned long ulzma(unsigned char *src, unsigned char *dst);
+
+/* Defined in src/arch/i386/boot/gdt.c */
+void move_gdt(void);
+
Modified: trunk/coreboot-v2/src/lib/cbfs.c
===
--- trunk/coreboot-v2/src/lib/cbfs.c2009-10-28 15:30:11 UTC (rev 4877)
+++ trunk/coreboot-v2/src/lib/cbfs.c2009-10-28 16:13:28 UTC (rev 4878)
@@ -21,6 +21,7 @@
#include string.h
#include console/console.h
#include cbfs.h
Re: [coreboot] [PATCH] Add lib.h
On Wed, Oct 28, 2009 at 10:12 AM, ron minnich rminn...@gmail.com wrote: Acked-by: Ronald G. Minnich rminn...@gmail.com Always good to find a home for lost prototypes. :) Rev 4878. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] LPC/FWH/Parallel buses on Intel ICH, VIA VT82*
Hi, I'm trying to get an overview about which flash buses are supported on which chipsets. SPI support is pretty clear for all chipsets. For ICH I don't know if they ever supported LPC flash, and when Parallel support stopped and FWH support started (and if there was any overlap). For VIA VT82*, I heard that FWH flash was never supported, but I'm not sure when Parallel support stopped and LPC support started (and if there was any overlap). Any insights appreciated. Regards, Carl-Daniel -- Developer quote of the week: We are juggling too many chainsaws and flaming arrows and tigers. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] Remove all build/ prefixes in the build output
See patch.
Uwe.
--
http://www.hermann-uwe.de | http://www.randomprojects.org
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Remove all build/ prefixes in the build output.
Also, remove one missing hardcoded build dir in the distclean target,
and clean up files generated by sconfig in 'make clean'.
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Index: src/arch/i386/Makefile.inc
===
--- src/arch/i386/Makefile.inc (Revision 4877)
+++ src/arch/i386/Makefile.inc (Arbeitskopie)
@@ -31,6 +31,7 @@
@printf VGABIOS$(CONFIG_FALLBACK_VGA_BIOS_FILE) $(CONFIG_FALLBACK_VGA_BIOS_ID)\n
$(CBFSTOOL) $(obj)/coreboot.rom add $(CONFIG_FALLBACK_VGA_BIOS_FILE) pci$(CONFIG_FALLBACK_VGA_BIOS_ID).rom optionrom
endif
+ @printf CBFSPRINT $(subst $(obj)/,,$(@))\n\n
$(CBFSTOOL) $(obj)/coreboot.rom print
@@ -38,7 +39,7 @@
# Build the bootblock
$(obj)/coreboot.bootblock: $(obj)/coreboot
- @printf OBJCOPY$(subst $(shell pwd)/,,$(@))\n
+ @printf OBJCOPY$(subst $(obj)/,,$(@))\n
$(OBJCOPY) -O binary $ $@
$(obj)/ldscript.ld: $(ldscripts) $(obj)/ldoptions
@@ -55,7 +56,7 @@
$(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $ $...@.new mv $...@.new $@
$(obj)/coreboot: $(initobjs) $(obj)/ldscript.ld
- @printf LINK $(subst $(shell pwd)/,,$(@))\n
+ @printf LINK $(subst $(obj)/,,$(@))\n
$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(obj)/ldscript.ld $(initobjs)
$(NM) -n $(obj)/coreboot | sort $(obj)/coreboot.map
@@ -63,27 +64,27 @@
# i386 specific tools
$(obj)/option_table.h $(obj)/option_table.c: $(obj)/build_opt_tbl $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout
- @printf OPTION $(subst $(shell pwd)/,,$(@))\n
+ @printf OPTION $(subst $(obj)/,,$(@))\n
$(obj)/build_opt_tbl --config $(top)/src/mainboard/$(MAINBOARDDIR)/cmos.layout --header $(obj)/option_table.h --option $(obj)/option_table.c
$(obj)/build_opt_tbl: $(top)/util/options/build_opt_tbl.c $(top)/src/include/pc80/mc146818rtc.h $(top)/src/include/boot/coreboot_tables.h $(obj)/config.h
- @printf HOSTCC $(subst $(shell pwd)/,,$(@))\n
+ @printf HOSTCC $(subst $(obj)/,,$(@))\n
$(HOSTCC) $(HOSTCFLAGS) -include $(obj)/config.h $ -o $@
###
# Build the coreboot_ram (stage 2)
$(obj)/coreboot_ram: $(obj)/coreboot_ram.o $(src)/config/coreboot_ram.ld #ldoptions
- @printf CC $(subst $(shell pwd)/,,$(@))\n
+ @printf CC $(subst $(obj)/,,$(@))\n
$(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/config/coreboot_ram.ld $(obj)/coreboot_ram.o
$(NM) -n $(obj)/coreboot_ram | sort $(obj)/coreboot_ram.map
$(obj)/coreboot_ram.o: $(obj)/arch/i386/lib/c_start.o $(drivers) $(obj)/coreboot.a $(LIBGCC_FILE_NAME)
- @printf CC $(subst $(shell pwd)/,,$(@))\n
+ @printf CC $(subst $(obj)/,,$(@))\n
$(CC) -nostdlib -r -o $@ $(obj)/arch/i386/lib/c_start.o $(drivers) -Wl,-\( $(obj)/coreboot.a $(LIBGCC_FILE_NAME) -Wl,-\)
$(obj)/coreboot.a: $(objs)
- @printf AR $(subst $(shell pwd)/,,$(@))\n
+ @printf AR $(subst $(obj)/,,$(@))\n
rm -f $(obj)/coreboot.a
$(AR) cr $(obj)/coreboot.a $(objs)
Index: util/sconfig/yapps2.py
===
--- util/sconfig/yapps2.py (Revision 4877)
+++ util/sconfig/yapps2.py (Arbeitskopie)
@@ -710,7 +710,7 @@
if inputfilename[-2:]=='.g': outputfilename = inputfilename[:-2]+'.py'
else: raise Invalid Filename, outputfilename
-print 'SCONFIG ', join(outputfilename.split('/')[-5:], '/')
+print 'SCONFIG ', join(outputfilename.split('/')[-4:], '/')
DIVIDER = '\n%%\n' # This pattern separates the pre/post parsers
preparser, postparser = None, None # Code before and after the parser desc
Index: util/sconfig/config.g
===
--- util/sconfig/config.g (Revision 4877)
+++ util/sconfig/config.g (Arbeitskopie)
@@ -886,7 +886,7 @@
def writecode(image):
filename = os.path.join(img_dir, static.c)
- print SCONFIG , join(filename.split('/')[-5:], '/')
+ print SCONFIG , join(filename.split('/')[-4:], '/')
file = safe_open(filename, 'w+')
file.write(#include device/device.h\n)
file.write(#include device/pci.h\n)
@@ -920,7 +920,7 @@
def writegraph(image):
filename = os.path.join(img_dir, static.dot)
- print SCONFIG , join(filename.split('/')[-5:], '/')
+ print SCONFIG , join(filename.split('/')[-4:], '/')
file = safe_open(filename, 'w+')
file.write(digraph devicetree {\n)
file.write( rankdir=LR\n)
Index: util/sconfig/parsedesc.g
===
--- util/sconfig/parsedesc.g (Revision 4877)
+++
Re: [coreboot] [PATCH] Remove all build/ prefixes in the build output
On Wed, Oct 28, 2009 at 10:19 AM, Uwe Hermann u...@hermann-uwe.de wrote:
See patch.
Thanks for finding the build I missed.
I'd prefer having (This may take a while) on the next line so that it
doesn't wrap.
I prefer
-print 'SCONFIG Output File:', os.path.basename(
outputfilename)
over custom splits and joins.
+print 'SCONFIG ', join(outputfilename.split('/')[-5:], '/')
Can we go back to os.path.basename? If so:
Acked-by: Myles Watson myle...@gmail.com
Thanks,
Myles
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Re: [coreboot] [PATCH] D945GCLF
ron minnich wrote: Acked-by: Ronald G. Minnich rminn...@gmail.com thanks, r4879 -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Remove all build/ prefixes in the build output
On Wed, Oct 28, 2009 at 10:28 AM, Myles Watson myle...@gmail.com wrote:
On Wed, Oct 28, 2009 at 10:19 AM, Uwe Hermann u...@hermann-uwe.de wrote:
See patch.
Thanks for finding the build I missed.
I'd prefer having (This may take a while) on the next line so that it
doesn't wrap.
I prefer
-print 'SCONFIG Output File:', os.path.basename(
outputfilename)
over custom splits and joins.
+print 'SCONFIG ', join(outputfilename.split('/')[-5:], '/')
I can see the point to having part of the path there. It can help us keep
things in the correct directories. I keep finding places where we
accidentally put things in the top directory.
Acked-by: Myles Watson myle...@gmail.com
Thanks,
Myles
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Re: [coreboot] LPC/FWH/Parallel buses on Intel ICH, VIA VT82*
On Wed, 28 Oct 2009 17:17:11 +0100, Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net wrote: Hi, I'm trying to get an overview about which flash buses are supported on which chipsets. SPI support is pretty clear for all chipsets. For ICH I don't know if they ever supported LPC flash, and when Parallel support stopped and FWH support started (and if there was any overlap). For VIA VT82*, I heard that FWH flash was never supported, but I'm not sure when Parallel support stopped and LPC support started (and if there was any overlap). Any insights appreciated. Carl-Daniel, I know that every ICH board I have ever seen ships with fwh. Whether or not lpc would work on ICH (I have never seen docs indicating support) or not has yet to be seen. I think this would require extensive testing. It seems VIA boards almost always have lpc chips. Hope this helps. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4880 - in trunk/coreboot-v2: . src/arch/i386 util/cbfstool util/sconfig
Author: uwe
Date: 2009-10-28 18:10:51 +0100 (Wed, 28 Oct 2009)
New Revision: 4880
Modified:
trunk/coreboot-v2/Makefile
trunk/coreboot-v2/src/arch/i386/Makefile.inc
trunk/coreboot-v2/util/cbfstool/Makefile.inc
trunk/coreboot-v2/util/sconfig/config.g
trunk/coreboot-v2/util/sconfig/parsedesc.g
trunk/coreboot-v2/util/sconfig/yapps2.py
Log:
Remove all build/ prefixes in the build output.
Also, remove one missing hardcoded build dir in the distclean target,
and clean up files generated by sconfig in 'make clean'.
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Myles Watson myle...@gmail.com
Modified: trunk/coreboot-v2/Makefile
===
--- trunk/coreboot-v2/Makefile 2009-10-28 16:52:48 UTC (rev 4879)
+++ trunk/coreboot-v2/Makefile 2009-10-28 17:10:51 UTC (rev 4880)
@@ -159,49 +159,49 @@
define objs_c_template
$(obj)/$(1)%.o: src/$(1)%.c
- @printf CC $$(subst $$(shell pwd)/,,$$(@))\n
+ @printf CC $$(subst $$(obj)/,,$$(@))\n
$(CC) -m32 $$(CFLAGS) -c -o $$@ $$
endef
define objs_S_template
$(obj)/$(1)%.o: src/$(1)%.S
- @printf CC $$(subst $$(shell pwd)/,,$$(@))\n
+ @printf CC $$(subst $$(obj)/,,$$(@))\n
$(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$
endef
define initobjs_c_template
$(obj)/$(1)%.o: src/$(1)%.c
- @printf CC $$(subst $$(shell pwd)/,,$$(@))\n
+ @printf CC $$(subst $$(obj)/,,$$(@))\n
$(CC) -m32 $$(CFLAGS) -c -o $$@ $$
endef
define initobjs_S_template
$(obj)/$(1)%.o: src/$(1)%.S
- @printf CC $$(subst $$(shell pwd)/,,$$(@))\n
+ @printf CC $$(subst $$(obj)/,,$$(@))\n
$(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$
endef
define drivers_c_template
$(obj)/$(1)%.o: src/$(1)%.c
- @printf CC $$(subst $$(shell pwd)/,,$$(@))\n
+ @printf CC $$(subst $$(obj)/,,$$(@))\n
$(CC) -m32 $$(CFLAGS) -c -o $$@ $$
endef
define drivers_S_template
$(obj)/$(1)%.o: src/$(1)%.S
- @printf CC $$(subst $$(shell pwd)/,,$$(@))\n
+ @printf CC $$(subst $$(obj)/,,$$(@))\n
$(CC) -m32 -DASSEMBLY $$(CFLAGS) -c -o $$@ $$
endef
define smmobjs_c_template
$(obj)/$(1)%.o: src/$(1)%.c
- @printf CC $$(subst $$(shell pwd)/,,$$(@))\n
+ @printf CC $$(subst $$(obj)/,,$$(@))\n
$(CC) -m32 $$(CFLAGS) -c -o $$@ $$
endef
define smmobjs_S_template
$(obj)/$(1)%.o: src/$(1)%.S
- @printf CC $$(subst $$(shell pwd)/,,$$(@))\n
+ @printf CC $$(subst $$(obj)/,,$$(@))\n
$(CC) -m32 $$(CFLAGS) -c -o $$@ $$
endef
@@ -265,7 +265,7 @@
test -n $(alldirs) mkdir -p $(alldirs) || true
prepare2:
- @printf GEN$(subst $(shell pwd)/,,$(obj)/build.h)\n
+ @printf GENbuild.h\n
printf #define COREBOOT_VERSION \$(KERNELVERSION)\\n
$(obj)/build.h
printf #define COREBOOT_EXTRA_VERSION \$(COREBOOT_EXTRA_VERSION)\\n
$(obj)/build.h
printf #define COREBOOT_V2 \$(COREBOOT_V2)\\n $(obj)/build.h
@@ -294,9 +294,10 @@
rm -f $(obj)/mainboard/$(MAINBOARDDIR)/static.c
$(obj)/mainboard/$(MAINBOARDDIR)/config.py
$(obj)/mainboard/$(MAINBOARDDIR)/static.dot
rm -f $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc
$(obj)/mainboard/$(MAINBOARDDIR)/crt0.s
$(obj)/mainboard/$(MAINBOARDDIR)/crt0.disasm
rmdir -p $(alldirs) 2/dev/null /dev/null || true
+ $(MAKE) -C util/sconfig clean
distclean: clean
- rm -rf build
+ rm -rf $(obj)
rm -f .config .config.old ..config.tmp .kconfig.d .tmpconfig*
update:
@@ -311,7 +312,7 @@
awk '/^#define ([^])* ([^])*$$/ {print $$2 = $$3 ;;}' $ $@
$(obj)/romcc: $(top)/util/romcc/romcc.c
- @printf HOSTCC $(obj)/romcc (this may take a while)\n
+ @printf HOSTCC $(subst $(obj)/,,$(@)) (this may take a
while)\n
$(HOSTCC) -g -O2 -Wall -o $@ $
.PHONY: $(PHONY) prepare prepare2 clean distclean doxygen doxy coreboot
Modified: trunk/coreboot-v2/src/arch/i386/Makefile.inc
===
--- trunk/coreboot-v2/src/arch/i386/Makefile.inc2009-10-28 16:52:48 UTC
(rev 4879)
+++ trunk/coreboot-v2/src/arch/i386/Makefile.inc2009-10-28 17:10:51 UTC
(rev 4880)
@@ -31,6 +31,7 @@
@printf VGABIOS$(CONFIG_FALLBACK_VGA_BIOS_FILE)
$(CONFIG_FALLBACK_VGA_BIOS_ID)\n
$(CBFSTOOL) $(obj)/coreboot.rom add $(CONFIG_FALLBACK_VGA_BIOS_FILE)
pci$(CONFIG_FALLBACK_VGA_BIOS_ID).rom optionrom
endif
+ @printf CBFSPRINT $(subst $(obj)/,,$(@))\n\n
$(CBFSTOOL) $(obj)/coreboot.rom print
@@ -38,7 +39,7 @@
# Build the bootblock
$(obj)/coreboot.bootblock: $(obj)/coreboot
- @printf OBJCOPY$(subst $(shell pwd)/,,$(@))\n
+ @printf
Re: [coreboot] [PATCH] Remove all build/ prefixes in the build output
On Wed, Oct 28, 2009 at 10:28:48AM -0600, Myles Watson wrote:
Thanks for finding the build I missed.
No problem.
I'd prefer having (This may take a while) on the next line so that it
doesn't wrap.
Hm? I don't understand what exactly wraps here? It should be one line
only, no wrapping.
I prefer
-print 'SCONFIG Output File:', os.path.basename(
outputfilename)
over custom splits and joins.
+print 'SCONFIG ', join(outputfilename.split('/')[-5:], '/')
Can we go back to os.path.basename? If so:
We could, but that's not consistent. This is the output with os.path.basename:
SCONFIGconfig.py
SCONFIGstatic.c
SCONFIGstatic.dot
and this with the splits and joins:
SCONFIGmainboard/asus/p2b-f/config.py
SCONFIGmainboard/asus/p2b-f/static.c
SCONFIGmainboard/asus/p2b-f/static.dot
As we do print the paths (relative to the build dir) for the other
files in the build output, I think we should do that here too.
Acked-by: Myles Watson myle...@gmail.com
Thanks, r4880.
Uwe.
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[coreboot] build service results for r4879
Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 4879 to the coreboot repository. This caused the following changes: Change Log: preliminary Intel D945GCLF Atom+i945 support. ram init fails, as the i945 driver currently only supports the mobile version of the chipset.. Not sure how much sense it makes to check this in, but since it's a nice and cheap board, maybe someone wants to work on this. Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Ronald G. Minnich rminn...@gmail.com Build Log: Configuration of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4879device=d945gclfvendor=intelnum=1 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Remove all build/ prefixes in the build output
I'd prefer having (This may take a while) on the next line so that it doesn't wrap. Hm? I don't understand what exactly wraps here? It should be one line only, no wrapping. HOSTCC /home/myles/try/buildrom-devel/work/coreboot/svn/build/romcc (this may take a while) Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4881 - in trunk/coreboot-v2: src/cpu/intel/model_106cx src/cpu/intel/socket_441 src/mainboard/intel/d945gclf src/mainboard/intel/d945gclf/acpi src/superio/smsc/lpc47m15x targets/intel
Author: uwe Date: 2009-10-28 18:36:11 +0100 (Wed, 28 Oct 2009) New Revision: 4881 Modified: trunk/coreboot-v2/src/cpu/intel/model_106cx/Config.lb trunk/coreboot-v2/src/cpu/intel/model_106cx/cache_as_ram_disable.c trunk/coreboot-v2/src/cpu/intel/model_106cx/cache_as_ram_post.c trunk/coreboot-v2/src/cpu/intel/model_106cx/model_6cx_init.c trunk/coreboot-v2/src/cpu/intel/socket_441/Config.lb trunk/coreboot-v2/src/cpu/intel/socket_441/chip.h trunk/coreboot-v2/src/cpu/intel/socket_441/socket_441.c trunk/coreboot-v2/src/mainboard/intel/d945gclf/Config.lb trunk/coreboot-v2/src/mainboard/intel/d945gclf/Kconfig trunk/coreboot-v2/src/mainboard/intel/d945gclf/Makefile.inc trunk/coreboot-v2/src/mainboard/intel/d945gclf/Options.lb trunk/coreboot-v2/src/mainboard/intel/d945gclf/acpi/ec.asl trunk/coreboot-v2/src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl trunk/coreboot-v2/src/mainboard/intel/d945gclf/acpi/ich7_pci_irqs.asl trunk/coreboot-v2/src/mainboard/intel/d945gclf/acpi/mainboard.asl trunk/coreboot-v2/src/mainboard/intel/d945gclf/acpi/platform.asl trunk/coreboot-v2/src/mainboard/intel/d945gclf/acpi/superio.asl trunk/coreboot-v2/src/mainboard/intel/d945gclf/acpi/thermal.asl trunk/coreboot-v2/src/mainboard/intel/d945gclf/acpi/video.asl trunk/coreboot-v2/src/mainboard/intel/d945gclf/acpi_tables.c trunk/coreboot-v2/src/mainboard/intel/d945gclf/auto.c trunk/coreboot-v2/src/mainboard/intel/d945gclf/chip.h trunk/coreboot-v2/src/mainboard/intel/d945gclf/cmos.layout trunk/coreboot-v2/src/mainboard/intel/d945gclf/debug.c trunk/coreboot-v2/src/mainboard/intel/d945gclf/devicetree.cb trunk/coreboot-v2/src/mainboard/intel/d945gclf/dmi.h trunk/coreboot-v2/src/mainboard/intel/d945gclf/dsdt.asl trunk/coreboot-v2/src/mainboard/intel/d945gclf/fadt.c trunk/coreboot-v2/src/mainboard/intel/d945gclf/irq_tables.c trunk/coreboot-v2/src/mainboard/intel/d945gclf/mainboard.c trunk/coreboot-v2/src/mainboard/intel/d945gclf/mainboard_smi.c trunk/coreboot-v2/src/mainboard/intel/d945gclf/mptable.c trunk/coreboot-v2/src/mainboard/intel/d945gclf/power_reset_check.c trunk/coreboot-v2/src/mainboard/intel/d945gclf/reset.c trunk/coreboot-v2/src/superio/smsc/lpc47m15x/Config.lb trunk/coreboot-v2/src/superio/smsc/lpc47m15x/chip.h trunk/coreboot-v2/src/superio/smsc/lpc47m15x/lpc47m15x.h trunk/coreboot-v2/src/superio/smsc/lpc47m15x/lpc47m15x_early_serial.c trunk/coreboot-v2/src/superio/smsc/lpc47m15x/superio.c trunk/coreboot-v2/targets/intel/d945gclf/Config-abuild.lb Log: Add some missing license headers, consistency fixes for others (trivial). Signed-off-by: Uwe Hermann u...@hermann-uwe.de Acked-by: Uwe Hermann u...@hermann-uwe.de Modified: trunk/coreboot-v2/src/cpu/intel/model_106cx/Config.lb === --- trunk/coreboot-v2/src/cpu/intel/model_106cx/Config.lb 2009-10-28 17:10:51 UTC (rev 4880) +++ trunk/coreboot-v2/src/cpu/intel/model_106cx/Config.lb 2009-10-28 17:36:11 UTC (rev 4881) @@ -1,3 +1,22 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2009 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + uses CONFIG_HAVE_MOVNTI default CONFIG_HAVE_MOVNTI=1 Modified: trunk/coreboot-v2/src/cpu/intel/model_106cx/cache_as_ram_disable.c === --- trunk/coreboot-v2/src/cpu/intel/model_106cx/cache_as_ram_disable.c 2009-10-28 17:10:51 UTC (rev 4880) +++ trunk/coreboot-v2/src/cpu/intel/model_106cx/cache_as_ram_disable.c 2009-10-28 17:36:11 UTC (rev 4881) @@ -5,8 +5,7 @@ * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. + * published by the Free Software Foundation; version 2 of the License. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of @@ -15,8 +14,7 @@ * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software - * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, - * MA 02110-1301 USA + * Foundation,
[coreboot] Accidentally broken builds with kconfig
[11/115] amd/serengeti_cheetah_fam10 fail. [34/115] digitallogic/adl855pc fail. [38/115] emulation/qemu-x86 fail. [49/115] intel/eagleheights fail. [68/115] msi/ms7135 fail. [70/115] msi/ms9185 fail. [77/115] pcengines/alix1c fail. [83/115] supermicro/h8dmr_fam10 fail. [85/115] supermicro/x6dhe_g fail. [86/115] supermicro/x6dhe_g2 fail. [91/115] technologic/ts5300 fail. [98/115] tyan/s2880 fail. [100/115] tyan/s2882 fail. [106/115] tyan/s2912_fam10 fail. [111/115] via/epia-m700 fail. [115/115] via/vt8454c fail. I admit that some of these are my fault. I think it's time to add kbuildall to qa.coreboot.org. If we could track the number of warnings for each build that would be helpful to. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r4880
Dear coreboot readers! This is the automatic build system of coreboot. The developer uwe checked in revision 4880 to the coreboot repository. This caused the following changes: Change Log: Remove all build/ prefixes in the build output. Also, remove one missing hardcoded build dir in the distclean target, and clean up files generated by sconfig in 'make clean'. Signed-off-by: Uwe Hermann u...@hermann-uwe.de Acked-by: Myles Watson myle...@gmail.com Build Log: Configuration of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4880device=d945gclfvendor=intelnum=1 If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r4881
Dear coreboot readers! This is the automatic build system of coreboot. The developer uwe checked in revision 4881 to the coreboot repository. This caused the following changes: Change Log: Add some missing license headers, consistency fixes for others (trivial). Signed-off-by: Uwe Hermann u...@hermann-uwe.de Acked-by: Uwe Hermann u...@hermann-uwe.de Build Log: Configuration of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4881device=d945gclfvendor=intelnum=1 If something broke during this checkin please be a pain in uwe's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Remove all build/ prefixes in the build output
On Wed, Oct 28, 2009 at 11:17:17AM -0600, Myles Watson wrote: I'd prefer having (This may take a while) on the next line so that it doesn't wrap. Hm? I don't understand what exactly wraps here? It should be one line only, no wrapping. HOSTCC /home/myles/try/buildrom-devel/work/coreboot/svn/build/romcc (this may take a while) Ah, that was fixed by the following hunk in my patch: - @printf HOSTCC $(obj)/romcc (this may take a while)\n + @printf HOSTCC $(subst $(obj)/,,$(@)) (this may take a while)\n Uwe. -- http://www.hermann-uwe.de | http://www.randomprojects.org http://www.crazy-hacks.org | http://www.unmaintained-free-software.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4882 - in trunk/coreboot-v2: src/cpu/intel src/cpu/intel/model_106cx src/mainboard/intel/d945gclf src/superio/smsc src/superio/smsc/lpc47m15x targets/intel/d945gclf
Author: myles Date: 2009-10-28 19:51:47 +0100 (Wed, 28 Oct 2009) New Revision: 4882 Added: trunk/coreboot-v2/src/superio/smsc/lpc47m15x/Makefile.inc trunk/coreboot-v2/targets/intel/d945gclf/Config.lb Modified: trunk/coreboot-v2/src/cpu/intel/Makefile.inc trunk/coreboot-v2/src/cpu/intel/model_106cx/Config.lb trunk/coreboot-v2/src/mainboard/intel/d945gclf/Kconfig trunk/coreboot-v2/src/superio/smsc/Kconfig trunk/coreboot-v2/src/superio/smsc/Makefile.inc trunk/coreboot-v2/src/superio/smsc/lpc47m15x/superio.c Log: Make d945gclf build. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson myle...@gmail.com Modified: trunk/coreboot-v2/src/cpu/intel/Makefile.inc === --- trunk/coreboot-v2/src/cpu/intel/Makefile.inc2009-10-28 17:36:11 UTC (rev 4881) +++ trunk/coreboot-v2/src/cpu/intel/Makefile.inc2009-10-28 18:51:47 UTC (rev 4882) @@ -3,6 +3,7 @@ # # Therefore: ONLY include Makefile.inc from socket directories! +subdirs-$(CONFIG_CPU_INTEL_SOCKET_411) += socket_411 subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += bga956 subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579 subdirs-$(CONFIG_CPU_INTEL_SOCKET_MFCPGA478) += socket_mFCPGA478 Modified: trunk/coreboot-v2/src/cpu/intel/model_106cx/Config.lb === --- trunk/coreboot-v2/src/cpu/intel/model_106cx/Config.lb 2009-10-28 17:36:11 UTC (rev 4881) +++ trunk/coreboot-v2/src/cpu/intel/model_106cx/Config.lb 2009-10-28 18:51:47 UTC (rev 4882) @@ -22,8 +22,6 @@ dir /cpu/x86/tsc dir /cpu/x86/mtrr -dir /cpu/x86/fpu -dir /cpu/x86/sse dir /cpu/x86/lapic dir /cpu/x86/cache dir /cpu/x86/smm Modified: trunk/coreboot-v2/src/mainboard/intel/d945gclf/Kconfig === --- trunk/coreboot-v2/src/mainboard/intel/d945gclf/Kconfig 2009-10-28 17:36:11 UTC (rev 4881) +++ trunk/coreboot-v2/src/mainboard/intel/d945gclf/Kconfig 2009-10-28 18:51:47 UTC (rev 4882) @@ -21,18 +21,18 @@ bool D945GCLF select ARCH_X86 select CPU_INTEL_CORE - select CPU_INTEL_SOCKET_MFCPGA478 + select CPU_INTEL_SOCKET_411 select NORTHBRIDGE_INTEL_I945 select SOUTHBRIDGE_INTEL_I82801GX - select SUPERIO_WINBOND_W83627THG + select SUPERIO_SMSC_LPC47M15X select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select MMCONF_SUPPORT select USE_PRINTK_IN_CAR select AP_IN_SIPI_WAIT select UDELAY_LAPIC - select HAVE_ACPI_TABLES - select HAVE_SMI_HANDLER + #select HAVE_ACPI_TABLES + #select HAVE_SMI_HANDLER select BOARD_ROMSIZE_KB_1024 config MAINBOARD_DIR @@ -79,3 +79,8 @@ int default 2 depends on BOARD_INTEL_D945GCLF + +config HAVE_INIT_TIMER + bool + default n + depends on BOARD_INTEL_D945GCLF Modified: trunk/coreboot-v2/src/superio/smsc/Kconfig === --- trunk/coreboot-v2/src/superio/smsc/Kconfig 2009-10-28 17:36:11 UTC (rev 4881) +++ trunk/coreboot-v2/src/superio/smsc/Kconfig 2009-10-28 18:51:47 UTC (rev 4882) @@ -6,6 +6,8 @@ bool config SUPERIO_SMSC_LPC47M10X bool +config SUPERIO_SMSC_LPC47M15X + bool config SUPERIO_SMSC_LPC47N217 bool config SUPERIO_SMSC_SMSCSUPERIO Modified: trunk/coreboot-v2/src/superio/smsc/Makefile.inc === --- trunk/coreboot-v2/src/superio/smsc/Makefile.inc 2009-10-28 17:36:11 UTC (rev 4881) +++ trunk/coreboot-v2/src/superio/smsc/Makefile.inc 2009-10-28 18:51:47 UTC (rev 4882) @@ -2,5 +2,6 @@ subdirs-y += lpc47b272 subdirs-y += lpc47b397 subdirs-y += lpc47m10x +subdirs-y += lpc47m15x subdirs-y += lpc47n217 subdirs-y += smscsuperio Copied: trunk/coreboot-v2/src/superio/smsc/lpc47m15x/Makefile.inc (from rev 4881, trunk/coreboot-v2/src/superio/smsc/lpc47m10x/Makefile.inc) === --- trunk/coreboot-v2/src/superio/smsc/lpc47m15x/Makefile.inc (rev 0) +++ trunk/coreboot-v2/src/superio/smsc/lpc47m15x/Makefile.inc 2009-10-28 18:51:47 UTC (rev 4882) @@ -0,0 +1,2 @@ +#config chip.h +obj-$(CONFIG_SUPERIO_SMSC_LPC47M15X) += superio.o Property changes on: trunk/coreboot-v2/src/superio/smsc/lpc47m15x/Makefile.inc ___ Added: svn:mergeinfo + Modified: trunk/coreboot-v2/src/superio/smsc/lpc47m15x/superio.c === --- trunk/coreboot-v2/src/superio/smsc/lpc47m15x/superio.c 2009-10-28 17:36:11 UTC (rev 4881) +++ trunk/coreboot-v2/src/superio/smsc/lpc47m15x/superio.c 2009-10-28 18:51:47 UTC (rev 4882) @@ -35,7 +35,6 @@ // Forward declarations static void
[coreboot] [v2] r4883 - in trunk/coreboot-v2/src/mainboard: . digitallogic/adl855pc emulation/qemu-x86 intel/eagleheights msi/ms9185 tyan/s2850 tyan/s2875 tyan/s2880 tyan/s2881 tyan/s2882 tyan/s2885
Author: myles Date: 2009-10-28 19:57:06 +0100 (Wed, 28 Oct 2009) New Revision: 4883 Modified: trunk/coreboot-v2/src/mainboard/Makefile.k8_CAR.inc trunk/coreboot-v2/src/mainboard/Makefile.k8_ck804.inc trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Kconfig trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Kconfig trunk/coreboot-v2/src/mainboard/intel/eagleheights/Makefile.inc trunk/coreboot-v2/src/mainboard/msi/ms9185/Kconfig trunk/coreboot-v2/src/mainboard/tyan/s2850/Makefile.inc trunk/coreboot-v2/src/mainboard/tyan/s2875/Makefile.inc trunk/coreboot-v2/src/mainboard/tyan/s2880/Makefile.inc trunk/coreboot-v2/src/mainboard/tyan/s2881/Makefile.inc trunk/coreboot-v2/src/mainboard/tyan/s2882/Makefile.inc trunk/coreboot-v2/src/mainboard/tyan/s2885/Makefile.inc Log: Fix some builds with Kconfig. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson myle...@gmail.com Modified: trunk/coreboot-v2/src/mainboard/Makefile.k8_CAR.inc === --- trunk/coreboot-v2/src/mainboard/Makefile.k8_CAR.inc 2009-10-28 18:51:47 UTC (rev 4882) +++ trunk/coreboot-v2/src/mainboard/Makefile.k8_CAR.inc 2009-10-28 18:57:06 UTC (rev 4883) @@ -49,11 +49,11 @@ ifdef POST_EVALUATION -$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl - iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl - mv dsdt.hex $@ +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl + iasl -p $(obj)/mainboard/$(MAINBOARDDIR)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl + mv $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.hex $@ -$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.c $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $ -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h Modified: trunk/coreboot-v2/src/mainboard/Makefile.k8_ck804.inc === --- trunk/coreboot-v2/src/mainboard/Makefile.k8_ck804.inc 2009-10-28 18:51:47 UTC (rev 4882) +++ trunk/coreboot-v2/src/mainboard/Makefile.k8_ck804.inc 2009-10-28 18:57:06 UTC (rev 4883) @@ -53,11 +53,11 @@ ifdef POST_EVALUATION -$(obj)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl - iasl -p dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl - mv dsdt.hex $@ +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.c: $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl + iasl -p $(obj)/mainboard/$(MAINBOARDDIR)/dsdt -tc $(src)/mainboard/$(MAINBOARDDIR)/dsdt.dsl + mv $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.hex $@ -$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/dsdt.c +$(obj)/mainboard/$(MAINBOARDDIR)/dsdt.o: $(obj)/mainboard/$(MAINBOARDDIR)/dsdt.c $(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(src) -I. -c $ -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/auto.inc: $(src)/mainboard/$(MAINBOARDDIR)/cache_as_ram_auto.c $(obj)/option_table.h Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Kconfig === --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Kconfig 2009-10-28 18:51:47 UTC (rev 4882) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Kconfig 2009-10-28 18:57:06 UTC (rev 4883) @@ -8,7 +8,6 @@ select HAVE_PIRQ_TABLE select UDELAY_TSC select BOARD_ROMSIZE_KB_1024 - select HAVE_HARD_RESET config MAINBOARD_DIR string Modified: trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb === --- trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb 2009-10-28 18:51:47 UTC (rev 4882) +++ trunk/coreboot-v2/src/mainboard/digitallogic/adl855pc/Options.lb 2009-10-28 18:57:06 UTC (rev 4883) @@ -2,7 +2,6 @@ uses CONFIG_GENERATE_PIRQ_TABLE uses CONFIG_USE_FALLBACK_IMAGE uses CONFIG_HAVE_FALLBACK_BOOT -uses CONFIG_HAVE_HARD_RESET uses CONFIG_HAVE_OPTION_TABLE uses CONFIG_USE_OPTION_TABLE uses CONFIG_ROM_PAYLOAD @@ -55,11 +54,6 @@ default CONFIG_GENERATE_MP_TABLE=0 ## -## Build code to reset the motherboard from coreboot -## -default CONFIG_HAVE_HARD_RESET=1 - -## ## use io based udelay function ## default CONFIG_UDELAY_IO=1 Modified: trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Kconfig === --- trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Kconfig 2009-10-28 18:51:47 UTC (rev 4882) +++ trunk/coreboot-v2/src/mainboard/emulation/qemu-x86/Kconfig 2009-10-28 18:57:06 UTC (rev 4883) @@ -20,3 +20,8 @@ int default 6 depends on
Re: [coreboot] [v2] r4883 - in trunk/coreboot-v2/src/mainboard: . digitallogic/adl855pc emulation/qemu-x86 intel/eagleheights msi/ms9185 tyan/s2850 tyan/s2875 tyan/s2880 tyan/s2881 tyan/s2882 tyan/s28
These are the non-fam10 boards that still need help to build with Kconfig: intel_d945gclf msi_ms7135 supermicro_x6dhe_g supermicro_x6dhe_g2 technologic_ts5300 Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r4882
Dear coreboot readers! This is the automatic build system of coreboot. The developer myles checked in revision 4882 to the coreboot repository. This caused the following changes: Change Log: Make d945gclf build. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson myle...@gmail.com Build Log: Configuration of intel:d945gclf has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4884 - in trunk/coreboot-v2/src: . arch include/cpu
Author: stepan Date: 2009-10-28 20:38:58 +0100 (Wed, 28 Oct 2009) New Revision: 4884 Removed: trunk/coreboot-v2/src/arch/ppc/ trunk/coreboot-v2/src/include/cpu/ppc/ Modified: trunk/coreboot-v2/src/Kconfig Log: Drop remainder of PPC port Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Ronald G. Minnich rminn...@gmail.com Modified: trunk/coreboot-v2/src/Kconfig === --- trunk/coreboot-v2/src/Kconfig 2009-10-28 18:57:06 UTC (rev 4883) +++ trunk/coreboot-v2/src/Kconfig 2009-10-28 19:38:58 UTC (rev 4884) @@ -51,7 +51,6 @@ source src/mainboard/Kconfig source src/arch/i386/Kconfig -source src/arch/ppc/Kconfig menu Chipset -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4885 - trunk/coreboot-v2/src/northbridge
Author: stepan Date: 2009-10-28 20:40:46 +0100 (Wed, 28 Oct 2009) New Revision: 4885 Removed: trunk/coreboot-v2/src/northbridge/ibm/ trunk/coreboot-v2/src/northbridge/motorola/ Modified: trunk/coreboot-v2/src/northbridge/Kconfig trunk/coreboot-v2/src/northbridge/Makefile.inc Log: Drop remainders of PPC port Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Ronald G. Minnich rminn...@gmail.com Modified: trunk/coreboot-v2/src/northbridge/Kconfig === --- trunk/coreboot-v2/src/northbridge/Kconfig 2009-10-28 19:38:58 UTC (rev 4884) +++ trunk/coreboot-v2/src/northbridge/Kconfig 2009-10-28 19:40:46 UTC (rev 4885) @@ -1,5 +1,3 @@ source src/northbridge/amd/Kconfig -#source src/northbridge/ibm/Kconfig source src/northbridge/intel/Kconfig -#source src/northbridge/motorola/Kconfig source src/northbridge/via/Kconfig Modified: trunk/coreboot-v2/src/northbridge/Makefile.inc === --- trunk/coreboot-v2/src/northbridge/Makefile.inc 2009-10-28 19:38:58 UTC (rev 4884) +++ trunk/coreboot-v2/src/northbridge/Makefile.inc 2009-10-28 19:40:46 UTC (rev 4885) @@ -1,5 +1,3 @@ subdirs-y += amd -#subdirs-y += ibm subdirs-y += intel -#subdirs-y += motorola subdirs-y += via -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4886 - in trunk/coreboot-v2/util: . amdtools amdtools/example_input
Author: ward Date: 2009-10-28 20:41:52 +0100 (Wed, 28 Oct 2009) New Revision: 4886 Added: trunk/coreboot-v2/util/amdtools/ trunk/coreboot-v2/util/amdtools/README trunk/coreboot-v2/util/amdtools/example_input/ trunk/coreboot-v2/util/amdtools/example_input/coreboot-48G-667MHz-memsettings trunk/coreboot-v2/util/amdtools/example_input/coreboot-48G-667MHz-memsettings-20090909h trunk/coreboot-v2/util/amdtools/example_input/lspci-cb-48G-667MHz-18.2-20090909e trunk/coreboot-v2/util/amdtools/example_input/lspci-prop-48G-667MHz-18.2 trunk/coreboot-v2/util/amdtools/k8-compare-pci-space.pl trunk/coreboot-v2/util/amdtools/k8-interpret-extended-memory-settings.pl trunk/coreboot-v2/util/amdtools/k8-read-mem-settings.sh trunk/coreboot-v2/util/amdtools/parse-bkdg.pl Log: Add an initial version of some tools to compare (extended) K8 memory settings. This generates (dirty) html with interpreted differences between PCI dumps, based on the K8 socket F bkdg. Signed-off-by: Ward Vandewege w...@gnu.org Acked-by: Stepan Reinauer ste...@coresystems.de Added: trunk/coreboot-v2/util/amdtools/README === --- trunk/coreboot-v2/util/amdtools/README (rev 0) +++ trunk/coreboot-v2/util/amdtools/README 2009-10-28 19:41:52 UTC (rev 4886) @@ -0,0 +1,32 @@ + + +This is a set of tools to compare (extended) K8 memory settings. + +Before you can use them, you need to massage the relevant BKDG sections into +useable data. Here's how. + +First, you need to acquire a copy of the K8 BKDG. Go here: + + Rev F: http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/32559.pdf + +Then make sure pdftotext is installed (it's in the poppler-utils package on Debian/Ubuntu). + +Now run the bkdg through pdftotext: + + pdftotext -layout 32559.pdf 32559.txt + +Now extract sections 4.5.15 - 4.5.19 from the file, and save it separately, say as bkdg-raw.data. + +Finally run the txt file through the parse-bkdg.pl script like so: + + parse-bkdg.pl bkdg-raw.data bkdg.data + +Now we have the bkdg.data file that is used by the other scripts. + +If you want to test the scripts without doing all this work, you can use some +sample input files from the 'example_input/' directory. + +-- +Ward Vandewege, 2009-10-28. +w...@jhvc.com + Added: trunk/coreboot-v2/util/amdtools/example_input/coreboot-48G-667MHz-memsettings === --- trunk/coreboot-v2/util/amdtools/example_input/coreboot-48G-667MHz-memsettings (rev 0) +++ trunk/coreboot-v2/util/amdtools/example_input/coreboot-48G-667MHz-memsettings 2009-10-28 19:41:52 UTC (rev 4886) @@ -0,0 +1,96 @@ +0:18.2 98.l: 8000 +0:18.2 9C.l: 00111222 +0:18.2 98.l: 8001 +0:18.2 9C.l: 16171715 +0:18.2 98.l: 8002 +0:18.2 9C.l: 1716131a +0:18.2 98.l: 8003 +0:18.2 9C.l: 0019 +0:18.2 98.l: 8004 +0:18.2 9C.l: 002f +0:18.2 98.l: 8005 +0:18.2 9C.l: 18191918 +0:18.2 98.l: 8006 +0:18.2 9C.l: 16161917 +0:18.2 98.l: 8007 +0:18.2 9C.l: 0017 +0:18.2 98.l: 8020 +0:18.2 9C.l: 00111222 +0:18.2 98.l: 8021 +0:18.2 9C.l: +0:18.2 98.l: 8022 +0:18.2 9C.l: +0:18.2 98.l: 8023 +0:18.2 9C.l: +0:18.2 98.l: 8024 +0:18.2 9C.l: +0:18.2 98.l: 8025 +0:18.2 9C.l: 2f2f2f2f +0:18.2 98.l: 8026 +0:18.2 9C.l: 2f2f2f2f +0:18.2 98.l: 8027 +0:18.2 9C.l: +0:18.2 98.l: 8010 +0:18.2 9C.l: +0:18.2 98.l: 8013 +0:18.2 9C.l: +0:18.2 98.l: 8016 +0:18.2 9C.l: 003f +0:18.2 98.l: 8019 +0:18.2 9C.l: 0046 +0:18.2 98.l: 8030 +0:18.2 9C.l: +0:18.2 98.l: 8033 +0:18.2 9C.l: +0:18.2 98.l: 8036 +0:18.2 9C.l: 0053 +0:18.2 98.l: 8039 +0:18.2 9C.l: 0053 +0:19.2 98.l: 8000 +0:19.2 9C.l: 00111222 +0:19.2 98.l: 8001 +0:19.2 9C.l: 15151515 +0:19.2 98.l: 8002 +0:19.2 9C.l: 15151515 +0:19.2 98.l: 8003 +0:19.2 9C.l: 0015 +0:19.2 98.l: 8004 +0:19.2 9C.l: 002f +0:19.2 98.l: 8005 +0:19.2 9C.l: 19181918 +0:19.2 98.l: 8006 +0:19.2 9C.l: 191a1817 +0:19.2 98.l: 8007 +0:19.2 9C.l: 0017 +0:19.2 98.l: 8020 +0:19.2 9C.l: 00111222 +0:19.2 98.l: 8021 +0:19.2 9C.l: +0:19.2 98.l: 8022 +0:19.2 9C.l: +0:19.2 98.l: 8023 +0:19.2 9C.l: +0:19.2 98.l: 8024 +0:19.2 9C.l: +0:19.2 98.l: 8025 +0:19.2 9C.l: 2f2f2f2f +0:19.2 98.l: 8026 +0:19.2 9C.l: 2f2f2f2f +0:19.2 98.l: 8027 +0:19.2 9C.l: +0:19.2 98.l: 8010 +0:19.2 9C.l: +0:19.2 98.l: 8013 +0:19.2 9C.l: +0:19.2 98.l: 8016 +0:19.2 9C.l: 003b +0:19.2 98.l: 8019 +0:19.2 9C.l: 0047 +0:19.2 98.l: 8030 +0:19.2 9C.l: +0:19.2 98.l: 8033 +0:19.2 9C.l: +0:19.2 98.l: 8036 +0:19.2 9C.l: 0053 +0:19.2 98.l: 8039 +0:19.2 9C.l: 0053
[coreboot] build service results for r4883
Dear coreboot readers! This is the automatic build system of coreboot. The developer myles checked in revision 4883 to the coreboot repository. This caused the following changes: Change Log: Fix some builds with Kconfig. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson myle...@gmail.com Build Log: Compilation of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4883device=d945gclfvendor=intelnum=2 If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [v2] r4887 - trunk/coreboot-v2/targets/intel/d945gclf
Author: myles Date: 2009-10-28 20:56:34 +0100 (Wed, 28 Oct 2009) New Revision: 4887 Modified: trunk/coreboot-v2/targets/intel/d945gclf/Config-abuild.lb Log: Comment out option ROM line in Config-abuild.lb to fix build. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson myle...@gmail.com Modified: trunk/coreboot-v2/targets/intel/d945gclf/Config-abuild.lb === --- trunk/coreboot-v2/targets/intel/d945gclf/Config-abuild.lb 2009-10-28 19:41:52 UTC (rev 4886) +++ trunk/coreboot-v2/targets/intel/d945gclf/Config-abuild.lb 2009-10-28 19:56:34 UTC (rev 4887) @@ -42,5 +42,5 @@ end buildrom ./coreboot.rom CONFIG_ROM_SIZE normal fallback -pci_rom ../../../misc/d945gclf-pci8086,2772.rom vendor_id=0x8086 device_id=0x2772 +#pci_rom ../../../misc/d945gclf-pci8086,2772.rom vendor_id=0x8086 device_id=0x2772 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb
See patch.
Uwe.
--
http://www.hermann-uwe.de | http://www.randomprojects.org
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb.
Since we have CBFS setting rom_address in board files is no longer
necessary.
Also, drop vga_rom_address from RS690 completely, it was never used
in the code.
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Index: src/southbridge/amd/rs690/chip.h
===
--- src/southbridge/amd/rs690/chip.h (Revision 4886)
+++ src/southbridge/amd/rs690/chip.h (Arbeitskopie)
@@ -23,7 +23,6 @@
/* Member variables are defined in Config.lb. */
struct southbridge_amd_rs690_config
{
- u32 vga_rom_address; /* The location that the VGA rom has been appened. */
u8 gpp_configuration; /* The configuration of General Purpose Port, A/B/C/D/E. */
u8 port_enable; /* Which port is enabled? GFX(2,3), GPP(4,5,6,7) */
u8 gfx_dev2_dev3; /* for GFX Core initialization REFCLK_SEL */
Index: src/mainboard/iwill/dk8_htx/Config.lb
===
--- src/mainboard/iwill/dk8_htx/Config.lb (Revision 4886)
+++ src/mainboard/iwill/dk8_htx/Config.lb (Arbeitskopie)
@@ -234,7 +234,6 @@
device pci 1.0 off end
#chip drivers/pci/onboard
#device pci 6.0 on end
- # register rom_address = 0xfff8
#end
end
device pci 1.0 on
Index: src/mainboard/iwill/dk8_htx/devicetree.cb
===
--- src/mainboard/iwill/dk8_htx/devicetree.cb (Revision 4886)
+++ src/mainboard/iwill/dk8_htx/devicetree.cb (Arbeitskopie)
@@ -26,7 +26,6 @@
device pci 1.0 off end
#chip drivers/pci/onboard
#device pci 6.0 on end
- # register rom_address = 0xfff8
#end
end
device pci 1.0 on
Index: src/mainboard/broadcom/blast/Config.lb
===
--- src/mainboard/broadcom/blast/Config.lb (Revision 4886)
+++ src/mainboard/broadcom/blast/Config.lb (Arbeitskopie)
@@ -211,7 +211,6 @@
chip drivers/pci/onboard
device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
# if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
- register rom_address = 0xfff8
end
end
#when CONFIG_HT_CHAIN_END_UNITID_BASE CONFIG_HT_CHAIN_UNITID_BASE (6, )
@@ -220,7 +219,6 @@
#end
#chip drivers/pci/onboard
# device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
-# register rom_address = 0xfff8
#end
Index: src/mainboard/broadcom/blast/devicetree.cb
===
--- src/mainboard/broadcom/blast/devicetree.cb (Revision 4886)
+++ src/mainboard/broadcom/blast/devicetree.cb (Arbeitskopie)
@@ -109,7 +109,6 @@
chip drivers/pci/onboard
device pci 4.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed, fake one to get the rom_address
# if CONFIG_HT_CHAIN_END_UNITID_BASE=0, it is 5, if CONFIG_HT_CHAIN_END_UNITID_BASE=1, it is 4
- register rom_address = 0xfff8
end
end
#when CONFIG_HT_CHAIN_END_UNITID_BASE CONFIG_HT_CHAIN_UNITID_BASE (6, )
@@ -118,7 +117,6 @@
#end
#chip drivers/pci/onboard
# device pci 5.0 on end # it is in bcm5785_0 bus, but the device id can not be changed even unitid is changed
-# register rom_address = 0xfff8
#end
Index: src/mainboard/thomson/ip1000/Config.lb
Re: [coreboot] [PATCH] Drop all pre-CBFS rom_address entries in Config.lb/devicetree.cb
On Wed, Oct 28, 2009 at 1:58 PM, Uwe Hermann u...@hermann-uwe.de wrote:
See patch.
I think it would be nice to figure out what we do with the onboard device
at the same time.
from src/drivers/pci/onboard.c:
static void onboard_enable(device_t dev)
{
struct drivers_pci_onboard_config *conf;
conf = dev-chip_info;
dev-rom_address = conf-rom_address;
}
Does it make sense to change ROM handling so that only onboard devices can
have their ROMs run? That's the way it used to be, right?
Otherwise, maybe we don't need onboard anymore at all?
Thanks,
Myles
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[coreboot] build service results for r4884
Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 4884 to the coreboot repository. This caused the following changes: Change Log: Drop remainder of PPC port Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Ronald G. Minnich rminn...@gmail.com Build Log: Compilation of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4884device=d945gclfvendor=intelnum=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r4885
Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 4885 to the coreboot repository. This caused the following changes: Change Log: Drop remainders of PPC port Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Ronald G. Minnich rminn...@gmail.com Build Log: Compilation of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4885device=d945gclfvendor=intelnum=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] Add prototypes for wrapped libgcc calls
Signed-off-by: Myles Watson myle...@gmail.com
Thanks,
Myles
Index: svn/src/include/lib.h
===
--- svn.orig/src/include/lib.h
+++ svn/src/include/lib.h
@@ -28,3 +28,15 @@ unsigned long ulzma(unsigned char *src,
/* Defined in src/arch/i386/boot/gdt.c */
void move_gdt(void);
+/* Defined in src/lib/gcc.c */
+#define WRAP_LIBGCC_CALL(type, name) \
+ type __wrap_##name(type a, type b) { return __real_##name(a, b); }
+
+#define PROTO_WRAP_LIBGCC_CALL(type, name) \
+ type __real_##name(type a, type b) __attribute__((regparm(0))); \
+ type __wrap_##name(type a, type b);
+
+PROTO_WRAP_LIBGCC_CALL(long long, __divdi3)
+PROTO_WRAP_LIBGCC_CALL(unsigned long long, __udivdi3)
+PROTO_WRAP_LIBGCC_CALL(long long, __moddi3)
+PROTO_WRAP_LIBGCC_CALL(unsigned long long, __umoddi3)
Index: svn/src/lib/gcc.c
===
--- svn.orig/src/lib/gcc.c
+++ svn/src/lib/gcc.c
@@ -22,10 +22,7 @@
* compiler call specifies. Therefore we need a wrapper around those
* functions. See gcc bug PR41055 for more information.
*/
-
-#define WRAP_LIBGCC_CALL(type, name) \
- type __real_##name(type a, type b) __attribute__((regparm(0))); \
- type __wrap_##name(type a, type b) { return __real_##name(a, b); }
+#include lib.h
WRAP_LIBGCC_CALL(long long, __divdi3)
WRAP_LIBGCC_CALL(unsigned long long, __udivdi3)
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[coreboot] build service results for r4886
Dear coreboot readers! This is the automatic build system of coreboot. The developer ward checked in revision 4886 to the coreboot repository. This caused the following changes: Change Log: Add an initial version of some tools to compare (extended) K8 memory settings. This generates (dirty) html with interpreted differences between PCI dumps, based on the K8 socket F bkdg. Signed-off-by: Ward Vandewege w...@gnu.org Acked-by: Stepan Reinauer ste...@coresystems.de Build Log: Compilation of intel:d945gclf is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=4886device=d945gclfvendor=intelnum=2 If something broke during this checkin please be a pain in ward's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] consolidate K8M890 VGA code
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
Hello all,
Following patch changes the K8M890 VGA handling. It reverts the framebuffer size
to option based (similar what Uwe did) and also it uses GFXUMA to handle the
high_tables_start offset from memory top.
It adds HAVE_MOTHERBOARD_RESOURCES to kconfig because we do have the resources
;)
Signed-off-by: Rudolf Marek r.ma...@assembler.cz
Rudolf
-BEGIN PGP SIGNATURE-
Version: GnuPG v1.4.9 (GNU/Linux)
Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org
iEYEARECAAYFAkrooN8ACgkQ3J9wPJqZRNUGeACeM7QCbwiHj6QpTDaCojxC8NjK
Qy0AnAl61XJfK/UB1NQOd4gB5HYJ8pJV
=f8uT
-END PGP SIGNATURE-
Index: src/southbridge/via/k8t890/Kconfig
===
--- src/southbridge/via/k8t890/Kconfig (revision 4874)
+++ src/southbridge/via/k8t890/Kconfig (working copy)
@@ -1,3 +1,35 @@
config SOUTHBRIDGE_VIA_K8T890
bool
+
+config SOUTHBRIDGE_VIA_K8T890_VGA_EN
+ bool Enable onboard K8M890 graphics
+ default y
+ depends on SOUTHBRIDGE_VIA_K8T890
+ select VGA
+ select GFXUMA
+
+choice
+ prompt Framebuffer size
+ default K8M890_VIDEO_MB_32MB
+ depends on SOUTHBRIDGE_VIA_K8T890_VGA_EN
+
+config K8M890_VIDEO_MB_32MB
+ bool 32MB
+config K8M890_VIDEO_MB_64MB
+ bool 64MB
+config K8M890_VIDEO_MB_128MB
+ bool 128MB
+config K8M890_VIDEO_MB_256MB
+ bool 256MB
+
+endchoice
+
+config VIDEO_MB
+ int
+ default 0 if K8M890_VIDEO_MB_OFF
+ default 32 if K8M890_VIDEO_MB_32MB
+ default 64 if K8M890_VIDEO_MB_64MB
+ default 128 if K8M890_VIDEO_MB_128MB
+ default 256 if K8M890_VIDEO_MB_256MB
+ depends on SOUTHBRIDGE_VIA_K8T890_VGA_EN
Index: src/southbridge/via/k8t890/k8t890_dram.c
===
--- src/southbridge/via/k8t890/k8t890_dram.c (revision 4874)
+++ src/southbridge/via/k8t890/k8t890_dram.c (working copy)
@@ -67,47 +67,25 @@
}
+#if CONFIG_GFXUMA
+extern uint64_t uma_memory_base, uma_memory_size;
+#endif
+
static void dram_enable_k8m890(struct device *dev)
{
- dram_enable(dev);
-
+#if CONFIG_GFXUMA
+ msr_t msr;
+ uma_memory_size = (CONFIG_VIDEO_MB 20);
+ msr = rdmsr(TOP_MEM);
+ uma_memory_base = msr.lo - uma_memory_size;
+ printk_info(K8M890: UMA base is %llx\n, uma_memory_base);
/* enable VGA, so the bridges gets VGA_EN and resources are set */
pci_write_config8(dev, 0xa1, 0x80);
-}
-
-static struct resource *resmax;
-
-static void get_memres(void *gp, struct device *dev, struct resource *res)
-{
- unsigned int *fbsize = (unsigned int *) gp;
- uint64_t proposed_base = res-base + res-size - *fbsize;
-
- printk_debug(get_memres: res-base=%llx res-size=%llx %d %d %d\n,
- res-base, res-size, (res-size *fbsize),
- (!(proposed_base (*fbsize - 1))),
- (proposed_base ((uint64_t) 0x)));
-
- /* if we fit and also align OK, and must be below 4GB */
- if ((res-size *fbsize) (!(proposed_base (*fbsize - 1)))
- (proposed_base ((uint64_t) 0x) )) {
- resmax = res;
- }
-#if CONFIG_WRITE_HIGH_TABLES==1
-/* in arch/i386/boot/tables.c */
-extern uint64_t high_tables_base, high_tables_size;
-
- if ((high_tables_base) ((high_tables_base proposed_base)
- (high_tables_base (res-base + res-size {
- high_tables_base = proposed_base - high_tables_size;
- printk_debug(Moving the high_tables_base pointer to
-new base %llx\n, high_tables_base);
- }
#endif
+ dram_enable(dev);
+
}
-/*
- *
- */
int
k8m890_host_fb_size_get(void)
{
@@ -125,57 +103,29 @@
static void dram_init_fb(struct device *dev)
{
+#if CONFIG_GFXUMA
/* Important bits:
* Enable the internal GFX bit 7 of reg 0xa1 plus in same reg:
* bits 6:4 X fbuffer size will be 2^(X+2) or 100 = 64MB, 101 = 128MB
* bits 3:0 BASE [31:28]
* reg 0xa0 bits 7:1 BASE [27:21] bit0 enable CPU access
*/
- u8 tmp;
- uint64_t proposed_base;
unsigned int fbbits = 0;
- unsigned int fbsize;
+ u8 tmp;
int ret;
+ fbbits = ((log2(uma_memory_size 20) - 2) 4);
+ printk_info(K8M890: Using a %dMB framebuffer.\n, (unsigned int) (uma_memory_size 20));
- ret = get_option(fbbits, videoram_size);
- if (ret) {
- printk_warning(Failed to get videoram size (error %d), using default.\n, ret);
- fbbits = 5;
- }
-
- if ((fbbits 1) || (fbbits 7)) {
- printk_warning(Invalid videoram size (%d), using default.\n,
- 4 fbbits);
- fbbits = 5;
- }
-
- fbsize = 4 (fbbits + 20);
-
- resmax = NULL;
- search_global_resources(
-IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
-get_memres, (void *) fbsize);
-
- /* no space for FB */
- if (!resmax) {
- printk_err(VIA FB: no space for framebuffer in RAM\n);
- return;
- }
-
- proposed_base = resmax-base + resmax-size - fbsize;
- resmax-size -= fbsize;
-
- printk_info(K8M890: Using a %dMB framebuffer.\n, 4 fbbits);
-
/* Step 1: enable UMA but no FB */
pci_write_config8(dev, 0xa1, 0x80);
/* Step 2: enough is just the FB size, the CPU accessible address
[coreboot] build service results for r4887
Dear coreboot readers! This is the automatic build system of coreboot. The developer myles checked in revision 4887 to the coreboot repository. This caused the following changes: Change Log: Comment out option ROM line in Config-abuild.lb to fix build. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson myle...@gmail.com Build Log: Compilation of intel:d945gclf has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [v2] r4886 - in trunk/coreboot-v2/util: . amdtools amdtools/example_input
Hi Ward, was it intentional that you placed these tools below coreboot-v2/ in the tree? On 28.10.2009 20:41, s...@coreboot.org wrote: Author: ward New Revision: 4886 Added: trunk/coreboot-v2/util/amdtools/ Log: Add an initial version of some tools to compare (extended) K8 memory settings. Regards, Carl-Daniel -- Developer quote of the week: We are juggling too many chainsaws and flaming arrows and tigers. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] ACPI updates + S3 Resume without hole at 31MB
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hi Stefan, 1) is 0x600 as base for lowmem trampoline safe? it always makes me wonder, this was the reason why I did the realmode code which runs above 1MB ;) Maybe we can have that too and only copy the trampoline to the highmem save area and execute it there. This would mean all memory bellow 1MB is untouched. It should be safe. The lower 4kb are supposed to be untouched by the OS, according to some information I found, including an old mail of yours on S3 Resume. Aha, I think we could rework this and have the trampoline in CBMEM, because the trick to run realmode code over 1MB would work too. 2) Since I only use the value in auto.c I did not put this into a one line function called externally. If that is what you suggest, we can easily do that, though. Yes this is just for code to look same... 3) I think your SMM code corrupts lowmem, or I have not seen any backup of that mem? Maybe I'm wrong? No, that is true... 0x38000 + size of SMM relocator is wiped out. OK ;) 4) Changes to the stack What patch are you referring to? Well I think the previous one for CBMEM if I recall correctly or the ICH7 updates stuff. 5) Don't understand much the cbmem_reinit((u64)high_ram_base)) in CAR Very ugly. Maybe we can fix the K8M890 resource code? What factors influence the high_ram_base on that chipset? How early can we determine them? Yes I tried to fixed it with separate patch. Except some hacks like make the cbmem look like some proprietary ACPI table and walk acpi tables as for we do for resume but in car stage just to find out where the tables are... Speaking of hacks, we could remember the CBMEM base address in the low 4KB so we can find them again... Yes I tried that I used 0:4F0 for the PRT which is some 'user data area'. I'm having trouble with CBMEM refusing me to create the ACPI RESUME table. However the bits I have rewritten to use the 0:4F0 trampoline are OK. Rudolf -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.9 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkroxGYACgkQ3J9wPJqZRNVO5wCeKH96JfOLZep/VEmLnGl4S6Tk aCMAnA/C/qXvGo/qiBPFwe1qeS3rY//y =25u2 -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] consolidate K8M890 VGA code
fbbits = ((log2(uma_memory_size 20) - 2) 4); Why not use CONFIG_VIDEO_MB here? If it is going to be fixed at compile time, it seems like you can get rid of uma_memory_size. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] consolidate K8M890 VGA code
On Wed, Oct 28, 2009 at 4:44 PM, Myles Watson myle...@gmail.com wrote: fbbits = ((log2(uma_memory_size 20) - 2) 4); Why not use CONFIG_VIDEO_MB here? If it is going to be fixed at compile time, it seems like you can get rid of uma_memory_size. Either way: Acked-by: Myles Watson myle...@gmail.com Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] consolidate K8M890 VGA code
On Wed, Oct 28, 2009 at 10:53:41PM +0100, Rudolf Marek wrote: -BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Hello all, Following patch changes the K8M890 VGA handling. It reverts the framebuffer size to option based (similar what Uwe did) and also it uses GFXUMA to handle the high_tables_start offset from memory top. It adds HAVE_MOTHERBOARD_RESOURCES to kconfig because we do have the resources ;) Signed-off-by: Rudolf Marek r.ma...@assembler.cz Rudolf Wtf? Do you really want to get rid of dynamically being able to set the FB size? Why? Don't you think that this is a feature that regular users of probably the only fully implemented coreboot motherboards might actually want to touch? Why is no time being spent on removing the other options that actually harm booting this device? Why does this feel like more pointless pedanticity? Luc Verhaegen. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] consolidate K8M890 VGA code
On Wed, Oct 28, 2009 at 05:00:11PM -0600, Myles Watson wrote: On Wed, Oct 28, 2009 at 4:44 PM, Myles Watson myle...@gmail.com wrote: fbbits = ((log2(uma_memory_size 20) - 2) 4); Why not use CONFIG_VIDEO_MB here? If it is going to be fixed at compile time, it seems like you can get rid of uma_memory_size. Either way: Acked-by: Myles Watson myle...@gmail.com Thanks, Myles NACK. WHY? Luc Verhaegen. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] LPC/FWH/Parallel buses on Intel ICH, VIA VT82*
Carl-Daniel Hailfinger wrote: For ICH I don't know if they ever supported LPC flash, It is safe to assume that they do not. FWH is a concept from Intel. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] grub as coreboot payload
On Mon, Oct 26, 2009 at 09:20:53PM +0100, Andreas B. Mundt wrote: Hi, first, congratulations to the 1.97-release! I vainly tried to run the latest grub2 (Revision: 2663) as payload to coreboot (Revision: 4852) following the wikipage: http://grub.enbug.org/CoreBoot Is this page still up to date and does anybody use grub2 as payload successfully? How? Hi, It appears that since r4534 (move to Kconfig), Multiboot information is no longer built in by default. You have to enable it in System tables / Generate Multiboot tables (for GRUB2), then GRUB works fine (at least on QEMU, which I just tested). Coreboot developers: would you consider enabling it again? The overhead is minimal, and it would make this less confusing for users. -- Robert Millan The DRM opt-in fallacy: Your data belongs to us. We will decide when (and how) you may access your data; but nobody's threatening your freedom: we still allow you to remove your data and not access it at all. Signed-off-by: Robert Millan rmh.g...@aybabtu.com Index: src/Kconfig === --- src/Kconfig (revision 4887) +++ src/Kconfig (working copy) @@ -319,7 +319,7 @@ config MULTIBOOT bool Generate Multiboot tables (for GRUB2) - default n + default y config GENERATE_ACPI_TABLES depends on HAVE_ACPI_TABLES -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [v2] r4886 - in trunk/coreboot-v2/util: . amdtools amdtools/example_input
Hi Carl-Daniel, On Wed, Oct 28, 2009 at 11:22:08PM +0100, Carl-Daniel Hailfinger wrote: was it intentional that you placed these tools below coreboot-v2/ in the tree? Hmm, not in so much other than that there are a whole bunch of subdirectories there, so I assumed that was the best place. What's our current thinking on that? I'd be happy to svn move them... Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] grub as coreboot payload
Like this? ron Leave it on by default, it's cheap. Signed-off-by: Ronald G. Minnich rminn...@gmail.com Index: src/Kconfig === --- src/Kconfig (revision 4887) +++ src/Kconfig (working copy) @@ -319,7 +319,7 @@ config MULTIBOOT bool Generate Multiboot tables (for GRUB2) - default n + default y config GENERATE_ACPI_TABLES depends on HAVE_ACPI_TABLES -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] grub as coreboot payload
On Wed, Oct 28, 2009 at 05:27:12PM -0700, ron minnich wrote: Like this? Looks fine to me, thanks. Acked-by: Robert Millan rmh.g...@aybabtu.com Leave it on by default, it's cheap. Signed-off-by: Ronald G. Minnich rminn...@gmail.com Index: src/Kconfig === --- src/Kconfig (revision 4887) +++ src/Kconfig (working copy) @@ -319,7 +319,7 @@ config MULTIBOOT bool Generate Multiboot tables (for GRUB2) - default n + default y config GENERATE_ACPI_TABLES depends on HAVE_ACPI_TABLES -- Robert Millan The DRM opt-in fallacy: Your data belongs to us. We will decide when (and how) you may access your data; but nobody's threatening your freedom: we still allow you to remove your data and not access it at all. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Intel i815 motherboard
I'd like to get coreboot working on my PC. I think the north bridge is currently unsupported but I would like to help. I have written bootloaders for a proprietary PowerPC based system. Here I might be out of my depth but I willing to give it a go. A concern is that my BIOS chip is soldered down, but the motherboard has a dip switch labelled recover, which I think reflashes from a 3.5in disk when enabled. So that could get me back to a working system. It's an HP Vectra VL400 mini-tower Phoenix BIOS IP.01.04US The HP motherboard P/N is D9820-6009. Socket 370 Pentium III era. Intel 815 north bridge. Intel 82801 - is that the south bridge? NSC87360 Super IO Flashrom reports Found chip Intel 82802AB (512 KB, FWH) at physical address 0xfff8 lspci output attached Chris lspci.d9820 Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
