Re: [coreboot] Tinyscheme ported to coreboot/libpayload
Dear Silvain, On 1/31/10 1:34 PM, Sylvain Ageneau wrote: Hello, I'd like to announce that tinyscheme http://tinyscheme.sourceforge.net/home.html can now run as a coreboot payload. TinyScheme is a lightweight Scheme interpreter that implements as large a subset of R5RS as was possible without getting very large and complicated. It is meant to be used as an embedded scripting interpreter for other programs. As such, it does not offer IDEs or extensive toolkits although it does sport a small top-level loop, included conditionally. A lot of functionality in TinyScheme is included conditionally, to allow developers freedom in balancing features and footprint. Programmatically, foreign functions in C can be added and values can be defined in the Scheme environment. Thank you very much for your efforts. The port was quite straightforward, most of the needed fonctionality needed was already in libpayload. It was probably possible to adapt tinyscheme to run on an unmodified libpayload but it didn't seem difficult to take the needed C functions from dietlibc (mostly stdio / math stuff) so I went that way instead (just needed to make some stubs for some low level functions like read/write). I don't know what your policy is with respect to integrating code from another GPL project but it looks like quite a bit of dietlibc could be easily integrated into libpayload. Some stuff uses syscalls and the like but other code doesn't require any fancy OS functionality. Please note that libpayload is _not_ released under the GPL, but under the BSD license (just like tinyscheme, btw), so it can not share code with GPL projects. Please also check http://www.coreboot.org/Development_Guidelines#How_to_contribute, especially the section on signing off patches. :-) Best regards, Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] It's not just v2 anymore
Am 30.01.2010 15:38, schrieb Stefan Reinauer: See patch :-) Acked-by: Patrick Georgi patrick.geo...@coresystems.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5070 - trunk/util/superiotool
Author: uwe
Date: Sun Jan 31 19:48:34 2010
New Revision: 5070
URL: http://tracker.coreboot.org/trac/coreboot/changeset/5070
Log:
Add detection support for the Winbond W83877AF (trivial).
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Uwe Hermann u...@hermann-uwe.de
Modified:
trunk/util/superiotool/winbond.c
Modified: trunk/util/superiotool/winbond.c
==
--- trunk/util/superiotool/winbond.cSat Jan 30 15:56:15 2010(r5069)
+++ trunk/util/superiotool/winbond.cSun Jan 31 19:48:34 2010(r5070)
@@ -464,9 +464,11 @@
/* ID[3..0] */
{0xa, W83877F, {
{EOT}}},
+ {0xb, W83877AF, {
+ {EOT}}},
{0xc, W83877TF, {
{EOT}}},
- {0xd, W83877ATF, {
+ {0xd, W83877ATF/ATG, {
{EOT}}},
{EOT}
};
@@ -556,7 +558,7 @@
else
id = (devid 4) | ((rev 0xf0) 4); /* ID and rev[7..4] */
- if (olddevid == 0x0a || olddevid == 0x0c || olddevid == 0x0d)
+ if (olddevid = 0x0a olddevid = 0x0d)
id = olddevid 0x0f;/* ID[3..0] */
if (superio_unknown(reg_table, id)) {
@@ -566,7 +568,7 @@
return;
}
- if (olddevid == 0x0a || olddevid == 0x0c || olddevid == 0x0d)
+ if (olddevid = 0x0a olddevid = 0x0d)
printf(Found Winbond %s (id=0x%02x) at 0x%x\n,
get_superio_name(reg_table, id), olddevid, port);
else
--
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[coreboot] [commit] r5071 - trunk/util/compareboard
Author: stepan Date: Sun Jan 31 21:51:00 2010 New Revision: 5071 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5071 Log: compareboard: - drop all occurences of LOGLEVEL settings. - drop CONFIG_CPU_[VIA|INTEL|AMD] because they're Kconfig only. - re-enable CONFIG_IOAPIC for now, it might need some fixing. Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Modified: trunk/util/compareboard/compareboard Modified: trunk/util/compareboard/compareboard == --- trunk/util/compareboard/compareboardSun Jan 31 19:48:34 2010 (r5070) +++ trunk/util/compareboard/compareboardSun Jan 31 21:51:00 2010 (r5071) @@ -84,10 +84,10 @@ sed \ -e /^CONFIG_VENDOR_/ d \ -e /^CONFIG_ARCH_POWERPC / d \ - -e /^CONFIG_[MAXIMUMDEFAULT]*_CONSOLE_LOGLEVEL_/ d \ + -e /^CONFIG_MAXIMUM_CONSOLE_LOGLEVEL/ d \ + -e /^CONFIG_DEFAULT_CONSOLE_LOGLEVEL/ d \ -e /^CONFIG_COREBOOT_ROMSIZE_/ d \ -e /^CONFIG_BOARD_/ d \ - -e /^CONFIG_IOAPIC / d \ -e /^CONFIG_HAVE_MOVNTI / d \ -e /^CONFIG_[NORTHSOUTH]*BRIDGE_/ d \ -e /^CONFIG_SUPERIO_/ d \ @@ -100,6 +100,9 @@ -e /^CONFIG_COMPRESSED_PAYLOAD_LZMA / d \ -e /^CONFIG_CPU_[A-Z]*_MODEL_/ d \ -e /^CONFIG_CPU_[A-Z]*_SOCKET_/ d \ + -e /^CONFIG_CPU_AMD_/ d \ + -e /^CONFIG_CPU_INTEL_/ d \ + -e /^CONFIG_CPU_VIA_/ d \ -e /^CONFIG_ROMBASE / d \ -e /^CONFIG_ROM_IMAGE_SIZE / d \ -e /^CONFIG_STACK_SIZE / d \ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5072 - trunk/src/devices
Author: stepan Date: Sun Jan 31 22:46:12 2010 New Revision: 5072 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5072 Log: - Improve help texts for option ROM initialization methods - disallow REAL_MODE method if ARCH_X86 is not set. Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Modified: trunk/src/devices/Kconfig Modified: trunk/src/devices/Kconfig == --- trunk/src/devices/Kconfig Sun Jan 31 21:51:00 2010(r5071) +++ trunk/src/devices/Kconfig Sun Jan 31 22:46:12 2010(r5072) @@ -42,32 +42,50 @@ Examples include IDE/SATA controller option ROMs and option ROMs for network cards (NICs). -# TODO: Describe YABEL vs. x86emu differences in more detail. choice prompt Option ROM execution type - default PCI_OPTION_ROM_RUN_REALMODE + default PCI_OPTION_ROM_RUN_YABEL if !ARCH_X86 + default PCI_OPTION_ROM_RUN_REALMODE if ARCH_X86 depends on PCI_ROM_RUN || VGA_ROM_RUN config PCI_OPTION_ROM_RUN_REALMODE prompt Real mode bool + depends on ARCH_X86 help If you select this option, PCI option ROMs will be executed - natively on the hardware (a 32bit x86 system is required). + natively on the CPU in real mode. No CPU emulation is involved, + so this is the fastest, but also the least secure option. + (only works on x86/x64 systems) -config PCI_OPTION_ROM_RUN_YABEL - prompt YABEL +config PCI_OPTION_ROM_RUN_X86EMU + prompt x86emu bool help - If you select this option, the YABEL BIOS emulator will be used to - execute PCI option ROMs. + If you select this option, the x86emu CPU emulator will be used to + execute PCI option ROMs. + When choosing this option, x86emu will pass through all hardware + accesses to memory and IO devices to the underlying memory and IO + addresses. While this option prevents option ROMs from doing dirty + tricks with the CPU (such as installing SMM modules or hypervisors), + they can still access all devices in the system. + Choosing x86emu, option ROM execution is slower than native execution + in real mode, but faster than the full system emulation YABEL + This is the default choice for non-x86 systems. -config PCI_OPTION_ROM_RUN_X86EMU - prompt x86emu +config PCI_OPTION_ROM_RUN_YABEL + prompt YABEL bool help - If you select this option, the x86emu BIOS emulator will be used to + If you select this option, the YABEL system emulator will be used to execute PCI option ROMs. + YABEL consists of two parts: It uses x86emu for the CPU emulation and + additionally provides a PC system emulation that filters bad device and + memory access (such as PCI config space access to other devices than the + initialized one). + This option best prevents option ROMs from doing dirty tricks with the + system (such as installing SMM modules or hypervisors), but it is also + significantly slower than the other option ROM initialization methods. endchoice -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Re : Tinyscheme ported to coreboot/libpayload
Hello Stefan, Ok, I get your point about the impossibility to merge some of dietlibc into libpayload. But for purpose of using tinyscheme as a scripting language on top of coreboot, would the fact the interpreter's executable is linked against GPL code also make any scheme script using it necessarily GPL ? In the patches I sent you, the dietlibc part is kept separate from libpayload. In any case, I'll see if I can remove the dietlibc dependency, I had actually started to implement some of the missing functions before I found out about dietlibc. Regards, Sylvain De : Stefan Reinauer ste...@coresystems.de À : coreboot@coreboot.org; sylvain_agen...@yahoo.fr Envoyé le : Dim 31 Janvier 2010, 11 h 12 min 27 s Objet : Re: [coreboot] Tinyscheme ported to coreboot/libpayload Dear Silvain, On 1/31/10 1:34 PM, Sylvain Ageneau wrote: Hello, I'd like to announce that tinyscheme can now run as a coreboot payload. TinyScheme is a lightweight Scheme interpreter that implements as large a subset of R5RS as was possible without getting very large and complicated. It is meant to be used as an embedded scripting interpreter for other programs. As such, it does not offer IDEs or extensive toolkits although it does sport a small top-level loop, included conditionally. A lot of functionality in TinyScheme is included conditionally, to allow developers freedom in balancing features and footprint. Programmatically, foreign functions in C can be added and values can be defined in the Scheme environment. Thank you very much for your efforts. The port was quite straightforward, most of the needed fonctionality needed was already in libpayload. It was probably possible to adapt tinyscheme to run on an unmodified libpayload but it didn't seem difficult to take the needed C functions from dietlibc (mostly stdio / math stuff) so I went that way instead (just needed to make some stubs for some low level functions like read/write). I don't know what your policy is with respect to integrating code from another GPL project but it looks like quite a bit of dietlibc could be easily integrated into libpayload. Some stuff uses syscalls and the like but other code doesn't require any fancy OS functionality. Please note that libpayload is _not_ released under the GPL, but under the BSD license (just like tinyscheme, btw), so it can not share code with GPL projects. Please also check http://www.coreboot.org/Development_Guidelines#How_to_contribute, especially the section on signing off patches. :-) Best regards, Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Re : Tinyscheme ported to coreboot/libpayload
Sylvain Ageneau wrote: But for purpose of using tinyscheme as a scripting language on top of coreboot, would the fact the interpreter's executable is linked against GPL code also make any scheme script using it necessarily GPL ? What GPL code do you mean? In any case, if you create a GPL payload out of libpayload+dietlibc+tinyscheme then that is an interpreter, and any code you execute using that interpreter can have a different license since they are not, in fact, linked together. In the patches I sent you, the dietlibc part is kept separate from libpayload. In any case, I'll see if I can remove the dietlibc dependency, I had actually started to implement some of the missing functions before I found out about dietlibc. That would be great. libpayload has already reused code from other BSD-licensed projects, in particular HelenOS IIRC, so possibly you can find another source of some of the code at least. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Request for Help/Information - Booting Linux Kernel (Embedded x86)
Graeme Russ wrote: A quick update - I think I'm getting even closer. Did you get some traction on the mkelfImage path too? U-Boot had some primitive BIOS Interrupt Service Routines and a Real Mode bootstrap .. So far I have seen instances of IRQ15, IRQ16 and IRQ10 Sounds like the kernel is running then. Digging deeper... arch/x86/boot/header.S calls arch/x86/boot/main.c //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] dell server BIOS setting insanity
Hi all, I thought I'd point out this little gem from the linux-poweredge list http://lists.us.dell.com/pipermail/linux-poweredge/2010-January/041170.html Apparently several lines of Dell servers have a BIOS setting called Cores-per-processor. It seems they ship these machines with the setting configured to 'dual', regardless of what CPUs are in the system. The poor guy who reported this to the list just took delivery of 300 of those machines - with quad core CPUs. They show up as dual core until he goes into the BIOS and changes the setting. That's also the 'official' solution for the problem from the Dell rep. Seriously. Thanks, Ward. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] dell server BIOS setting insanity
Ward Vandewege wrote: 300 of those machines - with quad core CPUs. They show up as dual core until he goes into the BIOS and changes the setting. That's also the 'official' solution for the problem from the Dell rep. Ask him to come to IRC. If really lucky it will be faster to create a program for it. But my guess is that it will be quicker to walk around and change the setting. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] dell server BIOS setting insanity
Do you know if it is in CMOS or FLASH? I could not tell. If in CMOS it's trivial to script and they're going to want that script, because in the typical factory BIOS these settings have a way of reverting to default, which is why we once had 4600 nodes come up and want a keyboard to be attached; they forgot that we'd told them there were no keyboards. ... and those are hardly the only nodes we've seen the problem on over the last 10 years. ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] dell server BIOS setting insanity
On 01.02.2010 04:44, Ward Vandewege wrote: I thought I'd point out this little gem from the linux-poweredge list http://lists.us.dell.com/pipermail/linux-poweredge/2010-January/041170.html Apparently several lines of Dell servers have a BIOS setting called Cores-per-processor. It seems they ship these machines with the setting configured to 'dual', regardless of what CPUs are in the system. The poor guy who reported this to the list just took delivery of 300 of those machines - with quad core CPUs. They show up as dual core until he goes into the BIOS and changes the setting. That's also the 'official' solution for the problem from the Dell rep. Seriously. You must be kidding. I mean, if Dell declare this to be a feature, they could go all the way to set the CPUs to single-core. Poor users. I envision a new option in Dell order forms: Apply correct BIOS settings. $25 Anyway, could you ask the guy to dump with nvramtool before and after the settings change? Maybe the settings live in NVRAM. That would make it scriptable. Regards, Carl-Daniel -- Developer quote of the year: We are juggling too many chainsaws and flaming arrows and tigers. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] Intel 82830 overhaul
Hello, Attached is major overhaul to the 82830 raminit. Alot of it is trivial clean ups. With on major change. The i830 is now able to initialize one row (side) of memory at a time (this is the way it is supposed to be done). See bootlog snip below (shows 512MB double sided SO-DIMM in socket 1 and 64MB single sided onboard memory) and attached patch. Signed-off-by: Joseph Smith j...@settoplinux.org coreboot-2.3 Sun Jan 31 23:42:28 EST 2010 starting... SMBus controller enabled Setting initial sdram registers Found DIMM in slot 00 DIMM is 0x0100 on side 1 DIMM is 0x0100 on side 2 DRB 0x60 has been set to 0x08 DRB1 0x61 has been set to 0x10 Found DIMM in slot 01 DIMM is 0x0040 on side 1 DIMM is 0x on side 2 DRB2 0x62 has been set to 0x12 DRB3 0x63 has been set to 0x12 Found DIMM in slot 00, setting DRA... DRA 0x70 has been set to 0x22 Found DIMM in slot 01, setting DRA... DRA 0x71 has been set to 0xf1 Initial sdram registers have been set. Initializing SDRAM Row 00 NOP RAM command 0x0010 Sending RAM command to 0x Pre-charging all banks RAM command 0x0020 Sending RAM command to 0x 8 CBR refreshes RAM command 0x0060 Sending RAM command to 0x RAM command 0x0060 Sending RAM command to 0x RAM command 0x0060 Sending RAM command to 0x RAM command 0x0060 Sending RAM command to 0x RAM command 0x0060 Sending RAM command to 0x RAM command 0x0060 Sending RAM command to 0x RAM command 0x0060 Sending RAM command to 0x RAM command 0x0060 Sending RAM command to 0x MRS RAM command 0x0030 Sending RAM command to 0x01d0 Normal operation mode RAM command 0x0070 Sending RAM command to 0x Performing dummy read/write Reading RAM at 0x = 0x3e5e556c Writing RAM at 0x = 0x55aa55aa Reading RAM at 0x = 0x55aa55aa Initializing SDRAM Row 01 NOP RAM command 0x0010 Sending RAM command to 0x1000 Pre-charging all banks RAM command 0x0020 Sending RAM command to 0x1000 8 CBR refreshes RAM command 0x0060 Sending RAM command to 0x1000 RAM command 0x0060 Sending RAM command to 0x1000 RAM command 0x0060 Sending RAM command to 0x1000 RAM command 0x0060 Sending RAM command to 0x1000 RAM command 0x0060 Sending RAM command to 0x1000 RAM command 0x0060 Sending RAM command to 0x1000 RAM command 0x0060 Sending RAM command to 0x1000 RAM command 0x0060 Sending RAM command to 0x1000 MRS RAM command 0x0030 Sending RAM command to 0x11d0 Normal operation mode RAM command 0x0070 Sending RAM command to 0x1000 Performing dummy read/write Reading RAM at 0x1000 = 0x55abf7aa Writing RAM at 0x1000 = 0x55aa55aa Reading RAM at 0x1000 = 0x55aa55aa Initializing SDRAM Row 02 NOP RAM command 0x0010 Sending RAM command to 0x2000 Pre-charging all banks RAM command 0x0020 Sending RAM command to 0x2000 8 CBR refreshes RAM command 0x0060 Sending RAM command to 0x2000 RAM command 0x0060 Sending RAM command to 0x2000 RAM command 0x0060 Sending RAM command to 0x2000 RAM command 0x0060 Sending RAM command to 0x2000 RAM command 0x0060 Sending RAM command to 0x2000 RAM command 0x0060 Sending RAM command to 0x2000 RAM command 0x0060 Sending RAM command to 0x2000 RAM command 0x0060 Sending RAM command to 0x2000 MRS RAM command 0x0030 Sending RAM command to 0x21d0 Normal operation mode RAM command 0x0070 Sending RAM command to 0x2000 Performing dummy read/write Reading RAM at 0x2000 = 0x55ba55aa Writing RAM at 0x2000 = 0x55aa55aa Reading RAM at 0x2000 = 0x55aa55aa Enabling Refresh Setting initialization complete Setting initial nothbridge registers Initial northbridge registers have been set. Northbridge following SDRAM init: PCI: 00:00.00 00: 86 80 75 35 06 00 10 00 04 00 00 06 00 00 00 00 10: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 40 00 00 00 00 00 00 00 00 00 00 00 40: 09 00 05 01 00 00 00 00 00 00 00 00 02 28 00 0e 50: 72 a0 40 00 00 00 00 00 00 30 33 33 33 33 33 33 60: 08 10 12 12 12 12 00 00 00 00 00 00 00 00 00 00 70: 22 f1 ff ff 00 00 00 00 10 00 00 00 70 01 00 20 80: 00 00 00 00 00 00 00 00 80 60 33 01 00 00 00 00 90: 02 38 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 02 00 20 00 17 02 00 1f 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 54 0e 41 a2 99 01 00 c0 00 00 00 00 00 00 00 d0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 1b 49 9b fc f0: 11 11 01 00 00 00 0b 05 35 d0 2c cf 1f cd 1d cc Copying coreboot to RAM. Loading stage image. Check CBFS header at fffeffe0 magic is 4f524243 Found CBFS header at fffeffe0 Check
