[coreboot] [PATCH] (resend to mailing list) COM2 on Geode
See patch. fixup patch from ticket #152 for coreboot trunk (http://tracker.coreboot.org/trac/coreboot/ticket/152) Signed-off-by: Stefan Reinauer ste...@coresystems.de Index: src/southbridge/amd/cs5536/cs5536_early_setup.c === --- src/southbridge/amd/cs5536/cs5536_early_setup.c (revision 4967) +++ src/southbridge/amd/cs5536/cs5536_early_setup.c (working copy) @@ -172,6 +172,7 @@ outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); /* Set: OUTAUX1 Select (0x10) */ outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); + /* GPIO9 - UART1_RX */ /* Set: Input Enable (0x20) */ outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); Index: src/southbridge/amd/cs5536/cs5536.c === --- src/southbridge/amd/cs5536/cs5536.c (revision 4967) +++ src/southbridge/amd/cs5536/cs5536.c (working copy) @@ -298,7 +298,7 @@ /* Set: OUTAUX1 Select (0x10) */ outl(GPIOL_8_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); - /* GPIO8 - UART1_RX */ + /* GPIO9 - UART1_RX */ /* Set: Input Enable (0x20) */ outl(GPIOL_9_SET, gpio_addr + GPIOL_INPUT_ENABLE); /* Set: INAUX1 Select (0x34) */ @@ -356,18 +356,18 @@ msr.lo |= sb-com2_irq 28; wrmsr(MDD_IRQM_YHIGH, msr); - /* GPIO4 - UART2_RX */ + /* GPIO3 - UART2_RX */ + /* Set: Input Enable (0x20) */ + outl(GPIOL_3_SET, gpio_addr + GPIOL_INPUT_ENABLE); + /* Set: INAUX1 Select (0x34) */ + outl(GPIOL_3_SET, gpio_addr + GPIOL_IN_AUX1_SELECT); + + /* GPIO4 - UART2_TX */ /* Set: Output Enable (0x4) */ outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); /* Set: OUTAUX1 Select (0x10) */ outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); - /* GPIO3 - UART2_TX */ - /* Set: Input Enable (0x20) */ - outl(GPIOL_3_SET, gpio_addr + GPIOL_INPUT_ENABLE); - /* Set: INAUX1 Select (0x34) */ - outl(GPIOL_3_SET, gpio_addr + GPIOL_IN_AUX1_SELECT); - /* Set: GPIO 3 and 4 Pull Up (0x18) */ outl(GPIOL_3_SET | GPIOL_4_SET, gpio_addr + GPIOL_PULLUP_ENABLE); -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] (resend to mailing list) COM2 on Geode
Tested on Norwich-type board as working. Acked-by: Edwin Beasant edwin_beas...@virtensys.com From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On Behalf Of Stefan Reinauer Sent: 03 February 2010 13:20 To: coreboot Subject: [coreboot] [PATCH] (resend to mailing list) COM2 on Geode See patch. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5074 - trunk/src/southbridge/amd/cs5536
Author: oxygene Date: Wed Feb 3 14:49:24 2010 New Revision: 5074 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5074 Log: The UART2 on the AMD cs5536 is incorrectly configured in two places. GPIO lines 4 and 3 are swapped and also incorrectly put in IR mode receive (compound fault). Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Edwin Beasant edwin_beas...@virtensys.com Modified: trunk/src/southbridge/amd/cs5536/cs5536.c trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Modified: trunk/src/southbridge/amd/cs5536/cs5536.c == --- trunk/src/southbridge/amd/cs5536/cs5536.c Mon Feb 1 23:51:18 2010 (r5073) +++ trunk/src/southbridge/amd/cs5536/cs5536.c Wed Feb 3 14:49:24 2010 (r5074) @@ -298,7 +298,7 @@ /* Set: OUTAUX1 Select (0x10) */ outl(GPIOL_8_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); - /* GPIO8 - UART1_RX */ + /* GPIO9 - UART1_RX */ /* Set: Input Enable (0x20) */ outl(GPIOL_9_SET, gpio_addr + GPIOL_INPUT_ENABLE); /* Set: INAUX1 Select (0x34) */ @@ -356,18 +356,18 @@ msr.lo |= sb-com2_irq 28; wrmsr(MDD_IRQM_YHIGH, msr); - /* GPIO4 - UART2_RX */ - /* Set: Output Enable (0x4) */ - outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); - /* Set: OUTAUX1 Select (0x10) */ - outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); - - /* GPIO3 - UART2_TX */ + /* GPIO3 - UART2_RX */ /* Set: Input Enable (0x20) */ outl(GPIOL_3_SET, gpio_addr + GPIOL_INPUT_ENABLE); /* Set: INAUX1 Select (0x34) */ outl(GPIOL_3_SET, gpio_addr + GPIOL_IN_AUX1_SELECT); + /* GPIO4 - UART2_TX */ + /* Set: Output Enable (0x4) */ + outl(GPIOL_4_SET, gpio_addr + GPIOL_OUTPUT_ENABLE); + /* Set: OUTAUX1 Select (0x10) */ + outl(GPIOL_4_SET, gpio_addr + GPIOL_OUT_AUX1_SELECT); + /* Set: GPIO 3 and 4 Pull Up (0x18) */ outl(GPIOL_3_SET | GPIOL_4_SET, gpio_addr + GPIOL_PULLUP_ENABLE); Modified: trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c == --- trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Mon Feb 1 23:51:18 2010(r5073) +++ trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c Wed Feb 3 14:49:24 2010(r5074) @@ -172,6 +172,7 @@ outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUTPUT_ENABLE); /* Set: OUTAUX1 Select (0x10) */ outl(GPIOL_8_SET, GPIO_IO_BASE + GPIOL_OUT_AUX1_SELECT); + /* GPIO9 - UART1_RX */ /* Set: Input Enable (0x20) */ outl(GPIOL_9_SET, GPIO_IO_BASE + GPIOL_INPUT_ENABLE); -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] #152: v3 Geode cs5536 UART2 wrongly configured
#152: v3 Geode cs5536 UART2 wrongly configured +--- Reporter: edwin_beas...@… | Owner: carldani Type: defect |Status: new Priority: major| Milestone: Going mainstream Component: coreboot | Keywords: serial com2 geode cs5536 Dependencies: | Patchstatus: patch is ready to be committed +--- Changes (by oxygene): * patchstatus: patch needs review = patch is ready to be committed Comment: Patch for v2 committed in r5074 -- Ticket URL: http://tracker.coreboot.org/trac/coreboot/ticket/152#comment:2 coreboot http://www.coreboot.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Patch Supermicro H8QME
Am 03.02.2010 14:53, schrieb Knut Kujat: Hi, hope thats how it works for adding a patch to the list so if something is wrong let me know. The procedure is fine. I copied a newer version of h8dmr_fam10's Makefile.inc to the h8qme_fam10 tree, otherwise it's fine. Acked-by: Patrick Georgi patrick.geo...@coresystems.de and committed as r5075 May I assume that crossgcc fixed your build issues? Patrick -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Patch Supermicro H8QME
Patrick Georgi escribió: Am 03.02.2010 14:53, schrieb Knut Kujat: Hi, hope thats how it works for adding a patch to the list so if something is wrong let me know. The procedure is fine. I copied a newer version of h8dmr_fam10's Makefile.inc to the h8qme_fam10 tree, otherwise it's fine. Acked-by: Patrick Georgi patrick.geo...@coresystems.de and committed as r5075 May I assume that crossgcc fixed your build issues? Yes! Patrick -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Motherboard HannStar - acer aspire 5720
Hi, Will coreboot work on a mobo HannStar J MV-4 94V-O ? It's about a laptop Acer aspire 5720 with Intel Core 2 Duo processor T5250 (1.5 GHz, 667 MHz FSB, 2 MB L2 cache). Below the output of 'lspci -tvnn' : -[:00]-+-00.0 Intel Corporation Mobile PM965/GM965/GL960 Memory Controller Hub [8086:2a00] +-02.0 Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller [8086:2a02] +-02.1 Intel Corporation Mobile GM965/GL960 Integrated Graphics Controller [8086:2a03] +-1a.0 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #4 [8086:2834] +-1a.1 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #5 [8086:2835] +-1a.7 Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #2 [8086:283a] +-1b.0 Intel Corporation 82801H (ICH8 Family) HD Audio Controller [8086:284b] +-1c.0-[:02]-- +-1c.1-[:04]-- +-1c.2-[:05]00.0 Broadcom Corporation NetLink BCM5787M Gigabit Ethernet PCI Express [14e4:1693] +-1c.3-[:06]00.0 Intel Corporation PRO/Wireless 3945ABG [Golan] Network Connection [8086:4222] +-1d.0 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #1 [8086:2830] +-1d.1 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #2 [8086:2831] +-1d.2 Intel Corporation 82801H (ICH8 Family) USB UHCI Controller #3 [8086:2832] +-1d.7 Intel Corporation 82801H (ICH8 Family) USB2 EHCI Controller #1 [8086:2836] +-1e.0-[:07]--+-00.0 Ricoh Co Ltd R5C832 IEEE 1394 Controller [1180:0832] | +-00.1 Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host Adapter [1180:0822] | +-00.2 Ricoh Co Ltd R5C843 MMC Host Controller [1180:0843] | +-00.3 Ricoh Co Ltd R5C592 Memory Stick Bus Host Adapter [1180:0592] | \-00.4 Ricoh Co Ltd xD-Picture Card Controller [1180:0852] +-1f.0 Intel Corporation 82801HEM (ICH8M) LPC Interface Controller [8086:2815] +-1f.1 Intel Corporation 82801HBM/HEM (ICH8M/ICH8M-E) IDE Controller [8086:2850] +-1f.2 Intel Corporation 82801HBM/HEM (ICH8M/ICH8M-E) SATA AHCI Controller [8086:2829] \-1f.3 Intel Corporation 82801H (ICH8 Family) SMBus Controller [8086:283e] Below the output of 'superiotool -dV' : superiotool r3125 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0x, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0x, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x, id=0x Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x01,0x55,0x55/0xaa) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x86,0x86) at 0x2e... Failed. Returned data:
[coreboot] [commit] r5076 - in trunk/src/mainboard/tyan: s2880 s2882 s2885
Author: uwe Date: Wed Feb 3 18:25:34 2010 New Revision: 5076 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5076 Log: Fix incorrect board names in Kconfig strings (trivial). Signed-off-by: Uwe Hermann u...@hermann-uwe.de Acked-by: Uwe Hermann u...@hermann-uwe.de Modified: trunk/src/mainboard/tyan/s2880/Kconfig trunk/src/mainboard/tyan/s2882/Kconfig trunk/src/mainboard/tyan/s2885/Kconfig Modified: trunk/src/mainboard/tyan/s2880/Kconfig == --- trunk/src/mainboard/tyan/s2880/Kconfig Wed Feb 3 17:04:40 2010 (r5075) +++ trunk/src/mainboard/tyan/s2880/Kconfig Wed Feb 3 18:25:34 2010 (r5076) @@ -1,5 +1,5 @@ config BOARD_TYAN_S2880 - bool S2880 (Thunder K8SR) + bool S2880 (Thunder K8S) select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 Modified: trunk/src/mainboard/tyan/s2882/Kconfig == --- trunk/src/mainboard/tyan/s2882/Kconfig Wed Feb 3 17:04:40 2010 (r5075) +++ trunk/src/mainboard/tyan/s2882/Kconfig Wed Feb 3 18:25:34 2010 (r5076) @@ -1,5 +1,5 @@ config BOARD_TYAN_S2882 - bool S2882 (Thunder K8SR) + bool S2882 (Thunder K8S Pro) select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 Modified: trunk/src/mainboard/tyan/s2885/Kconfig == --- trunk/src/mainboard/tyan/s2885/Kconfig Wed Feb 3 17:04:40 2010 (r5075) +++ trunk/src/mainboard/tyan/s2885/Kconfig Wed Feb 3 18:25:34 2010 (r5076) @@ -1,5 +1,5 @@ config BOARD_TYAN_S2885 - bool S2885 (Thunder K8SR) + bool S2885 (Thunder K8W) select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] fix Tyan s2881 boot (Kconfig)
This fixes breakage introduced in r5051. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator Revision 5051 broke Kconfig booting for the Tyan s2881 board. Up to 5050, there were two SB_HT_CHAIN_ON_BUS0 sections in the mainboard Kconfig file - one setting the parameter to 0, the other setting it to 2. Revision 5051 removed one of the two SB_HT_CHAIN_ON_BUS0 sections - the wrong one. This patch fixes that. Tested on real hardware. Signed-off-by: Ward Vandewege w...@gnu.org Index: src/mainboard/tyan/s2881/Kconfig === --- src/mainboard/tyan/s2881/Kconfig (revision 5076) +++ src/mainboard/tyan/s2881/Kconfig (working copy) @@ -24,7 +24,7 @@ config SB_HT_CHAIN_ON_BUS0 int - default 0 + default 2 depends on BOARD_TYAN_S2881 config LB_CKS_RANGE_END -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] fix Tyan s2881 boot (Kconfig)
On 2/3/10 6:50 PM, Ward Vandewege wrote: This fixes breakage introduced in r5051. Thanks, Ward. Sorry for the inconvenience. Acked-by: Stefan Reinauer ste...@coresystems.de -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5077 - in trunk: src/arch/i386 util/cbfstool
Author: oxygene
Date: Wed Feb 3 18:56:37 2010
New Revision: 5077
URL: http://tracker.coreboot.org/trac/coreboot/changeset/5077
Log:
Guards against errors that are hard to track down:
- if crt0s is empty (eg. because crt0-y is still used),
break the build, and say where that behaviour changed
- if a stage is unusable for cbfstool because it's placed
outside the ROM space (linked to 0 is somewhat notorious),
warn about it, give some hints and exit instead of crashing.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Stefan Reinauer stefan.reina...@coresystems.de
Modified:
trunk/src/arch/i386/Makefile.inc
trunk/util/cbfstool/cbfs-mkstage.c
Modified: trunk/src/arch/i386/Makefile.inc
==
--- trunk/src/arch/i386/Makefile.incWed Feb 3 18:25:34 2010(r5076)
+++ trunk/src/arch/i386/Makefile.incWed Feb 3 18:56:37 2010(r5077)
@@ -62,6 +62,10 @@
###
# done
+# crt0s should be set by now
+ifeq ($(crt0s),)
+$(error crt0s are empty. If your board still uses crt0-y and ldscript-y: It
shouldn't, we moved away from that in r5065)
+endif
endif
ifeq ($(CONFIG_TINY_BOOTBLOCK),y)
Modified: trunk/util/cbfstool/cbfs-mkstage.c
==
--- trunk/util/cbfstool/cbfs-mkstage.c Wed Feb 3 18:25:34 2010(r5076)
+++ trunk/util/cbfstool/cbfs-mkstage.c Wed Feb 3 18:56:37 2010(r5077)
@@ -126,6 +126,11 @@
data_start = *location;
}
+ if (data_end = data_start) {
+ fprintf(stderr, E: data ends before it starts. Make sure the
ELF file is correct and resides in ROM space.\n);
+ exit(1);
+ }
+
/* allocate an intermediate buffer for the data */
buffer = calloc(data_end - data_start, 1);
--
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http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5078 - trunk/targets/emulation/qemu-x86
Author: oxygene Date: Wed Feb 3 18:57:55 2010 New Revision: 5078 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5078 Log: Trivial: In QEmu, the fallback image should USE_FALLBACK_IMAGE. (fixed buildtarget) Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Patrick Georgi patrick.geo...@coresystems.de Modified: trunk/targets/emulation/qemu-x86/Config.lb Modified: trunk/targets/emulation/qemu-x86/Config.lb == --- trunk/targets/emulation/qemu-x86/Config.lb Wed Feb 3 18:56:37 2010 (r5077) +++ trunk/targets/emulation/qemu-x86/Config.lb Wed Feb 3 18:57:55 2010 (r5078) @@ -13,6 +13,7 @@ option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 romimage fallback + option USE_FALLBACK_IMAGE=1 option COREBOOT_EXTRA_VERSION=-GRUB2 # payload /home/stepan/core.img payload ../payload.elf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] fix Tyan s2881 boot (Kconfig)
Am 03.02.2010 18:50, schrieb Ward Vandewege: This fixes breakage introduced in r5051. Sorry for that. I assumed newconfig would be fine: (Options.lb) #make the SB HT chain on bus 0, default is not (0) default CONFIG_SB_HT_CHAIN_ON_BUS0=0 If you want to change that in newconfig, too, consider both your patch and that change to be Acked-by: Patrick Georgi patrick.geo...@coresystems.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5079 - trunk/targets/emulation/qemu-x86
Author: uwe Date: Wed Feb 3 21:52:14 2010 New Revision: 5079 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5079 Log: Add missing CONFIG_ prefix to make manual QEMU build work (trivial). Signed-off-by: Uwe Hermann u...@hermann-uwe.de Acked-by: Uwe Hermann u...@hermann-uwe.de Modified: trunk/targets/emulation/qemu-x86/Config.lb Modified: trunk/targets/emulation/qemu-x86/Config.lb == --- trunk/targets/emulation/qemu-x86/Config.lb Wed Feb 3 18:57:55 2010 (r5078) +++ trunk/targets/emulation/qemu-x86/Config.lb Wed Feb 3 21:52:14 2010 (r5079) @@ -13,7 +13,7 @@ option CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9 romimage fallback - option USE_FALLBACK_IMAGE=1 + option CONFIG_USE_FALLBACK_IMAGE=1 option COREBOOT_EXTRA_VERSION=-GRUB2 # payload /home/stepan/core.img payload ../payload.elf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5080 - trunk/src/mainboard/supermicro/h8qme_fam10
Author: uwe Date: Wed Feb 3 23:07:57 2010 New Revision: 5080 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5080 Log: Supermicro H8QME-2+ (Fam10) whitespace fixes (trivial). This makes the code more similar to the h8dmr_fam10 target in order to make the diff between both smaller and more readable. Build-tested with newconfig and kconfig. Signed-off-by: Uwe Hermann u...@hermann-uwe.de Acked-by: Uwe Hermann u...@hermann-uwe.de Modified: trunk/src/mainboard/supermicro/h8qme_fam10/Config.lb trunk/src/mainboard/supermicro/h8qme_fam10/Options.lb trunk/src/mainboard/supermicro/h8qme_fam10/apc_auto.c trunk/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c trunk/src/mainboard/supermicro/h8qme_fam10/mainboard.c trunk/src/mainboard/supermicro/h8qme_fam10/mb_sysconf.h trunk/src/mainboard/supermicro/h8qme_fam10/mptable.c trunk/src/mainboard/supermicro/h8qme_fam10/spd_addr.h Modified: trunk/src/mainboard/supermicro/h8qme_fam10/Config.lb == --- trunk/src/mainboard/supermicro/h8qme_fam10/Config.lbWed Feb 3 21:52:14 2010(r5079) +++ trunk/src/mainboard/supermicro/h8qme_fam10/Config.lbWed Feb 3 23:07:57 2010(r5080) @@ -288,12 +288,12 @@ device pci 5.0 on end # SATA 0 device pci 5.1 on end # SATA 1 device pci 5.2 on end # SATA 2 - device pci 6.1 off end # AZA - device pci 7.0 on - device pci 1.0 on end - end - device pci 8.0 off end - device pci 9.0 off end + device pci 6.1 off end # AZA + device pci 7.0 on + device pci 1.0 on end + end + device pci 8.0 off end + device pci 9.0 off end device pci a.0 on end # PCI E 5 device pci b.0 on end # PCI E 4 device pci c.0 on end # PCI E 3 @@ -312,20 +312,18 @@ device pci 18.3 on end device pci 18.4 on end device pci 19.0 on end - device pci 19.0 on end - device pci 19.0 on - chip southbridge/amd/amd8132 - device pci 0.0 on end - device pci 0.1 on end - device pci 1.0 on - device pci 3.0 on end - device pci 3.1 on end - end - device pci 1.1 on end - - end #amd8132 - - end #device pci 19.0 + device pci 19.0 on end + device pci 19.0 on + chip southbridge/amd/amd8132 + device pci 0.0 on end + device pci 0.1 on end + device pci 1.0 on + device pci 3.0 on end + device pci 3.1 on end + end + device pci 1.1 on end + end #amd8132 + end #device pci 19.0 device pci 19.1 on end device pci 19.2 on end device pci 19.3 on end Modified: trunk/src/mainboard/supermicro/h8qme_fam10/Options.lb == --- trunk/src/mainboard/supermicro/h8qme_fam10/Options.lb Wed Feb 3 21:52:14 2010(r5079) +++ trunk/src/mainboard/supermicro/h8qme_fam10/Options.lb Wed Feb 3 23:07:57 2010(r5080) @@ -141,6
[coreboot] [commit] r5081 - trunk/util/superiotool
Author: uwe
Date: Thu Feb 4 01:55:06 2010
New Revision: 5081
URL: http://tracker.coreboot.org/trac/coreboot/changeset/5081
Log:
Add dump support for the Winbond W83877AF (trivial).
This Super I/O doesn't seem to know the concept of LDNs, it's just a
bunch of registers not splitted into banks/LDNs.
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Uwe Hermann u...@hermann-uwe.de
Modified:
trunk/util/superiotool/winbond.c
Modified: trunk/util/superiotool/winbond.c
==
--- trunk/util/superiotool/winbond.cWed Feb 3 23:07:57 2010(r5080)
+++ trunk/util/superiotool/winbond.cThu Feb 4 01:55:06 2010(r5081)
@@ -465,6 +465,15 @@
{0xa, W83877F, {
{EOT}}},
{0xb, W83877AF, {
+ {NOLDN, NULL,
+ {0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,
+0x0a,0x0b,0x0c,0x0d,0x0e,0x0f,0x10,0x11,0x12,0x13,
+0x14,0x15,0x16,0x17,0x1e,0x20,0x21,0x22,0x23,0x24,
+0x25,0x26,0x27,0x28,0x29,0x2a,0x2b,0x2c,0x2d,EOT},
+ {0x00,0x00,0x00,0x30,0x00,0x00,0x00,0x00,0x00,0x0a,
+0x1f,0x0c,0x28,0xa3,RSVD,RSVD,0x00,0x00,0x00,0x00,
+0x00,0x00,0x0e,0x00,MISC,MISC,MISC,MISC,MISC,MISC,
+MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,MISC,EOT}},
{EOT}}},
{0xc, W83877TF, {
{EOT}}},
--
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[coreboot] [commit] r5082 - in trunk: src/cpu/amd/model_gx1 src/cpu/amd/model_gx2 src/cpu/amd/model_lx src/cpu/intel/slot_2 src/mainboard/amd/db800 src/mainboard/amd/norwich src/mainboard/artecgroup/d
Author: stepan Date: Thu Feb 4 02:32:43 2010 New Revision: 5082 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5082 Log: Move CAR settings for all GX1, GX2, LX and Intel Slot2 boards to the CPU. This automatically adds the settings for those boards that didn't have settings at all yet. Also, small fixup to compareboard. Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de -- Please help porting all boards from newconfig to Kconfig -- This is a lot of janitor work and we can use your helping hands. The sooner we can get rid of Kbuild, the better. The KBuild report on the mailing list shows the config differences between newconfig and Kconfig. In theory, all Kconfig configs should be equal to their newconfig pendant. In practice it's better to come close but stay clean. -- Please help porting all boards from newconfig to Kconfig -- Modified: trunk/src/cpu/amd/model_gx1/Kconfig trunk/src/cpu/amd/model_gx2/Kconfig trunk/src/cpu/amd/model_lx/Kconfig trunk/src/cpu/intel/slot_2/Kconfig trunk/src/mainboard/amd/db800/Kconfig trunk/src/mainboard/amd/norwich/Kconfig trunk/src/mainboard/artecgroup/dbe61/Kconfig trunk/src/mainboard/digitallogic/msm800sev/Kconfig trunk/src/mainboard/iei/pcisa-lx-800-r10/Kconfig trunk/src/mainboard/lippert/roadrunner-lx/Kconfig trunk/src/mainboard/lippert/spacerunner-lx/Kconfig trunk/src/mainboard/pcengines/alix1c/Kconfig trunk/util/compareboard/compareboard Modified: trunk/src/cpu/amd/model_gx1/Kconfig == --- trunk/src/cpu/amd/model_gx1/Kconfig Thu Feb 4 01:55:06 2010(r5081) +++ trunk/src/cpu/amd/model_gx1/Kconfig Thu Feb 4 02:32:43 2010(r5082) @@ -21,3 +21,13 @@ config CPU_AMD_GX1 bool +config DCACHE_RAM_BASE + hex + default 0xc + depends on CPU_AMD_GX1 + +config DCACHE_RAM_SIZE + hex + default 0x01000 + depends on CPU_AMD_GX1 + Modified: trunk/src/cpu/amd/model_gx2/Kconfig == --- trunk/src/cpu/amd/model_gx2/Kconfig Thu Feb 4 01:55:06 2010(r5081) +++ trunk/src/cpu/amd/model_gx2/Kconfig Thu Feb 4 02:32:43 2010(r5082) @@ -1,2 +1,32 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 coresystems GmbH +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + config CPU_AMD_GX2 bool + +config DCACHE_RAM_BASE + hex + default 0xc + depends on CPU_AMD_GX2 + +config DCACHE_RAM_SIZE + hex + default 0x01000 + depends on CPU_AMD_GX2 + Modified: trunk/src/cpu/amd/model_lx/Kconfig == --- trunk/src/cpu/amd/model_lx/Kconfig Thu Feb 4 01:55:06 2010(r5081) +++ trunk/src/cpu/amd/model_lx/Kconfig Thu Feb 4 02:32:43 2010(r5082) @@ -1,3 +1,13 @@ config CPU_AMD_LX bool +config DCACHE_RAM_BASE + hex + default 0xc8000 + depends on CPU_AMD_LX + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on CPU_AMD_LX + Modified: trunk/src/cpu/intel/slot_2/Kconfig == --- trunk/src/cpu/intel/slot_2/Kconfig Thu Feb 4 01:55:06 2010(r5081) +++ trunk/src/cpu/intel/slot_2/Kconfig Thu Feb 4 02:32:43 2010(r5082) @@ -21,3 +21,13 @@ config CPU_INTEL_SLOT_2 bool +config DCACHE_RAM_BASE + hex + default 0xc + depends on CPU_INTEL_SLOT_2 + +config DCACHE_RAM_SIZE + hex + default 0x01000 + depends on CPU_INTEL_SLOT2 + Modified: trunk/src/mainboard/amd/db800/Kconfig == --- trunk/src/mainboard/amd/db800/Kconfig Thu Feb 4 01:55:06 2010 (r5081) +++ trunk/src/mainboard/amd/db800/Kconfig Thu Feb 4 02:32:43 2010 (r5082) @@ -32,16 +32,6 @@ default 4 depends on BOARD_AMD_DB800 -config DCACHE_RAM_BASE - hex - default 0xc8000 - depends on BOARD_AMD_DB800 - -config DCACHE_RAM_SIZE - hex - default 0x8000 - depends on BOARD_AMD_DB800 - config RAMBASE hex
[coreboot] [commit] r5083 - trunk/src/mainboard/tyan/s2881
Author: ward Date: Thu Feb 4 04:03:39 2010 New Revision: 5083 URL: http://tracker.coreboot.org/trac/coreboot/changeset/5083 Log: Revision 5051 broke Kconfig booting for the Tyan s2881 board. Up to 5050, there were two SB_HT_CHAIN_ON_BUS0 sections in the mainboard Kconfig file - one setting the parameter to 0, the other setting it to 2. Revision 5051 removed one of the two SB_HT_CHAIN_ON_BUS0 sections - the wrong one. This patch fixes that. Revision 5051 removed the wrong setting because newconfig for this board was *also* wrong. This patch fixes that too. Tested on real hardware, both with Kconfig and newconfig. Signed-off-by: Ward Vandewege w...@gnu.org Acked-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Modified: trunk/src/mainboard/tyan/s2881/Kconfig trunk/src/mainboard/tyan/s2881/Options.lb Modified: trunk/src/mainboard/tyan/s2881/Kconfig == --- trunk/src/mainboard/tyan/s2881/Kconfig Thu Feb 4 02:32:43 2010 (r5082) +++ trunk/src/mainboard/tyan/s2881/Kconfig Thu Feb 4 04:03:39 2010 (r5083) @@ -24,7 +24,7 @@ config SB_HT_CHAIN_ON_BUS0 int - default 0 + default 2 depends on BOARD_TYAN_S2881 config LB_CKS_RANGE_END Modified: trunk/src/mainboard/tyan/s2881/Options.lb == --- trunk/src/mainboard/tyan/s2881/Options.lb Thu Feb 4 02:32:43 2010 (r5082) +++ trunk/src/mainboard/tyan/s2881/Options.lb Thu Feb 4 04:03:39 2010 (r5083) @@ -128,7 +128,7 @@ default CONFIG_HT_CHAIN_END_UNITID_BASE=0x06 #make the SB HT chain on bus 0, default is not (0) -default CONFIG_SB_HT_CHAIN_ON_BUS0=0 +default CONFIG_SB_HT_CHAIN_ON_BUS0=2 ##only offset for SB chain?, default is yes(1) #default CONFIG_SB_HT_CHAIN_UNITID_OFFSET_ONLY=0 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] fix Tyan s2881 boot (Kconfig)
On Wed, Feb 03, 2010 at 06:52:57PM +0100, Stefan Reinauer wrote: On 2/3/10 6:50 PM, Ward Vandewege wrote: This fixes breakage introduced in r5051. Thanks, Ward. Sorry for the inconvenience. Acked-by: Stefan Reinauer ste...@coresystems.de No worries - fixed in r5083 for both newconfig and Kconfig. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] newconfig to Kconfig for Dummies
-- Please help porting all boards from newconfig to Kconfig-- This is a lot of janitor work and we can use your helping hands. The sooner we can get rid of Kbuild, the better. The KBuild report on the mailing list shows the config differences between newconfig and Kconfig. In theory, all Kconfig configs should be equal to their newconfig pendant. In practice it's better to come close but stay clean. -- Please help porting all boards from newconfig to Kconfig-- Hello, I really want to get my boards up to date, but I really don't know where to start. I ran the kbuildall util on my boards, stared at the the files it created for about an hour and then walked away. Being new to Kconfig and all I am a bit lost. If someone could please write a brief newconfig to Kconfig for Dummies I would be truly grateful. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
