Re: [coreboot] VGA rom can not be loaded by SEABIOS
Wang, Qingpei escribió: Hi, With the latest version of seabios, the vgarom can not be loaded correctly. I find that in the code seabios/src/optionrom.c vga_setup Can to load the vga rom from cbfs. The detail log is attached. Jason Wang BeiJing Technology Development Center Advanced Micro Devices (AMD) Hi, I had a similar problem some time ago. I mistakenly set CONFIG_OPTIONROMS_DEPLOYED 1 and it should be 0. Bye, Knut Kujat. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]: AMD RS780/SB700 support
Hi, I would suggest something from Gigabyte, as they're easily the best all around motherboards currently available, especially regarding parts quality. This model might be worth looking into: http://www.gigabyte.pt/products/mb/specs/ga-ma78gm-ud2h_10.html Since it's one that only has a revision available, whereas it's not the case with other models. They also have ATX models, which might also be of interest. Best regards, Tiago On Tue, Mar 16, 2010 at 2:10 AM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net wrote: This is really great news. Thank you so much! Please pass on our thanks to everybody who made this possible. It has been suggested that coreboot should be ported to a sizable number of AMD RS780 series mainboards during Google Summer of Code 2010. Are there any suggestions from you (AMD) for boards we should start with, i.e. server/consumer/enthusiast/embedded boards, or maybe boards which are envisioned to have a long life or big market share? Are any press releases planned about this big code contribution or should we wait until a bunch of mainboards has been ported? Regards, Carl-Daniel -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]: AMD RS780/SB700 support
Hello, I own a GA-MA785GT-UD3H ( http://www.gigabyte.de/Products/Motherboard/Products_Overview.aspx?ProductID=4694 ) but unfortunately it uses 785G / SB710. SB710 seems to be supported by Zheng Bao's patch but I am unsure about 785G. Are there any marjor differences between RS780 and RS880 except for the graphics part? I am afraid that there are too many to support it easily... Kind regards Ole Am Mittwoch, 17. März 2010 11:51:24 schrieb Tiago Marques: Hi, I would suggest something from Gigabyte, as they're easily the best all around motherboards currently available, especially regarding parts quality. This model might be worth looking into: http://www.gigabyte.pt/products/mb/specs/ga-ma78gm-ud2h_10.html Since it's one that only has a revision available, whereas it's not the case with other models. They also have ATX models, which might also be of interest. Best regards, Tiago signature.asc Description: This is a digitally signed message part. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] VGA rom can not be loaded by SEABIOS
On Wed, Mar 17, 2010 at 04:15:41PM +0800, Wang, Qingpei wrote: Hi, With the latest version of seabios, the vgarom can not be loaded correctly. I find that in the code seabios/src/optionrom.c vga_setup Did you enable CONFIG_COREBOOT_FLASH in SeaBIOS' src/config.h file? Be sure to follow the steps at: http://www.coreboot.org/SeaBIOS#SeaBIOS -Kevin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] VGA rom can not be loaded by SEABIOS
hi Kevin, I have already found the problem. Coreboot now use cbfs to organize the option rom. The vga.rom may be renamed like pci1002,731F.rom. But in seabios/optionrom.c it just check the filename with prefix vgaroms/ which can not load the vgarom. maybe coreboot should organzie the vga rom in a different way which can let seabios detect. On Wed, Mar 17, 2010 at 10:03 PM, Kevin O'Connor ke...@koconnor.net wrote: On Wed, Mar 17, 2010 at 04:15:41PM +0800, Wang, Qingpei wrote: Hi, With the latest version of seabios, the vgarom can not be loaded correctly. I find that in the code seabios/src/optionrom.c vga_setup Did you enable CONFIG_COREBOOT_FLASH in SeaBIOS' src/config.h file? Be sure to follow the steps at: http://www.coreboot.org/SeaBIOS#SeaBIOS -Kevin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Wang Qing Pei MSN:wangqing...@hotmail.com msn%3awangqing...@hotmail.com Gmail:wangqing...@gmail.com gmail%3awangqing...@gmail.com Phone:86+13426369984 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] VGA rom can not be loaded by SEABIOS
On Wed, Mar 17, 2010 at 11:10:14PM +0800, Jason Wang wrote: hi Kevin, I have already found the problem. Coreboot now use cbfs to organize the option rom. The vga.rom may be renamed like pci1002,731F.rom. But in seabios/optionrom.c it just check the filename with prefix vgaroms/ which can not load the vgarom. maybe coreboot should organzie the vga rom in a different way which can let seabios detect. SeaBIOS will load roms of the form pci,.rom. I don't see any messages from SeaBIOS about checking CBFS though, which makes me wonder if CONFIG_COREBOOT_FLASH is set. Can you also post the output of cbfstool print. -Kevin -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] More i82801dx_lpc fixups
More fixups for i82801dx_lpc.c code including, fixing
i82801dx_power_options() so CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
works, and get rid of HPET, ICH4 does not support it (btw, ICH5 is the
first to support HPET). Build and boot tested.
Signed-off-by: Joseph Smith j...@settoplinux.org
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
Index: src/southbridge/intel/i82801dx/i82801dx_lpc.c
===
--- src/southbridge/intel/i82801dx/i82801dx_lpc.c (revision 5251)
+++ src/southbridge/intel/i82801dx/i82801dx_lpc.c (working copy)
@@ -64,7 +64,6 @@
if (reg32 != (1 25))
die(APIC Error\n);
- /* TODO: From i82801ca, needed/useful on other ICH? */
*ioapic_index = 3; /* Select Boot Configuration register. */
*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
}
@@ -91,37 +90,85 @@
pci_write_config8(dev, PIRQF_ROUT, config-pirqf_routing);
pci_write_config8(dev, PIRQG_ROUT, config-pirqg_routing);
pci_write_config8(dev, PIRQH_ROUT, config-pirqh_routing);
-
}
static void i82801dx_power_options(device_t dev)
{
- u8 byte;
- int pwr_on = -1;
+ u8 reg8;
+ u16 reg16, pmbase;
+ u32 reg32;
+ const char *state;
+
+ int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
int nmi_option;
- /* power after power fail */
- /* FIXME this doesn't work! */
/* Which state do we want to goto after g3 (power restored)?
* 0 == S0 Full On
* 1 == S5 Soft Off
+ *
+ * If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
*/
- pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
- printk_info(Set power %s if power fails\n, pwr_on ? on : off);
+ if (get_option(pwr_on, power_on_after_fail) 0)
+ pwr_on = MAINBOARD_POWER_ON;
+ reg8 = pci_read_config8(dev, GEN_PMCON_3);
+ reg8 = 0xfe;
+ switch (pwr_on) {
+ case MAINBOARD_POWER_OFF:
+ reg8 |= 1;
+ state = off;
+ break;
+ case MAINBOARD_POWER_ON:
+ reg8 = ~1;
+ state = on;
+ break;
+ case MAINBOARD_POWER_KEEP:
+ reg8 = ~1;
+ state = state keep;
+ break;
+ default:
+ state = undefined;
+ }
+
+ reg8 = ~(1 3); /* minimum asssertion is 1 to 2 RTCCLK */
+
+ pci_write_config8(dev, GEN_PMCON_3, reg8);
+ printk_info(Set power %s after power failure.\n, state);
+
/* Set up NMI on errors. */
- byte = inb(0x61);
- byte = ~(1 3); /* IOCHK# NMI Enable */
- byte = ~(1 2); /* PCI SERR# Enable */
- outb(byte, 0x61);
- byte = inb(0x70);
+ reg8 = inb(0x61);
+ reg8 = 0x0f; /* Higher Nibble must be 0 */
+ reg8 = ~(1 3); /* IOCHK# NMI Enable */
+ // reg8 = ~(1 2); /* PCI SERR# Enable */
+ reg8 |= (1 2); /* PCI SERR# Disable for now */
+ outb(reg8, 0x61);
+ reg8 = inb(0x70);
nmi_option = NMI_OFF;
get_option(nmi_option, nmi);
if (nmi_option) {
- byte = ~(1 7); /* Set NMI. */
- outb(byte, 0x70);
+ printk_info (NMI sources enabled.\n);
+ reg8 = ~(1 7); /* Set NMI. */
+ } else {
+ printk_info (NMI sources disabled.\n);
+ reg8 |= ( 1 7); /* Disable NMI. */
}
+ outb(reg8, 0x70);
+
+ /* Set SMI# rate down and enable CPU_SLP# */
+ reg16 = pci_read_config16(dev, GEN_PMCON_1);
+ reg16 = ~(3 0); // SMI# rate 1 minute
+ reg16 |= (1 5); // CPUSLP_EN Desktop only
+ pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+ pmbase = pci_read_config16(dev, 0x40) 0xfffe;
+
+ /* Set up power management block and determine sleep mode */
+ reg32 = inl(pmbase + 0x04); // PM1_CNT
+
+ reg32 = ~(7 10); // SLP_TYP
+ reg32 |= (1 0); // SCI_EN
+ outl(reg32, pmbase + 0x04);
}
static void gpio_init(device_t dev)
@@ -177,27 +224,6 @@
pci_write_config16(dev, LPC_EN, 0x300F);
}
-static void enable_hpet(struct device *dev)
-{
- u32 reg32;
- u32 code = (0 0x3);
-
- reg32 = pci_read_config32(dev, GEN_CNTL);
- reg32 |= (1 17); /* Enable HPET. */
- /*
- * Bits [16:15] Memory Address Range
- * 00 FED0_h - FED0_03FFh
- * 01 FED0_1000h - FED0_13FFh
- * 10 FED0_2000h - FED0_23FFh
- * 11 FED0_3000h - FED0_33FFh
- */
- reg32 = ~(3 15); /* Clear it */
- reg32 |= (code 15);
- pci_write_config32(dev, GEN_CNTL, reg32);
-
- printk_debug(Enabling HPET @0x%x\n, HPET_ADDR | (code 12));
-}
-
static void lpc_init(struct device *dev)
{
/* Set the value for PCI command register. */
@@ -228,9 +254,6 @@
/* Setup decode ports and LPC I/F enables. */
i82801dx_lpc_decode_en(dev);
-
- /* Initialize the High Precision Event Timers */
- enable_hpet(dev);
}
static void i82801dx_lpc_read_resources(device_t dev)
Index: src/southbridge/intel/i82801dx/i82801dx.h
===
--- src/southbridge/intel/i82801dx/i82801dx.h (revision 5251)
+++ src/southbridge/intel/i82801dx/i82801dx.h (working copy)
@@ -37,7 +37,6 @@
#endif
#define IO_APIC_ADDR 0xfec0
-#define HPET_ADDR 0xfed0
#define DEBUG_PERIODIC_SMIS 0
@@ -202,6 +201,10 @@
#define TCOBASE 0x60 /* TCO Base Address Register */
#define TCO1_CNT 0x08 /* TCO1 Control Register */
+#define GEN_PMCON_1 0xa0
+#define GEN_PMCON_2 0xa2
+#define
[coreboot] ICH HPET
FYI, The HPET code in i82801ex, does absolutely nothing. It reads the reg and configs it but does not write it back to the reg... And ICH 0-4 does not support HPET and should be removed from code -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ICH HPET
On Wed, Mar 17, 2010 at 12:23:16PM -0400, Joseph Smith wrote: FYI, The HPET code in i82801ex, does absolutely nothing. It reads the reg and configs it but does not write it back to the reg... That should be fixed, yes. And ICH 0-4 does not support HPET and should be removed from code Not quite, ICH3 and ICH4 do have HPET, just undocumented by Intel. There's been kernel support to force-enable it since 2007 which obviously works fine and has been tested by various people since then. http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=158ad3260ba3b006e3c6dfad05298e9d7889c5b1 So I think we should keep the ICH3/4 code around (ICH0-ICH2 can be safely dropped I guess). Uwe. -- http://www.hermann-uwe.de | http://www.randomprojects.org http://www.crazy-hacks.org | http://www.unmaintained-free-software.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5252 - in trunk/src/southbridge/intel: i82801ax i82801bx i82801dx i82801ex
Author: stepan
Date: Wed Mar 17 18:50:48 2010
New Revision: 5252
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5252
Log:
fix HPET on some ICH southbridges
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c
trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c
trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c
trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c
Modified: trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c
==
--- trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c Wed Mar 17 05:40:15
2010(r5251)
+++ trunk/src/southbridge/intel/i82801ax/i82801ax_lpc.c Wed Mar 17 18:50:48
2010(r5252)
@@ -272,28 +272,6 @@
}
}
-static void enable_hpet(struct device *dev)
-{
-#ifdef HPET_PRESENT
- uint32_t reg32;
- uint32_t code = (0 0x3);
-
- reg32 = pci_read_config32(dev, GEN_CNTL);
- reg32 |= (1 17); /* Enable HPET. */
- /*
-* Bits [16:15] Memory Address Range
-* 00 FED0_h - FED0_03FFh
-* 01 FED0_1000h - FED0_13FFh
-* 10 FED0_2000h - FED0_23FFh
-* 11 FED0_3000h - FED0_33FFh
-*/
- reg32 = ~(3 15);/* Clear it */
- reg32 |= (code 15);
- /* TODO: reg32 is never written to anywhere? */
- printk_debug(Enabling HPET @0x%x\n, HPET_ADDR | (code 12));
-#endif
-}
-
static void lpc_init(struct device *dev)
{
uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID);
@@ -326,9 +304,6 @@
/* Setup decode ports and LPC I/F enables. */
i82801ax_lpc_decode_en(dev, ich_model);
-
- /* Initialize the High Precision Event Timers, if present. */
- enable_hpet(dev);
}
static void i82801ax_lpc_read_resources(device_t dev)
Modified: trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c
==
--- trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c Wed Mar 17 05:40:15
2010(r5251)
+++ trunk/src/southbridge/intel/i82801bx/i82801bx_lpc.c Wed Mar 17 18:50:48
2010(r5252)
@@ -272,28 +272,6 @@
}
}
-static void enable_hpet(struct device *dev)
-{
-#ifdef HPET_PRESENT
- uint32_t reg32;
- uint32_t code = (0 0x3);
-
- reg32 = pci_read_config32(dev, GEN_CNTL);
- reg32 |= (1 17); /* Enable HPET. */
- /*
-* Bits [16:15] Memory Address Range
-* 00 FED0_h - FED0_03FFh
-* 01 FED0_1000h - FED0_13FFh
-* 10 FED0_2000h - FED0_23FFh
-* 11 FED0_3000h - FED0_33FFh
-*/
- reg32 = ~(3 15);/* Clear it */
- reg32 |= (code 15);
- /* TODO: reg32 is never written to anywhere? */
- printk_debug(Enabling HPET @0x%x\n, HPET_ADDR | (code 12));
-#endif
-}
-
static void lpc_init(struct device *dev)
{
uint16_t ich_model = pci_read_config16(dev, PCI_DEVICE_ID);
@@ -326,9 +304,6 @@
/* Setup decode ports and LPC I/F enables. */
i82801bx_lpc_decode_en(dev, ich_model);
-
- /* Initialize the High Precision Event Timers, if present. */
- enable_hpet(dev);
}
static void i82801bx_lpc_read_resources(device_t dev)
Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c
==
--- trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 05:40:15
2010(r5251)
+++ trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 18:50:48
2010(r5252)
@@ -177,27 +177,6 @@
pci_write_config16(dev, LPC_EN, 0x300F);
}
-static void enable_hpet(struct device *dev)
-{
- u32 reg32;
- u32 code = (0 0x3);
-
- reg32 = pci_read_config32(dev, GEN_CNTL);
- reg32 |= (1 17); /* Enable HPET. */
- /*
-* Bits [16:15] Memory Address Range
-* 00 FED0_h - FED0_03FFh
-* 01 FED0_1000h - FED0_13FFh
-* 10 FED0_2000h - FED0_23FFh
-* 11 FED0_3000h - FED0_33FFh
-*/
- reg32 = ~(3 15);/* Clear it */
- reg32 |= (code 15);
- pci_write_config32(dev, GEN_CNTL, reg32);
-
- printk_debug(Enabling HPET @0x%x\n, HPET_ADDR | (code 12));
-}
-
static void lpc_init(struct device *dev)
{
/* Set the value for PCI command register. */
@@ -228,9 +207,6 @@
/* Setup decode ports and LPC I/F enables. */
i82801dx_lpc_decode_en(dev);
-
- /* Initialize the High Precision Event Timers */
- enable_hpet(dev);
}
static void i82801dx_lpc_read_resources(device_t dev)
Modified: trunk/src/southbridge/intel/i82801ex/i82801ex_lpc.c
==
Re: [coreboot] ICH HPET
On 3/17/10 6:43 PM, Uwe Hermann wrote: And ICH 0-4 does not support HPET and should be removed from code Not quite, ICH3 and ICH4 do have HPET, just undocumented by Intel. There's been kernel support to force-enable it since 2007 which obviously works fine and has been tested by various people since then. http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=158ad3260ba3b006e3c6dfad05298e9d7889c5b1 So I think we should keep the ICH3/4 code around (ICH0-ICH2 can be safely dropped I guess). Uh,.. you are right..! sorry for my quick shot.. I'll back out the dx change I made... CX never had enable_hpet code it seems. -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ICH HPET
On 03/17/2010 02:37 PM, Stefan Reinauer wrote: On 3/17/10 6:43 PM, Uwe Hermann wrote: And ICH 0-4 does not support HPET and should be removed from code Not quite, ICH3 and ICH4 do have HPET, just undocumented by Intel. There's been kernel support to force-enable it since 2007 which obviously works fine and has been tested by various people since then. http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commitdiff;h=158ad3260ba3b006e3c6dfad05298e9d7889c5b1 So I think we should keep the ICH3/4 code around (ICH0-ICH2 can be safely dropped I guess). Uh,.. you are right..! sorry for my quick shot.. I'll back out the dx change I made... CX never had enable_hpet code it seems. Ah cool! Stefan, don't do anything, new patch coming. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]: AMD RS780/SB700 support
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Niels Ole Salscheider wrote: Hello, I own a GA-MA785GT-UD3H ( http://www.gigabyte.de/Products/Motherboard/Products_Overview.aspx?ProductID=4694 ) but unfortunately it uses 785G / SB710. SB710 seems to be supported by Zheng Bao's patch but I am unsure about 785G. It works, check my thread about the Asrock board. The SB700 code will work on any SB7xx fhe RS785 has same PCIids except the graphics chip, which is rv620 and not rv610. I just added the ID and it does work it seems. Rudolf -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkuhTd4ACgkQ3J9wPJqZRNUxTACfeBYlnRkmNm56Ug4uSc0etmBk as8AoM3ysH3sNCTRUSv56UBTl3Ppgs/s =0bTL -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [Patch] remove some warnings
1. gcc doesn't like a character array being cast to a struct. -extern unsigned char AmlCode[]; +extern void* AmlCode; 2. Include console/console.h if you're using PRINTK_IN_CAR (not ROMCC) 3. Add a few more nuisance prototypes. Signed-off-by: Myles Watson myle...@gmail.com I think it would be nice to add the number of warnings for each board on one of the build pages. It looks like there are many that could compile without any warnings, and some that look like they have a few too many. Here's the list after this patch: coreboot-builds/a-trend_atc-6220/make.log:2 coreboot-builds/a-trend_atc-6240/make.log:2 coreboot-builds/abit_be6-ii_v2_0/make.log:2 coreboot-builds/advantech_pcm-5820/make.log:76 coreboot-builds/amd_db800/make.log:111 coreboot-builds/amd_dbm690t/make.log:132 coreboot-builds/amd_mahogany/make.log:182 coreboot-builds/amd_mahogany_fam10/make.log:378 coreboot-builds/amd_norwich/make.log:110 coreboot-builds/amd_pistachio/make.log:127 coreboot-builds/amd_rumba/make.log:65 coreboot-builds/amd_serengeti_cheetah/make.log:74 coreboot-builds/amd_serengeti_cheetah_fam10/make.log:270 coreboot-builds/arima_hdama/make.log:49 coreboot-builds/artecgroup_dbe61/make.log:112 coreboot-builds/asi_mb_5blgp/make.log:2 coreboot-builds/asi_mb_5blmp/make.log:2 coreboot-builds/asus_a8n_e/make.log:54 coreboot-builds/asus_a8v-e_se/make.log:74 coreboot-builds/asus_m2v-mx_se/make.log:103 coreboot-builds/asus_mew-am/make.log:9 coreboot-builds/asus_mew-vm/make.log:10 coreboot-builds/asus_p2b-d/make.log:3 coreboot-builds/asus_p2b-ds/make.log:3 coreboot-builds/asus_p2b-f/make.log:2 coreboot-builds/asus_p2b-ls/make.log:2 coreboot-builds/asus_p2b/make.log:2 coreboot-builds/asus_p3b-f/make.log:2 coreboot-builds/axus_tc320/make.log:2 coreboot-builds/azza_pt-6ibd/make.log:2 coreboot-builds/bcom_winnet100/make.log:2 coreboot-builds/bcom_winnetp680/make.log:100 coreboot-builds/biostar_m6tba/make.log:2 coreboot-builds/broadcom_blast/make.log:78 coreboot-builds/compaq_deskpro_en_sff_p600/make.log:2 coreboot-builds/dell_s1850/make.log:5 coreboot-builds/digitallogic_adl855pc/make.log:10 coreboot-builds/digitallogic_msm586seg/make.log:12 coreboot-builds/digitallogic_msm800sev/make.log:111 coreboot-builds/eaglelion_5bcm/make.log:2 coreboot-builds/emulation_qemu-x86/make.log:0 coreboot-builds/gigabyte_ga-6bxc/make.log:2 coreboot-builds/gigabyte_ga_2761gxdk/make.log:128 coreboot-builds/gigabyte_m57sli/make.log:133 coreboot-builds/hp_dl145_g3/make.log:110 coreboot-builds/hp_e_vectra_p2706t/make.log:9 coreboot-builds/ibm_e325/make.log:48 coreboot-builds/ibm_e326/make.log:50 coreboot-builds/iei_juki-511p/make.log:2 coreboot-builds/iei_nova4899r/make.log:2 coreboot-builds/iei_pcisa-lx-800-r10/make.log:111 coreboot-builds/intel_d945gclf/make.log:24 coreboot-builds/intel_eagleheights/make.log:49 coreboot-builds/intel_jarrell/make.log:13 coreboot-builds/intel_mtarvon/make.log:6 coreboot-builds/intel_truxton/make.log:6 coreboot-builds/intel_xe7501devkit/make.log:15 coreboot-builds/iwill_dk8_htx/make.log:51 coreboot-builds/iwill_dk8s2/make.log:58 coreboot-builds/iwill_dk8x/make.log:53 coreboot-builds/jetway_j7f24/make.log:99 coreboot-builds/kontron_986lcd-m/make.log:15 coreboot-builds/kontron_kt690/make.log:131 coreboot-builds/lippert_frontrunner/make.log:42 coreboot-builds/lippert_roadrunner-lx/make.log:113 coreboot-builds/lippert_spacerunner-lx/make.log:114 coreboot-builds/mitac_6513wu/make.log:9 coreboot-builds/msi_ms6119/make.log:2 coreboot-builds/msi_ms6147/make.log:2 coreboot-builds/msi_ms6156/make.log:2 coreboot-builds/msi_ms6178/make.log:9 coreboot-builds/msi_ms7135/make.log:58 coreboot-builds/msi_ms7260/make.log:131 coreboot-builds/msi_ms9185/make.log:108 coreboot-builds/msi_ms9282/make.log:132 coreboot-builds/msi_ms9652_fam10/make.log:298 coreboot-builds/nec_powermate2000/make.log:9 coreboot-builds/newisys_khepri/make.log:48 coreboot-builds/nvidia_l1_2pvv/make.log:135 coreboot-builds/olpc_btest/make.log:72 coreboot-builds/olpc_rev_a/make.log:71 coreboot-builds/pcengines_alix1c/make.log:112 coreboot-builds/rca_rm4100/make.log:1 coreboot-builds/roda_rk886ex/make.log:25 coreboot-builds/soyo_sy-6ba-plus-iii/make.log:2 coreboot-builds/sunw_ultra40/make.log:59 coreboot-builds/supermicro_h8dme/make.log:126 coreboot-builds/supermicro_h8dmr/make.log:124 coreboot-builds/supermicro_h8dmr_fam10/make.log:293 coreboot-builds/supermicro_h8qme_fam10/make.log:293 coreboot-builds/supermicro_x6dai_g/make.log:13 coreboot-builds/supermicro_x6dhe_g/make.log:17 coreboot-builds/supermicro_x6dhe_g2/make.log:9 coreboot-builds/supermicro_x6dhr_ig/make.log:6 coreboot-builds/supermicro_x6dhr_ig2/make.log:6 coreboot-builds/technexion_tim5690/make.log:130 coreboot-builds/technexion_tim8690/make.log:130 coreboot-builds/technologic_ts5300/make.log:10 coreboot-builds/televideo_tc7020/make.log:2 coreboot-builds/thomson_ip1000/make.log:0 coreboot-builds/tyan_s1846/make.log:2 coreboot-builds/tyan_s2735/make.log:78 coreboot-builds/tyan_s2850/make.log:52
[coreboot] [commit] r5253 - trunk/src/southbridge/intel/i82801dx
Author: stepan
Date: Wed Mar 17 23:08:51 2010
New Revision: 5253
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5253
Log:
revert the faulty part of r5252
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c
Modified: trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c
==
--- trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 18:50:48
2010(r5252)
+++ trunk/src/southbridge/intel/i82801dx/i82801dx_lpc.c Wed Mar 17 23:08:51
2010(r5253)
@@ -177,6 +177,30 @@
pci_write_config16(dev, LPC_EN, 0x300F);
}
+/* ICH4 does not mention HPET in the docs, but
+ * all ICH3 and ICH4 do have HPETs built in.
+ */
+static void enable_hpet(struct device *dev)
+{
+ u32 reg32;
+ u32 code = (0 0x3);
+
+ reg32 = pci_read_config32(dev, GEN_CNTL);
+ reg32 |= (1 17); /* Enable HPET. */
+ /*
+* Bits [16:15] Memory Address Range
+* 00 FED0_h - FED0_03FFh
+* 01 FED0_1000h - FED0_13FFh
+* 10 FED0_2000h - FED0_23FFh
+* 11 FED0_3000h - FED0_33FFh
+*/
+ reg32 = ~(3 15);/* Clear it */
+ reg32 |= (code 15);
+ pci_write_config32(dev, GEN_CNTL, reg32);
+
+ printk_debug(Enabling HPET @0x%x\n, HPET_ADDR | (code 12));
+}
+
static void lpc_init(struct device *dev)
{
/* Set the value for PCI command register. */
@@ -207,6 +231,9 @@
/* Setup decode ports and LPC I/F enables. */
i82801dx_lpc_decode_en(dev);
+
+ /* Initialize the High Precision Event Timers */
+ enable_hpet(dev);
}
static void i82801dx_lpc_read_resources(device_t dev)
--
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[coreboot] [commit] r5254 - in trunk/src: cpu/amd/model_lx northbridge/amd/lx southbridge/amd/cs5536 southbridge/amd/sb600 southbridge/amd/sb700
Author: stepan
Date: Wed Mar 17 23:09:26 2010
New Revision: 5254
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5254
Log:
more warnings gone...
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/cpu/amd/model_lx/vsmsetup.c
trunk/src/northbridge/amd/lx/northbridge.c
trunk/src/northbridge/amd/lx/northbridgeinit.c
trunk/src/northbridge/amd/lx/raminit.c
trunk/src/southbridge/amd/cs5536/cs5536.c
trunk/src/southbridge/amd/cs5536/cs5536_early_setup.c
trunk/src/southbridge/amd/sb600/sb600_hda.c
trunk/src/southbridge/amd/sb600/sb600_sata.c
trunk/src/southbridge/amd/sb600/sb600_usb.c
trunk/src/southbridge/amd/sb700/sb700_hda.c
trunk/src/southbridge/amd/sb700/sb700_usb.c
Modified: trunk/src/cpu/amd/model_lx/vsmsetup.c
==
--- trunk/src/cpu/amd/model_lx/vsmsetup.c Wed Mar 17 23:08:51 2010
(r5253)
+++ trunk/src/cpu/amd/model_lx/vsmsetup.c Wed Mar 17 23:09:26 2010
(r5254)
@@ -290,7 +290,7 @@
if ((unsigned int)cbfs_load_stage(vsa) != VSA2_ENTRY_POINT) {
printk_err(do_vsmbios: Failed to load VSA.\n);
}
- buf = VSA2_BUFFER;
+ buf = (unsigned char *)VSA2_BUFFER;
printk_debug(buf %p *buf %d buf[256k] %d\n,
buf, buf[0], buf[SMM_SIZE * 1024]);
printk_debug(buf[0x20] signature is %x:%x:%x:%x\n,
@@ -501,15 +501,15 @@
printk_debug(biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n,
ebp, esp, edi, esi);
printk_debug(biosint: ip 0x%x cs 0x%x flags 0x%x\n,
-ip, cs, flags);
+(u32)ip, (u32)cs, (u32)flags);
printk_debug(biosint: gs 0x%x fs 0x%x ds 0x%x es 0x%x\n,
-gsfs 16, gsfs 0x, dses 16, dses 0x);
+(u16)(gsfs 16), (u16)(gsfs 0x), (u16)(dses
16), (u16)(dses 0x));
// cases in a good compiler are just as good as your own tables.
switch (intnumber) {
case 0 ... 15:
// These are not BIOS service, but the CPU-generated exceptions
- printk_info(biosint: Oops, exception %u\n, intnumber);
+ printk_info(biosint: Oops, exception 0x%x\n, (u32)intnumber);
if (esp 0x1000) {
printk_debug(Stack contents: );
while (esp 0x1000) {
@@ -537,7 +537,7 @@
ebx, edx, ecx, eax, flags);
break;
default:
- printk_info(BIOSINT: Unsupport int #0x%x\n, intnumber);
+ printk_info(BIOSINT: Unsupported int #0x%x\n, (u32)intnumber);
break;
}
if (ret)
@@ -617,16 +617,7 @@
unsigned long *pesp, unsigned long *pebx, unsigned long *pedx,
unsigned long *pecx, unsigned long *peax, unsigned long *pflags)
{
- unsigned long edi = *pedi;
- unsigned long esi = *pesi;
- unsigned long ebp = *pebp;
- unsigned long esp = *pesp;
- unsigned long ebx = *pebx;
- unsigned long edx = *pedx;
- unsigned long ecx = *pecx;
- unsigned long eax = *peax;
- unsigned long flags = *pflags;
- unsigned short func = (unsigned short)eax;
+ unsigned short func = (unsigned short)*peax;
int retval = 0;
unsigned short devid, vendorid, devfn;
short devindex; /* Use short to get rid of gabage in upper half
of 32-bit register */
@@ -740,7 +731,7 @@
unsigned long *ecx, unsigned long *eax, unsigned long *flags)
{
int res = -1;
- printk_debug(handleint21, eax 0x%x\n, *eax);
+ printk_debug(handleint21, eax 0x%x\n, (u32)*eax);
switch (*eax 0x) {
case 0x5f19:
break;
Modified: trunk/src/northbridge/amd/lx/northbridge.c
==
--- trunk/src/northbridge/amd/lx/northbridge.c Wed Mar 17 23:08:51 2010
(r5253)
+++ trunk/src/northbridge/amd/lx/northbridge.c Wed Mar 17 23:09:26 2010
(r5254)
@@ -253,16 +253,16 @@
}
iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
- printk_debug(IOR 0x%08X is now 0x%08X\n,
+ printk_debug(IOR 0x%08X is now 0x%08lX\n,
GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
iol = inl(GPIOL_EVENTS_ENABLE);
- printk_debug(IOR 0x%08X is now 0x%08X\n,
+ printk_debug(IOR 0x%08X is now 0x%08lX\n,
GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
iol = inl(GPIOL_INPUT_INVERT_ENABLE);
- printk_debug(IOR 0x%08X is now 0x%08X\n,
+ printk_debug(IOR 0x%08X is now 0x%08lX\n,
GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
iol = inl(GPIO_MAPPER_X);
- printk_debug(IOR 0x%08X is now 0x%08X\n, GPIO_IO_BASE + GPIO_MAPPER_X,
+
Re: [coreboot] [Patch] remove some warnings
On 3/17/10 10:33 PM, Myles Watson wrote: +#ifndef __ROMCC__ +#include lib.h /* Prototypes */ +#endif I think the ifndef __ROMCC__ should go into lib.h just as __PRE_RAM__ did.. Acked-by: Stefan Reinauer ste...@coresystems.de -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [Patch] remove some warnings
On 3/17/10 10:33 PM, Myles Watson wrote: -extern unsigned char AmlCode[]; +extern void* AmlCode; Is this really a void *? Did you test that this works? -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [Patch] remove some warnings
On 3/17/10 11:11 PM, Stefan Reinauer wrote:
On 3/17/10 10:33 PM, Myles Watson wrote:
+#ifndef __ROMCC__
+#include lib.h /* Prototypes */
+#endif
I think the ifndef __ROMCC__ should go into lib.h just as __PRE_RAM__ did..
Acked-by: Stefan Reinauer ste...@coresystems.de
Sorry, got to N-Ack again
unsigned char AmlCode[] =
{
0x44,0x53,0x44,0x54,0xE6,0x27,0x00,0x00, /* DSDT.'.. */
0x02,0x7C,0x41,0x4D,0x44,0x20,0x20,0x20, /* 0008.|AMD*/
0x4D,0x41,0x48,0x4F,0x47,0x41,0x4E,0x59, /* 0010MAHOGANY */
}
and in another file it looks like this:
-extern unsigned char AmlCode[];
+extern void* AmlCode;
So AmlCode is used as a void * pointing to the address 0x54445344
which is definitely not what you want...
Even though it might appear that char *foo and char foo[] are the same
in C, they're in fact not.
Stefan
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Re: [coreboot] [PATCH]Remove failover/fallback/normal decision from mainboards' romstage.c
On 3/17/10 10:42 PM, Patrick Georgi wrote: Hi, attached patch removes the failover/fallback/normal decision from romstage.c files of mainboards that did failover. It is the first part of a larger effort. This mechanism was used by newconfig style builds and is not useful anymore since we dropped newconfig. In fact, in rare circumstances it might lead to coreboot hanging early on boot (when normal is selected - this should fix itself by three reboots, as coreboot reverts to fallback then) The code assumes that various places are visited twice on boot. That's not true anymore for Kconfig builds, no matter if the boards is using romstage as bootblock, or the tiny bootblock. Removing these assumptions simplifies the code and should help the user when trying to track the code flow. The change looks big, but it's really a couple of simple and relatively mechanical steps repeated for lots of boards: 1. In failover_process(), I removed the fallback/normal selection logic and kept the remaining hardware init in. The if-clauses' conditions are reverted to match. Remove #if failover||fallback guard. 2. Change cache_as_ram_main() to first call failover_process, then real_main unconditionally. 3. Move failover_process's code to the beginning of real_main, remove failover_process and its call in cache_as_ram_main. 4. Remove cache_as_ram_main, rename real_main to cache_as_ram_main (same arguments, so no problem with that) As those changes are quite mechanical, but not easily automated, I'd prefer some additional eyeballs that look if the end result of the boards looks alike (they should be more similar to each other than before). The patch is build tested and boot tested on amd/serengeti_cheetah in SimNow. After the changes, the entire hardware init is ran on cold boot, on warm reset the hardware init that used to be in failover_process is skipped. The affected boards do not use __fallback_image or __normal_image anymore. The next step will a comparable change to the remaining boards. After that, I'll aim for the removal of the remaining uses of HAVE_FALLBACK_BOOT, USE_FALLBACK_IMAGE, HAVE_FAILOVER_BOOT, USE_FAILOVER_IMAGE and their definition in Kconfig. Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]: Configure the GFX mode of RS780
On Tue, Mar 16, 2010 at 2:34 AM, Bao, Zheng zheng@amd.com wrote: This patch configures the toppology of rs780 graphics. The new gfx_dual_slot option 2 is for the board which can configure the double/single mode. In that case, we need to know whether a device is plugged behind DEV 3. So the is_dev3_present() is needed. This doesn't help mahogany much. You will need in the future. Add an option for HDMI display. If you need it, just uncomment it. + vgainfo.ulDDISlot1Config = 0x000c0011; //0; //VGA + //vgainfo.ulDDISlot1Config = 0x000c00FF; //0; //HDMI Instead of requiring it to be uncommented in the sb source code, can it be a mainboard device option in devicetree.cb like the gpp_configuration? Marc -- http://se-eng.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [Patch] remove some warnings
On Wed, Mar 17, 2010 at 4:16 PM, Stefan Reinauer ste...@coresystems.dewrote:
On 3/17/10 11:11 PM, Stefan Reinauer wrote:
On 3/17/10 10:33 PM, Myles Watson wrote:
+#ifndef __ROMCC__
+#include lib.h /* Prototypes */
+#endif
I think the ifndef __ROMCC__ should go into lib.h just as __PRE_RAM__
did..
Acked-by: Stefan Reinauer ste...@coresystems.de
Sorry, got to N-Ack again
unsigned char AmlCode[] =
{
0x44,0x53,0x44,0x54,0xE6,0x27,0x00,0x00, /* DSDT.'.. */
0x02,0x7C,0x41,0x4D,0x44,0x20,0x20,0x20, /* 0008.|AMD*/
0x4D,0x41,0x48,0x4F,0x47,0x41,0x4E,0x59, /* 0010MAHOGANY */
}
and in another file it looks like this:
-extern unsigned char AmlCode[];
+extern void* AmlCode;
So AmlCode is used as a void * pointing to the address 0x54445344
which is definitely not what you want...
You're right. And that's definitely not what I expected to happen. It
seems like there ought to be a correct way to do this. I'll keep looking.
Thanks,
Myles
Even though it might appear that char *foo and char foo[] are the same
in C, they're in fact not.
Stefan
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Re: [coreboot] [Patch] remove some warnings
On 3/18/10 12:05 AM, Myles Watson wrote:
unsigned char AmlCode[] =
{
0x44,0x53,0x44,0x54,0xE6,0x27,0x00,0x00, /*
DSDT.'.. */
and in another file it looks like this:
-extern unsigned char AmlCode[];
+extern void* AmlCode;
So AmlCode is used as a void * pointing to the address 0x54445344
which is definitely not what you want...
You're right. And that's definitely not what I expected to happen.
It seems like there ought to be a correct way to do this. I'll keep
looking.
What is it, you want to do?
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Re: [coreboot] [Patch] remove some warnings
-extern unsigned char AmlCode[]; +extern void* AmlCode; So AmlCode is used as a void * pointing to the address 0x54445344 which is definitely not what you want... You're right. And that's definitely not what I expected to happen. It seems like there ought to be a correct way to do this. I'll keep looking. What is it, you want to do? Get rid of the type punned warning that gcc gives for that code where AmlCode gets cast to acpi_header_t. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [Patch] remove some warnings
Hi Segher, you're probably able to solve this one easily. On 18.03.2010 00:45, Myles Watson wrote: -extern unsigned char AmlCode[]; +extern void* AmlCode; So AmlCode is used as a void * pointing to the address 0x54445344 which is definitely not what you want... You're right. And that's definitely not what I expected to happen. It seems like there ought to be a correct way to do this. I'll keep looking. What is it, you want to do? Get rid of the type punned warning that gcc gives for that code where AmlCode gets cast to acpi_header_t. Could __attribute__((may_alias)) help? Then again, a Google search turns up a few miscompiles with that attribute, so another option may be to run memcpy(AmlCode,AmlCode, ...). Regards, Carl-Daniel -- I do consider assignment statements and pointer variables to be among computer science's most valuable treasures. -- Donald E. Knuth -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [Patch] remove some warnings
On Wed, Mar 17, 2010 at 6:17 PM, Carl-Daniel Hailfinger c-d.hailfinger.devel.2...@gmx.net wrote: Hi Segher, you're probably able to solve this one easily. On 18.03.2010 00:45, Myles Watson wrote: -extern unsigned char AmlCode[]; +extern void* AmlCode; So AmlCode is used as a void * pointing to the address 0x54445344 What is it, you want to do? Get rid of the type punned warning that gcc gives for that code where AmlCode gets cast to acpi_header_t. Could __attribute__((may_alias)) help? I'd rather not use an attribute if we can just use a cast. It seems to work to have an intermediate void*: void_ptr = AmlCode_ssdt; current += ((acpi_header_t *)void_ptr)-length; It compiles without warning and is functionally correct, but it may be too ugly. I'm still surprised that it needs to be AmlCode_ssdt. I really expected Amlcode_ssdt to be a cast-able pointer. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]: AMD RS780/SB700 support
On Wed, Mar 17, 2010 at 10:47:10PM +0100, Rudolf Marek wrote: Niels Ole Salscheider wrote: Hello, I own a GA-MA785GT-UD3H ( http://www.gigabyte.de/Products/Motherboard/Products_Overview.aspx?ProductID=4694 ) but unfortunately it uses 785G / SB710. SB710 seems to be supported by Zheng Bao's patch but I am unsure about 785G. It works, check my thread about the Asrock board. The SB700 code will work on any SB7xx fhe RS785 has same PCIids except the graphics chip, which is rv620 and not rv610. I just added the ID and it does work it seems. But that Gigabyte board is DDR3 - didn't Zheng say that was not supported with fam10 CPUs yet? Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator Join us in Cambridge for LibrePlanet, March 19th-21st! http://groups.fsf.org/wiki/LibrePlanet2010 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]: AMD RS780/SB700 support
On Wed, Mar 17, 2010 at 6:34 PM, Ward Vandewege w...@gnu.org wrote: On Wed, Mar 17, 2010 at 10:47:10PM +0100, Rudolf Marek wrote: Niels Ole Salscheider wrote: Hello, I own a GA-MA785GT-UD3H ( http://www.gigabyte.de/Products/Motherboard/Products_Overview.aspx?ProductID=4694 ) but unfortunately it uses 785G / SB710. SB710 seems to be supported by Zheng Bao's patch but I am unsure about 785G. It works, check my thread about the Asrock board. The SB700 code will work on any SB7xx fhe RS785 has same PCIids except the graphics chip, which is rv620 and not rv610. I just added the ID and it does work it seems. But that Gigabyte board is DDR3 - didn't Zheng say that was not supported with fam10 CPUs yet? Thanks, Ward. No DDR3 yet but I hope that we can support it soon. Marc -- http://se-eng.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [commit] r5254 - in trunk/src: cpu/amd/model_lx northbridge/amd/lx southbridge/amd/cs5536 southbridge/amd/sb600 southbridge/amd/sb700
repository service wrote: printk_debug(biosint: ip 0x%x cs 0x%x flags 0x%x\n, - ip, cs, flags); + (u32)ip, (u32)cs, (u32)flags); Aren't ip and cs just 16? flags is 32 though. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] More i82801dx_lpc fixups again
Ok, lets try this again. More fixups for i82801dx_lpc.c code including, fixing i82801dx_power_options() so CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL works, and rewrite HPET code so it is more along the lines of how the Linux Kernel does it. Build and boot tested. Signed-off-by: Joseph Smith j...@settoplinux.org -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] More i82801dx_lpc fixups again
Ok, lets try this again.
More fixups for i82801dx_lpc.c code including, fixing
i82801dx_power_options() so CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
works, and rewrite HPET code so it is more along the lines of how the
Linux Kernel does it. Build and boot tested.
Signed-off-by: Joseph Smith j...@settoplinux.org
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
Index: src/southbridge/intel/i82801dx/i82801dx_lpc.c
===
--- src/southbridge/intel/i82801dx/i82801dx_lpc.c (revision 5255)
+++ src/southbridge/intel/i82801dx/i82801dx_lpc.c (working copy)
@@ -64,7 +64,6 @@
if (reg32 != (1 25))
die(APIC Error\n);
- /* TODO: From i82801ca, needed/useful on other ICH? */
*ioapic_index = 3; /* Select Boot Configuration register. */
*ioapic_data = 1; /* Use Processor System Bus to deliver interrupts. */
}
@@ -91,37 +90,85 @@
pci_write_config8(dev, PIRQF_ROUT, config-pirqf_routing);
pci_write_config8(dev, PIRQG_ROUT, config-pirqg_routing);
pci_write_config8(dev, PIRQH_ROUT, config-pirqh_routing);
-
}
static void i82801dx_power_options(device_t dev)
{
- u8 byte;
- int pwr_on = -1;
+ u8 reg8;
+ u16 reg16, pmbase;
+ u32 reg32;
+ const char *state;
+
+ int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
int nmi_option;
- /* power after power fail */
- /* FIXME this doesn't work! */
/* Which state do we want to goto after g3 (power restored)?
* 0 == S0 Full On
* 1 == S5 Soft Off
+ *
+ * If the option is not existent (Laptops), use MAINBOARD_POWER_ON.
*/
- pci_write_config8(dev, GEN_PMCON_3, pwr_on ? 0 : 1);
- printk_info(Set power %s if power fails\n, pwr_on ? on : off);
+ if (get_option(pwr_on, power_on_after_fail) 0)
+ pwr_on = MAINBOARD_POWER_ON;
+ reg8 = pci_read_config8(dev, GEN_PMCON_3);
+ reg8 = 0xfe;
+ switch (pwr_on) {
+ case MAINBOARD_POWER_OFF:
+ reg8 |= 1;
+ state = off;
+ break;
+ case MAINBOARD_POWER_ON:
+ reg8 = ~1;
+ state = on;
+ break;
+ case MAINBOARD_POWER_KEEP:
+ reg8 = ~1;
+ state = state keep;
+ break;
+ default:
+ state = undefined;
+ }
+
+ reg8 = ~(1 3); /* minimum asssertion is 1 to 2 RTCCLK */
+
+ pci_write_config8(dev, GEN_PMCON_3, reg8);
+ printk_info(Set power %s after power failure.\n, state);
+
/* Set up NMI on errors. */
- byte = inb(0x61);
- byte = ~(1 3); /* IOCHK# NMI Enable */
- byte = ~(1 2); /* PCI SERR# Enable */
- outb(byte, 0x61);
- byte = inb(0x70);
+ reg8 = inb(0x61);
+ reg8 = 0x0f; /* Higher Nibble must be 0 */
+ reg8 = ~(1 3); /* IOCHK# NMI Enable */
+ // reg8 = ~(1 2); /* PCI SERR# Enable */
+ reg8 |= (1 2); /* PCI SERR# Disable for now */
+ outb(reg8, 0x61);
+ reg8 = inb(0x70);
nmi_option = NMI_OFF;
get_option(nmi_option, nmi);
if (nmi_option) {
- byte = ~(1 7); /* Set NMI. */
- outb(byte, 0x70);
+ printk_info (NMI sources enabled.\n);
+ reg8 = ~(1 7); /* Set NMI. */
+ } else {
+ printk_info (NMI sources disabled.\n);
+ reg8 |= ( 1 7); /* Disable NMI. */
}
+ outb(reg8, 0x70);
+
+ /* Set SMI# rate down and enable CPU_SLP# */
+ reg16 = pci_read_config16(dev, GEN_PMCON_1);
+ reg16 = ~(3 0); // SMI# rate 1 minute
+ reg16 |= (1 5); // CPUSLP_EN Desktop only
+ pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+ pmbase = pci_read_config16(dev, 0x40) 0xfffe;
+
+ /* Set up power management block and determine sleep mode */
+ reg32 = inl(pmbase + 0x04); // PM1_CNT
+
+ reg32 = ~(7 10); // SLP_TYP
+ reg32 |= (1 0); // SCI_EN
+ outl(reg32, pmbase + 0x04);
}
static void gpio_init(device_t dev)
@@ -182,23 +229,36 @@
*/
static void enable_hpet(struct device *dev)
{
- u32 reg32;
- u32 code = (0 0x3);
+ u32 reg32, hpet, val;
+ /* Set HPET base address and enable it */
+ printk_debug(Enabling HPET at 0x%x\n, HPET_ADDR);
reg32 = pci_read_config32(dev, GEN_CNTL);
- reg32 |= (1 17); /* Enable HPET. */
/*
- * Bits [16:15] Memory Address Range
- * 00 FED0_h - FED0_03FFh
- * 01 FED0_1000h - FED0_13FFh
- * 10 FED0_2000h - FED0_23FFh
- * 11 FED0_3000h - FED0_33FFh
+ * Bit 17 is HPET enable bit.
+ * Bit 16:15 control the HPET base address.
*/
reg32 = ~(3 15); /* Clear it */
- reg32 |= (code 15);
+
+ hpet = HPET_ADDR 12;
+ hpet = 0x3;
+
+ reg32 |= (hpet 15);
+ reg32 |= (1 17); /* Enable HPET. */
pci_write_config32(dev, GEN_CNTL, reg32);
- printk_debug(Enabling HPET @0x%x\n, HPET_ADDR | (code 12));
+ /* Check to see whether it took */
+ reg32 = pci_read_config32(dev, GEN_CNTL);
+ val = reg32 15;
+ val = 0x7;
+
+ if ((val 0x4) (hpet == (val 0x3))) {
+ printk_debug(HPET enabled at 0x%x\n, HPET_ADDR);
+ } else {
+ printk_err(HPET was not enabled correctly\n);
+ reg32 = ~(1 17); /* Clear Enable */
+ pci_write_config32(dev, GEN_CNTL, reg32);
+ }
}
static void lpc_init(struct device *dev)
Index: src/southbridge/intel/i82801dx/i82801dx.h
===
--- src/southbridge/intel/i82801dx/i82801dx.h (revision 5255)
+++
[coreboot] [commit] r5256 - in trunk/src/southbridge/amd: rs780 sb600
Author: zbao Date: Thu Mar 18 06:57:32 2010 New Revision: 5256 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5256 Log: trivial. Delelte double blank line. Signed-off-by: Zheng Bao zheng@amd.com Acked-by: Zheng Bao zheng@amd.com Modified: trunk/src/southbridge/amd/rs780/rs780_cmn.c trunk/src/southbridge/amd/sb600/Kconfig Modified: trunk/src/southbridge/amd/rs780/rs780_cmn.c == --- trunk/src/southbridge/amd/rs780/rs780_cmn.c Wed Mar 17 23:44:39 2010 (r5255) +++ trunk/src/southbridge/amd/rs780/rs780_cmn.c Thu Mar 18 06:57:32 2010 (r5256) @@ -350,4 +350,3 @@ pci_write_config32(nb_dev, 0x90, uma_memory_base); //nbmc_write_index(nb_dev, 0x1e, uma_memory_base); } - Modified: trunk/src/southbridge/amd/sb600/Kconfig == --- trunk/src/southbridge/amd/sb600/Kconfig Wed Mar 17 23:44:39 2010 (r5255) +++ trunk/src/southbridge/amd/sb600/Kconfig Thu Mar 18 06:57:32 2010 (r5256) @@ -20,4 +20,3 @@ config SOUTHBRIDGE_AMD_SB600 bool select IOAPIC - -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
