Re: [coreboot] Newbie to coreboot with a 845G chipset
A.Haq Abbad wrote: So you advice me to install coreboot on it? I wouldn't. You will brick the board. the motherboard is not mentioned on the website, but the chipset is! That doesn't help. Unless you want to spend some time (ranging from a few weeks to a few months) on developing support for your mainboard I would strongly recommend looking for another, known working, board to try out coreboot on. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Newbie to coreboot with a 845G chipset
On 4/14/10 8:08 AM, Peter Stuge wrote: A.Haq Abbad wrote: So you advice me to install coreboot on it? I wouldn't. You will brick the board. the motherboard is not mentioned on the website, but the chipset is! That doesn't help. Unless you want to spend some time (ranging from a few weeks to a few months) on developing support for your mainboard I would strongly recommend looking for another, known working, board to try out coreboot on. Also, the chipset is not supported. Merely the southbridge is. The trickier part, the northbridge, is missing. Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Newbie to coreboot with a 845G chipset
no, what i want to tell you is that seabios may support DOS/Xp, but others not. be mention that there is always risk to flash the bios. On Wed, Apr 14, 2010 at 3:51 AM, A.Haq Abbad haq...@gmail.com wrote: So you advice me to install coreboot on it? the motherboard is not mentioned on the website, but the chipset is! Thanks. On Tue, Apr 13, 2010 at 6:44 PM, Qing Pei Wang wangqing...@gmail.comwrote: if you want to try xp/DOS, Seabios would be the only choice. and it is unnecessary to use kernel as payload(as a matter of fact, i doubt if it can be taken as payload). i think filo will be the easiest payload as the same. On Tue, Apr 13, 2010 at 10:52 PM, A.Haq Abbad haq...@gmail.com wrote: Hi All Intel® 845G chipset Southbridge 82801 P4 2.4GHz From Compaq Evo D310 DT (Custom Mobo, P4B266-VMX) Any recomemendations? Which payload to choose? I want to start with a basic one, will be using Linux mostly, but I do want to try XP and DOS perhaps. SeaBios seems good, but on the Wiki, it only mentions coreboot v3, and not 4! I hope it's a typo. I don't think I can use a Linux kernel as a payload, as the chip only has 512KB. How risky is it to render the PC useless? Note that the BIOS chip is soldered into the Mobo :\ and I doubt I'd be bothered to buy a new one and solder it. Time to complete the whole thing? If too long, I'll do it on the weekend. Thanks. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Wang Qing Pei MSN:wangqing...@hotmail.com msn%3awangqing...@hotmail.com Gmail:wangqing...@gmail.com gmail%3awangqing...@gmail.com Phone:86+13426369984 -- Wang Qing Pei MSN:wangqing...@hotmail.com msn%3awangqing...@hotmail.com Gmail:wangqing...@gmail.com gmail%3awangqing...@gmail.com Phone:86+13426369984 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [RFC] ACPI for ASUS P2B/P2B-LS (Intel 440BX/82371EB)
On 4/14/10 5:54 AM, Keith Hui wrote: irq 9: nobody cared (try booting with the irqpoll option) This is caused by setting fadt-sci_int without an irqoverride source in the MADT. current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, MP_IRQ_TRIGGER_LEVEL | MP_IRQ_POLARITY_HIGH); Generally your fadt looks a bit off, still: +fadt-sci_int = 9; // APM_CNT This is not APM control but the sci interrupt +fadt-smi_cmd = 0; This should be APM_CNT +fadt-acpi_enable = 0xa1; // ACPI_ENABLE +fadt-acpi_disable = 0xa0; // ACPI_DISABLE These two should be zero unless you have an SMM handler +fadt-s4bios_req = 0x0; +fadt-pstate_cnt = 0x0; With SMM it should look like this, assuming the APM_CNT port is 0xb2 on the 82371 too. (It is on the ICHx chips) #define APM_CNT 0xb2 #define CST_CONTROL 0x85 #define PST_CONTROL 0x80 #define ACPI_DISABLE 0x1e #define ACPI_ENABLE 0xe1 fadt-sci_int = 0x9; fadt-smi_cmd = APM_CNT; fadt-acpi_enable = ACPI_ENABLE; fadt-acpi_disable = ACPI_DISABLE; fadt-s4bios_req = 0x0; fadt-pstate_cnt = PST_CONTROL; ... fadt-cst_cnt = CST_CONTROL; HTH, Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] EP80579 reference platform
On 4/14/10 4:18 AM, Dustin Harrison wrote:
I've put several print_info statements in romstage.c and narrowed it
down to the following line in i3100_early_lpc.c:
pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 7));
Further debug shows that in general I can not read a value and then
use the value. If I just perfrom a read operation it executes the
instruction and contiues. But if I do a read and try to use a
print_info_hexXX function it just hangs.
Can you try this patch please?
Index: src/southbridge/intel/i3100/i3100_early_lpc.c
===
--- src/southbridge/intel/i3100/i3100_early_lpc.c(revision 5413)
+++ src/southbridge/intel/i3100/i3100_early_lpc.c(working copy)
@@ -34,13 +34,14 @@
{
device_t dev = PCI_DEV(0x0, 0x1f, 0x0);
-/* Temporarily enable the ACPI I/O range at 0x4000 */
-pci_write_config32(dev, 0x40, 0x4000 | (1 0));
-pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 7));
+#define ABASE 0x400
+/* Temporarily enable the ACPI I/O range at ABASE */
+pci_write_config32(dev, 0x40, ABASE | (1 0));
+pci_write_config8(dev, 0x44, (1 7));
/* Halt the TCO timer, preventing SMI and automatic reboot */
-outw(inw(0x4068) | (1 11), 0x4068);
+outw(inw(ABASE + 0x68) | (1 11), ABASE + 0x68);
/* Disable the ACPI I/O range */
-pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) ~(1
7));
+pci_write_config8(dev, 0x44, 0);
}
Any ideas on what to try next? Is there a recommended toolchain?
Yes, you can compile it with
$ cd coreboot/util/crossgcc
$ sh buildgcc
coreboot will automatically pick it up. You might have to delete
coreboot/.xcompile in order to have coreboot pick it up.
Stefan
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5423 - in trunk/src: arch/i386 cpu/intel/car cpu/intel/model_6bx cpu/intel/socket_mFCBGA479 cpu/x86/car mainboard/rca/rm4100 mainboard/thomson/ip1000 mainboard/tyan/s2735 northbri
Author: stepan Date: Wed Apr 14 09:47:07 2010 New Revision: 5423 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5423 Log: move cpu/x86/car to cpu/intel/car as previously discussed on the mailing list. this patch also slightly changes it so we have a single cache_as_ram.inc which requires no help from cache_as_ram_post.c and cache_as_ram_disable.c (or worse, a lot of cruft hacked right into romstage.c like on tyan s2735) Now all CAR code except the AMD Opteron/Athlon64 CAR code follows the new simpler scheme. I'll gladly leave src/cpu/amd/car to someone else ;-) Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Added: trunk/src/cpu/intel/car/ - copied from r5413, trunk/src/cpu/x86/car/ Deleted: trunk/src/cpu/intel/car/cache_as_ram_post.c trunk/src/cpu/intel/model_6bx/cache_as_ram_disable.c trunk/src/cpu/x86/car/ Modified: trunk/src/arch/i386/Makefile.inc trunk/src/cpu/intel/car/cache_as_ram.inc trunk/src/cpu/intel/socket_mFCBGA479/Makefile.inc trunk/src/mainboard/rca/rm4100/romstage.c trunk/src/mainboard/thomson/ip1000/romstage.c trunk/src/mainboard/tyan/s2735/romstage.c trunk/src/northbridge/via/vx800/examples/romstage.c Modified: trunk/src/arch/i386/Makefile.inc == --- trunk/src/arch/i386/Makefile.incTue Apr 13 23:31:42 2010(r5422) +++ trunk/src/arch/i386/Makefile.incWed Apr 14 09:47:07 2010(r5423) @@ -127,7 +127,7 @@ # FIXME move to CPU_INTEL_SOCKET_MPGA604 # ifeq ($(CONFIG_BOARD_TYAN_S2735),y) -crt0s += $(src)/cpu/x86/car/cache_as_ram.inc +crt0s += $(src)/cpu/intel/car/cache_as_ram.inc endif ifeq ($(CONFIG_LLSHELL),y) Modified: trunk/src/cpu/intel/car/cache_as_ram.inc == --- trunk/src/cpu/x86/car/cache_as_ram.inc Tue Apr 13 01:12:15 2010 (r5413) +++ trunk/src/cpu/intel/car/cache_as_ram.incWed Apr 14 09:47:07 2010 (r5423) @@ -126,6 +126,19 @@ wrmsr jmp clear_fixed_var_mtrr + +fixed_mtrr_msr: + .long 0x250, 0x258, 0x259 + .long 0x268, 0x269, 0x26A + .long 0x26B, 0x26C, 0x26D + .long 0x26E, 0x26F +var_mtrr_msr: + .long 0x200, 0x201, 0x202, 0x203 + .long 0x204, 0x205, 0x206, 0x207 + .long 0x208, 0x209, 0x20A, 0x20B + .long 0x20C, 0x20D, 0x20E, 0x20F + .long 0x000 /* NULL, end of table */ + clear_fixed_var_mtrr_out: /* 0x06 is the WB IO type for a given 4k segment. @@ -289,48 +302,118 @@ /* We need to set ebp ? No need */ movl%esp, %ebp pushl %eax /* bist */ - callstage1_main - /* We will not go back */ + callmain -fixed_mtrr_msr: - .long 0x250, 0x258, 0x259 - .long 0x268, 0x269, 0x26A - .long 0x26B, 0x26C, 0x26D - .long 0x26E, 0x26F -var_mtrr_msr: - .long 0x200, 0x201, 0x202, 0x203 - .long 0x204, 0x205, 0x206, 0x207 - .long 0x208, 0x209, 0x20A, 0x20B - .long 0x20C, 0x20D, 0x20E, 0x20F - .long 0x000 /* NULL, end of table */ + /* + FIXME : backup stack in CACHE_AS_RAM into mmx and sse and after we get STACK up, we restore that. + It is only needed if we want to go back + */ + +/* We don't need cache as ram for now on */ +/* disable cache */ + movl%cr0, %eax + orl$(0x130),%eax + movl%eax, %cr0 + +/* clear sth */ + movl$0x269, %ecx /* fix4k_c8000*/ + xorl%edx, %edx + xorl%eax, %eax + wrmsr - .align 0x1000 - .code16 -.global LogicalAP_SIPI -LogicalAP_SIPI: - // cr0 register is shared among the logical processors; - // so clear CD NW bits so that the BSP's cr0 register - // controls the cache behavior - // Note: The cache behavior is determined by OR result - // of the cr0 registers of the logical processors +#if CONFIG_DCACHE_RAM_SIZE 0x8000 + movl$0x268, %ecx /* fix4k_c*/ + wrmsr +#endif - movl%cr0, %eax - andl$0x9FFF, %eax - movl%eax, %cr0 +/* Set the default memory type and disable fixed and enable variable MTRRs */ + movl$0x2ff, %ecx +// movl$MTRRdefType_MSR, %ecx + xorl%edx, %edx +/* Enable Variable and Disable Fixed MTRRs */ + movl$0x0800, %eax + wrmsr - finit +#if defined(CLEAR_FIRST_1M_RAM) +/* enable caching for first 1M using variable mtrr */ + movl$0x200, %ecx + xorl%edx, %edx + movl $(0 | 1), %eax +// movl $(0 | MTRR_TYPE_WRCOMB), %eax + wrmsr - // Set the semaphore to indicate the Logical AP is done - // with CAR specific initialization - movl$0x250, %ecx - movl$0x06, %eax -
[coreboot] build service results for r5423
Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 5423 to the coreboot repository. This caused the following changes: Change Log: move cpu/x86/car to cpu/intel/car as previously discussed on the mailing list. this patch also slightly changes it so we have a single cache_as_ram.inc which requires no help from cache_as_ram_post.c and cache_as_ram_disable.c (or worse, a lot of cruft hacked right into romstage.c like on tyan s2735) Now all CAR code except the AMD Opteron/Athlon64 CAR code follows the new simpler scheme. I'll gladly leave src/cpu/amd/car to someone else ;-) Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Build Log: Compilation of digitallogic:adl855pc has been broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5423device=adl855pcvendor=digitallogicnum=2 If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Newbie to coreboot with a 845G chipset
Ohh, I thought it was going to be an easy ride, but I'll wait for AMD 785/750 support, as others are very old! Thanks every one. On Wed, Apr 14, 2010 at 7:08 AM, Peter Stuge pe...@stuge.se wrote: A.Haq Abbad wrote: So you advice me to install coreboot on it? I wouldn't. You will brick the board. the motherboard is not mentioned on the website, but the chipset is! That doesn't help. Unless you want to spend some time (ranging from a few weeks to a few months) on developing support for your mainboard I would strongly recommend looking for another, known working, board to try out coreboot on. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5424 - in trunk/src: mainboard/digitallogic/adl855pc northbridge/intel/i855
Author: stepan
Date: Wed Apr 14 11:04:31 2010
New Revision: 5424
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5424
Log:
fix digitallogic adl855pc compilation (and clean up the warnings while at it)
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/mainboard/digitallogic/adl855pc/romstage.c
trunk/src/northbridge/intel/i855/debug.c
trunk/src/northbridge/intel/i855/raminit.c
trunk/src/northbridge/intel/i855/raminit.h
Modified: trunk/src/mainboard/digitallogic/adl855pc/romstage.c
==
--- trunk/src/mainboard/digitallogic/adl855pc/romstage.cWed Apr 14
09:47:07 2010(r5423)
+++ trunk/src/mainboard/digitallogic/adl855pc/romstage.cWed Apr 14
11:04:31 2010(r5424)
@@ -3,12 +3,10 @@
#include arch/io.h
#include device/pnp_def.h
#include arch/romcc_io.h
-#if 0
-#include arch/smp/lapic.h
-#endif
#include arch/hlt.h
//#include option_table.h
#include stdlib.h
+#include pc80/udelay_io.c
#include pc80/mc146818rtc_early.c
#include pc80/serial.c
#include console/console.c
@@ -16,13 +14,6 @@
#include southbridge/intel/i82801dx/i82801dx.h
#include southbridge/intel/i82801dx/i82801dx_early_smbus.c
#include northbridge/intel/i855/raminit.h
-
-#if 0
-#include cpu/p6/apic_timer.c
-#include lib/delay.c
-#endif
-
-#include cpu/x86/lapic/boot_cpu.c
#include northbridge/intel/i855/debug.c
#include superio/winbond/w83627hf/w83627hf_early_serial.c
#include cpu/x86/mtrr/earlymtrr.c
@@ -30,24 +21,6 @@
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-static void hard_reset(void)
-{
-outb(0x0e, 0x0cf9);
-}
-
-static void memreset_setup(void)
-{
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-/* nothing to do */
-}
-
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
@@ -57,10 +30,7 @@
#include northbridge/intel/i855/reset_test.c
#include lib/generic_sdram.c
-
-#include cpu/intel/model_6bx/cache_as_ram_disable.c
-
-void real_main(unsigned long bist)
+void main(unsigned long bist)
{
static const struct mem_controller memctrl[] = {
{
@@ -93,7 +63,6 @@
dump_spd_registers(memctrl[0]);
dump_smbus_registers();
#endif
- memreset_setup();
sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
Modified: trunk/src/northbridge/intel/i855/debug.c
==
--- trunk/src/northbridge/intel/i855/debug.cWed Apr 14 09:47:07 2010
(r5423)
+++ trunk/src/northbridge/intel/i855/debug.cWed Apr 14 11:04:31 2010
(r5424)
@@ -18,24 +18,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-/*
- * generic K8 debug code, used by mainboard specific romstage.c
- *
- */
-#if 1
-/*
-static void print_debug_pci_dev(unsigned dev)
-{
- print_debug(PCI: );
- print_debug_hex8((dev 16) 0xff);
- print_debug_char(':');
- print_debug_hex8((dev 11) 0x1f);
- print_debug_char('.');
- print_debug_hex8((dev 8) 7);
-}
-*/
-
-
static void print_debug_pci_dev(unsigned dev)
{
print_debug(PCI: );
@@ -46,7 +28,7 @@
print_debug_hex8((dev 12) 0x07);
}
-static void print_pci_devices(void)
+static inline void print_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
@@ -85,7 +67,7 @@
}
}
-static void dump_pci_devices(void)
+static inline void dump_pci_devices(void)
{
device_t dev;
for(dev = PCI_DEV(0, 0, 0);
@@ -102,7 +84,7 @@
}
}
-static void dump_spd_registers(const struct mem_controller *ctrl)
+static inline void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
print_debug(\n);
@@ -134,37 +116,10 @@
}
print_debug(\n);
}
-#if 0
- device = ctrl-channel1[i];
- if (device) {
- int j;
- print_debug(dimm: );
- print_debug_hex8(i);
- print_debug(.1: );
- print_debug_hex8(device);
- for(j = 0; j 256; j++) {
- int status;
- unsigned char byte;
- if ((j 0xf) == 0) {
- print_debug(\n);
- print_debug_hex8(j);
- print_debug(: );
- }
- status = smbus_read_byte(device, j);
- if (status 0) {
-
[coreboot] build service results for r5424
Dear coreboot readers! This is the automatic build system of coreboot. The developer stepan checked in revision 5424 to the coreboot repository. This caused the following changes: Change Log: fix digitallogic adl855pc compilation (and clean up the warnings while at it) Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Build Log: Compilation of digitallogic:adl855pc has been fixed If something broke during this checkin please be a pain in stepan's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Dualbios etc
Vadim Girlin wrote: OK, but I sent some disassembled logs - the bios is proprietary, isn't? Anyway all I want is to say that i don't want to violate any rules. Any info that I sent was supposed to help the developers. If some of my posts violates some rules - I'm sorry. So probably you should say on coreboot page that we shouldn't send any disassembled dumps if this could make a problem for you. Well it is not a problem for me, IANAL maybe nextime use pastebin ;) Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5425 - in trunk/src: cpu/amd/model_lx drivers/ati/ragexl mainboard/bcom/winnetp680 mainboard/digitallogic/msm800sev mainboard/hp/dl145_g3 mainboard/kontron/kt690 mainboard/pcengin
Author: stepan
Date: Wed Apr 14 12:12:23 2010
New Revision: 5425
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5425
Log:
zero warnings days. Down to under 600 different warnings
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/cpu/amd/model_lx/vsmsetup.c
trunk/src/drivers/ati/ragexl/xlinit.c
trunk/src/mainboard/bcom/winnetp680/romstage.c
trunk/src/mainboard/digitallogic/msm800sev/romstage.c
trunk/src/mainboard/hp/dl145_g3/mptable.c
trunk/src/mainboard/kontron/kt690/mainboard.c
trunk/src/mainboard/pcengines/alix1c/romstage.c
trunk/src/mainboard/technexion/tim8690/mainboard.c
trunk/src/northbridge/amd/amdht/h3finit.c
trunk/src/northbridge/amd/gx2/northbridge.c
trunk/src/northbridge/via/vt8623/northbridge.c
trunk/src/northbridge/via/vx800/dev_init.c
trunk/src/northbridge/via/vx800/dram_init.c
trunk/src/northbridge/via/vx800/dram_init.h
trunk/src/northbridge/via/vx800/drdy_bl.c
trunk/src/northbridge/via/vx800/freq_setting.c
trunk/src/northbridge/via/vx800/raminit.c
trunk/src/northbridge/via/vx800/rank_map.c
trunk/src/northbridge/via/vx800/uma_ram_setting.c
trunk/src/northbridge/via/vx800/vgabios.c
trunk/src/southbridge/amd/cs5535/cs5535_early_setup.c
trunk/src/southbridge/amd/cs5536/cs5536_smbus2.h
trunk/src/southbridge/intel/i82801ex/i82801ex_early_smbus.c
trunk/src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
trunk/src/southbridge/nvidia/mcp55/mcp55_fadt.c
trunk/src/southbridge/via/vt8235/vt8235.c
Modified: trunk/src/cpu/amd/model_lx/vsmsetup.c
==
--- trunk/src/cpu/amd/model_lx/vsmsetup.c Wed Apr 14 11:04:31 2010
(r5424)
+++ trunk/src/cpu/amd/model_lx/vsmsetup.c Wed Apr 14 12:12:23 2010
(r5425)
@@ -268,10 +268,7 @@
void do_vsmbios(void)
{
- device_t dev;
- unsigned long busdevfn;
unsigned char *buf;
- unsigned int size = SMM_SIZE * 1024;
int i;
printk(BIOS_ERR, do_vsmbios\n);
Modified: trunk/src/drivers/ati/ragexl/xlinit.c
==
--- trunk/src/drivers/ati/ragexl/xlinit.c Wed Apr 14 11:04:31 2010
(r5424)
+++ trunk/src/drivers/ati/ragexl/xlinit.c Wed Apr 14 12:12:23 2010
(r5425)
@@ -489,7 +489,10 @@
int j;
u16 type;
u8 rev;
- const char *chipname = NULL, *xtal;
+ const char *chipname = NULL;
+#if CONFIG_CONSOLE_BTEXT
+ const char *xtal;
+#endif
int pll, mclk, xclk;
#if CONFIG_CONSOLE_BTEXT==1
Modified: trunk/src/mainboard/bcom/winnetp680/romstage.c
==
--- trunk/src/mainboard/bcom/winnetp680/romstage.c Wed Apr 14 11:04:31
2010(r5424)
+++ trunk/src/mainboard/bcom/winnetp680/romstage.c Wed Apr 14 12:12:23
2010(r5425)
@@ -39,10 +39,6 @@
#include superio/winbond/w83697hf/w83697hf_early_serial.c
#define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1)
-static void memreset_setup(void)
-{
-}
-
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
@@ -53,8 +49,6 @@
static void enable_mainboard_devices(void)
{
device_t dev;
- u8 reg;
-
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_VIA,
PCI_DEVICE_ID_VIA_VT8237R_LPC), 0);
if (dev == PCI_DEV_INVALID)
die(Southbridge not found!!!\n);
@@ -89,9 +83,6 @@
void main(unsigned long bist)
{
- unsigned long x;
- device_t dev;
-
/* Enable multifunction for northbridge. */
pci_write_config8(ctrl.d0f0, 0x4f, 0x01);
Modified: trunk/src/mainboard/digitallogic/msm800sev/romstage.c
==
--- trunk/src/mainboard/digitallogic/msm800sev/romstage.c Wed Apr 14
11:04:31 2010(r5424)
+++ trunk/src/mainboard/digitallogic/msm800sev/romstage.c Wed Apr 14
12:12:23 2010(r5425)
@@ -51,7 +51,6 @@
msr.hi = 0x2000;
msr.lo = 0xfff00;
wrmsr(MSR_GLIU1 + 0x20, msr);
-
}
static void mb_gpio_init(void)
@@ -61,7 +60,6 @@
void cache_as_ram_main(void)
{
- extern void RestartCAR();
post_code(0x01);
static const struct mem_controller memctrl [] = {
Modified: trunk/src/mainboard/hp/dl145_g3/mptable.c
==
--- trunk/src/mainboard/hp/dl145_g3/mptable.c Wed Apr 14 11:04:31 2010
(r5424)
+++ trunk/src/mainboard/hp/dl145_g3/mptable.c Wed Apr 14 12:12:23 2010
(r5425)
@@ -50,8 +50,6 @@
static const char productid[12] = TREX;
struct mp_config_table *mc;
- unsigned char bus_num;
- int i;
struct mb_sysconf_t *m;
Re: [coreboot] Newbie to coreboot with a 845G chipset
AMD785G works, Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Newbie to coreboot with a 845G chipset
Hello, i845 is on my TODO list. Have patients, the goal is to have it done by the end of the year. By the way, this is some what a tricky chipset because it supports both SDRAM and/or DDR. -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5426 - in trunk/src: cpu/amd/mtrr cpu/x86/mtrr lib mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/serengeti_cheeta
Author: stepan
Date: Wed Apr 14 13:40:34 2010
New Revision: 5426
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5426
Log:
drop quite a lot of dead code that did nothing but produce warnings and make
the rest of the code unreadable.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Deleted:
trunk/src/cpu/amd/mtrr/amd_earlymtrr.c
Modified:
trunk/src/cpu/x86/mtrr/earlymtrr.c
trunk/src/lib/debug.c
trunk/src/mainboard/amd/dbm690t/romstage.c
trunk/src/mainboard/amd/mahogany/romstage.c
trunk/src/mainboard/amd/mahogany_fam10/romstage.c
trunk/src/mainboard/amd/pistachio/romstage.c
trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
trunk/src/mainboard/arima/hdama/romstage.c
trunk/src/mainboard/asrock/939a785gmh/romstage.c
trunk/src/mainboard/asus/a8n_e/romstage.c
trunk/src/mainboard/asus/a8v-e_se/romstage.c
trunk/src/mainboard/asus/m2v-mx_se/romstage.c
trunk/src/mainboard/broadcom/blast/romstage.c
trunk/src/mainboard/dell/s1850/romstage.c
trunk/src/mainboard/digitallogic/msm586seg/romstage.c
trunk/src/mainboard/gigabyte/ga_2761gxdk/romstage.c
trunk/src/mainboard/gigabyte/m57sli/romstage.c
trunk/src/mainboard/hp/dl145_g3/romstage.c
trunk/src/mainboard/ibm/e325/romstage.c
trunk/src/mainboard/ibm/e326/romstage.c
trunk/src/mainboard/intel/eagleheights/romstage.c
trunk/src/mainboard/intel/jarrell/romstage.c
trunk/src/mainboard/intel/mtarvon/romstage.c
trunk/src/mainboard/intel/truxton/romstage.c
trunk/src/mainboard/intel/xe7501devkit/reset.c
trunk/src/mainboard/intel/xe7501devkit/romstage.c
trunk/src/mainboard/iwill/dk8_htx/romstage.c
trunk/src/mainboard/iwill/dk8s2/romstage.c
trunk/src/mainboard/iwill/dk8x/romstage.c
trunk/src/mainboard/kontron/kt690/romstage.c
trunk/src/mainboard/msi/ms7135/irq_tables.c
trunk/src/mainboard/msi/ms7135/romstage.c
trunk/src/mainboard/msi/ms7260/romstage.c
trunk/src/mainboard/msi/ms9185/romstage.c
trunk/src/mainboard/msi/ms9282/romstage.c
trunk/src/mainboard/msi/ms9652_fam10/romstage.c
trunk/src/mainboard/newisys/khepri/romstage.c
trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
trunk/src/mainboard/sunw/ultra40/romstage.c
trunk/src/mainboard/supermicro/h8dme/romstage.c
trunk/src/mainboard/supermicro/h8dmr/romstage.c
trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
trunk/src/mainboard/supermicro/x6dai_g/romstage.c
trunk/src/mainboard/supermicro/x6dhe_g/romstage.c
trunk/src/mainboard/supermicro/x6dhe_g2/romstage.c
trunk/src/mainboard/supermicro/x6dhr_ig/romstage.c
trunk/src/mainboard/supermicro/x6dhr_ig2/romstage.c
trunk/src/mainboard/technexion/tim5690/romstage.c
trunk/src/mainboard/technexion/tim8690/romstage.c
trunk/src/mainboard/tyan/s2735/romstage.c
trunk/src/mainboard/tyan/s2850/romstage.c
trunk/src/mainboard/tyan/s2875/romstage.c
trunk/src/mainboard/tyan/s2880/romstage.c
trunk/src/mainboard/tyan/s2881/romstage.c
trunk/src/mainboard/tyan/s2882/romstage.c
trunk/src/mainboard/tyan/s2885/romstage.c
trunk/src/mainboard/tyan/s2891/romstage.c
trunk/src/mainboard/tyan/s2892/romstage.c
trunk/src/mainboard/tyan/s2912/romstage.c
trunk/src/mainboard/tyan/s2912_fam10/romstage.c
trunk/src/mainboard/tyan/s4880/romstage.c
trunk/src/mainboard/tyan/s4882/romstage.c
trunk/src/mainboard/via/epia-cn/romstage.c
trunk/src/mainboard/via/epia-m/romstage.c
trunk/src/mainboard/via/epia-n/romstage.c
trunk/src/northbridge/intel/e7501/raminit.c
trunk/src/northbridge/intel/i3100/raminit.c
trunk/src/northbridge/via/vt8623/northbridge.c
Modified: trunk/src/cpu/x86/mtrr/earlymtrr.c
==
--- trunk/src/cpu/x86/mtrr/earlymtrr.c Wed Apr 14 12:12:23 2010(r5425)
+++ trunk/src/cpu/x86/mtrr/earlymtrr.c Wed Apr 14 13:40:34 2010(r5426)
@@ -2,6 +2,7 @@
#define EARLYMTRR_C
#include cpu/x86/cache.h
#include cpu/x86/mtrr.h
+#include cpu/amd/mtrr.h
#include cpu/x86/msr.h
#if 0
Modified: trunk/src/lib/debug.c
==
--- trunk/src/lib/debug.c Wed Apr 14 12:12:23 2010(r5425)
+++ trunk/src/lib/debug.c Wed Apr 14 13:40:34 2010(r5426)
@@ -33,7 +33,7 @@
{
device_t dev;
for (dev = PCI_DEV(0, 0, 0);
-dev = PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
+dev = PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
u32 id;
id = pci_read_config32(dev, PCI_VENDOR_ID);
if (((id 0x) == 0x) || ((id 0x) == 0x)
Modified: trunk/src/mainboard/amd/dbm690t/romstage.c
==
--- trunk/src/mainboard/amd/dbm690t/romstage.c Wed Apr 14 12:12:23 2010
[coreboot] [PATCH] epia-en first attempt
A first attempt at getting epia-en to work irq table will be total crap. Mostly (all) stolen from other epia's Signed-off-by: Jasper Aorangi jasper.mackenzie_pleasespamemIlovefreegivawaysenlargementsetc_gmail.com epia-en-first-attempt.patch Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [commit] r5426 - in trunk/src: cpu/amd/mtrr cpu/x86/mtrr lib mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/serengeti_ch
On Wed, Apr 14, 2010 at 5:40 AM, repository service s...@coreboot.orgwrote:
Author: stepan
Date: Wed Apr 14 13:40:34 2010
New Revision: 5426
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5426
Log:
drop quite a lot of dead code that did nothing but produce warnings and
make
the rest of the code unreadable.
Modified: trunk/src/lib/debug.c
==
--- trunk/src/lib/debug.c Wed Apr 14 12:12:23 2010(r5425)
+++ trunk/src/lib/debug.c Wed Apr 14 13:40:34 2010(r5426)
@@ -33,7 +33,7 @@
{
device_t dev;
for (dev = PCI_DEV(0, 0, 0);
-dev = PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
+dev = PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
It looks like this slipped in. I thought it hangs some boards to probe PCI
busses that aren't there.
Thanks,
Myles
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [commit] r5426 - in trunk/src: cpu/amd/mtrr cpu/x86/mtrr lib mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/serengeti_ch
On Wed, Apr 14, 2010 at 6:50 AM, Stefan Reinauer ste...@coresystems.dewrote:
On 4/14/10 2:36 PM, Myles Watson wrote:
Modified: trunk/src/lib/debug.c
==
--- trunk/src/lib/debug.c Wed Apr 14 12:12:23 2010(r5425)
+++ trunk/src/lib/debug.c Wed Apr 14 13:40:34 2010(r5426)
@@ -33,7 +33,7 @@
{
device_t dev;
for (dev = PCI_DEV(0, 0, 0);
-dev = PCI_DEV(0, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
+dev = PCI_DEV(0xff, 0x1f, 0x7); dev += PCI_DEV(0, 0, 1)) {
It looks like this slipped in. I thought it hangs some boards to probe
PCI busses that aren't there.
Hm,... do you happen to know which ones?
http://www.coreboot.org/pipermail/coreboot/2009-October/053330.html
I think this is what I was remembering, so it may not be relevant.
There are about 15 places where this function is defined.
Thanks,
Myles
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5427 - trunk/util/xcompile
Author: oxygene
Date: Wed Apr 14 16:35:40 2010
New Revision: 5427
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5427
Log:
Rename variable to not confuse gcc on mingw
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
Modified:
trunk/util/xcompile/xcompile
Modified: trunk/util/xcompile/xcompile
==
--- trunk/util/xcompile/xcompileWed Apr 14 13:40:34 2010(r5426)
+++ trunk/util/xcompile/xcompileWed Apr 14 16:35:40 2010(r5427)
@@ -35,8 +35,8 @@
done
GCCPREFIX=invalid
-TMP=`mktemp /tmp/temp. 2/dev/null || echo /tmp/temp.78gOIUGz`
-touch $TMP
+TMPFILE=`mktemp /tmp/temp. 2/dev/null || echo /tmp/temp.78gOIUGz`
+touch $TMPFILE
# This should be a loop over all supported architectures
TARCH=i386
@@ -45,9 +45,9 @@
if ! which ${gccprefixes}as 2/dev/null /dev/null; then
continue
fi
- rm -f ${TMP}.o
- if ${gccprefixes}as -o ${TMP}.o ${TMP}; then
- TYPE=`${gccprefixes}objdump -p ${TMP}.o`
+ rm -f ${TMPFILE}.o
+ if ${gccprefixes}as -o ${TMPFILE}.o ${TMPFILE}; then
+ TYPE=`${gccprefixes}objdump -p ${TMPFILE}.o`
if [ ${TYPE##* } == elf${TWIDTH}-${TARCH} ]; then
GCCPREFIX=$gccprefixes
ASFLAGS=
@@ -56,8 +56,8 @@
break
fi
fi
- if ${gccprefixes}as --32 -o ${TMP}.o ${TMP}; then
- TYPE=`${gccprefixes}objdump -p ${TMP}.o`
+ if ${gccprefixes}as --32 -o ${TMPFILE}.o ${TMPFILE}; then
+ TYPE=`${gccprefixes}objdump -p ${TMPFILE}.o`
if [ ${TYPE##* } == elf${TWIDTH}-${TARCH} ]; then
GCCPREFIX=$gccprefixes
ASFLAGS=--32
@@ -67,7 +67,7 @@
fi
fi
done
-rm -f $TMP ${TMP}.o
+rm -f $TMPFILE ${TMPFILE}.o
if [ $GCCPREFIX = invalid ]; then
echo '$(error no suitable gcc found)'
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5428 - trunk/util/sconfig
Author: oxygene Date: Wed Apr 14 16:41:30 2010 New Revision: 5428 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5428 Log: sconfig should return success when it's successful Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Patrick Georgi patrick.geo...@coresystems.de Modified: trunk/util/sconfig/sconfig.tab.c_shipped trunk/util/sconfig/sconfig.y Modified: trunk/util/sconfig/sconfig.tab.c_shipped == --- trunk/util/sconfig/sconfig.tab.c_shippedWed Apr 14 16:35:40 2010 (r5427) +++ trunk/util/sconfig/sconfig.tab.c_shippedWed Apr 14 16:41:30 2010 (r5428) @@ -2057,5 +2057,6 @@ walk_device_tree(staticc, root, pass1, NULL); fclose(staticc); + return 0; } Modified: trunk/util/sconfig/sconfig.y == --- trunk/util/sconfig/sconfig.yWed Apr 14 16:35:40 2010(r5427) +++ trunk/util/sconfig/sconfig.yWed Apr 14 16:41:30 2010(r5428) @@ -497,4 +497,5 @@ walk_device_tree(staticc, root, pass1, NULL); fclose(staticc); + return 0; } -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [RFC] ACPI for ASUS P2B/P2B-LS (Intel 440BX/82371EB)
Hi Keith, * I also replicated the content of the PIIX4 function 3 config space after booting with vendor BIOS, as below: 00:04.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 02) 00: 86 80 13 71 03 00 80 02 02 00 80 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 e4 00 00 00 00 00 20 1e 30 00 01 00 00 00 00 50: 00 58 19 00 c0 c8 3b 02 37 40 40 03 00 00 00 00 60: 90 02 e7 00 00 00 00 10 04 e4 11 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 01 e8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 30 0f 00 00 00 00 00 00 Please do not blindly copy the BIOS settings. You dont need to use the old way to monitor device activity because ACPI is about OS driven power management and not HW driven powermanagement. One exception is 0x90-0x91 which has the SMBus host base address. I kept it as 0x0f00. * Idwer is trying to build ACPI 4.0 (!) tables. Since P2B-LS is shipped when ACPI was still at 1.0, that's what I did. For booting XP, even ACPI 2.0 compliance is sufficient. This is a summary of what happens: * I can no longer get POST codes on the PCI bus. POST codes still appear on the ISA bus. Glad I picked a POST card that works on both buses. * Power off does not work. The last POST code to show before complete kernel shutdown and hard drive spinning down is 0xF5. I think you are trying to setup the SMI trap using the BIOS values you supplied. * I don't how how to enter soft suspend in Linux (silly me -_-! ), so I have not tested it. You need to tweak memory controller for that. And other CPU stuff. * the sensor appears on ISA bus port 0x290, just like vendor BIOS. * My SB AWE64 ISA card still got initialized and driver loaded, but no sound. In fact ALSA can't even do I/O to the card. That apparently is because PIIX4 needs to be configured to forward certain I/O port ranges to ISA, and some of those port ranges can be further configured. This would require detecting in runtime what ISA cards are installed, what are they, and what I/O port ranges they would use. Where in the source tree should I place such code? Southbridge? I think the subtractive decoding is default, hence all IO which is not decoded by any PCI device should be send to ISA automatically. Maybe you need to trigger EIO/ISA bit too. Thanks, Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5429 - in trunk/src: mainboard/supermicro/h8qme_fam10 northbridge/amd/amdfam10
Author: stepan
Date: Wed Apr 14 17:44:21 2010
New Revision: 5429
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5429
Log:
udelay_tsc does not exist in the whole tree.
Neither does quadcore.h (anymore)
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
trunk/src/northbridge/amd/amdfam10/debug.c
trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
Modified: trunk/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c
==
--- trunk/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c Wed Apr 14
16:41:30 2010(r5428)
+++ trunk/src/mainboard/supermicro/h8qme_fam10/get_bus_conf.c Wed Apr 14
17:44:21 2010(r5429)
@@ -25,7 +25,7 @@
#include string.h
#include stdint.h
#if CONFIG_LOGICAL_CPUS==1
-#include cpu/amd/quadcore.h
+#include cpu/amd/multicore.h
#endif
#include cpu/amd/amdfam10_sysconf.h
Modified: trunk/src/northbridge/amd/amdfam10/debug.c
==
--- trunk/src/northbridge/amd/amdfam10/debug.c Wed Apr 14 16:41:30 2010
(r5428)
+++ trunk/src/northbridge/amd/amdfam10/debug.c Wed Apr 14 17:44:21 2010
(r5429)
@@ -23,8 +23,6 @@
#include amdfam10_pci.c
-static void udelay_tsc(u32 us);
-
static inline void print_debug_addr(const char *str, void *val)
{
#if CACHE_AS_RAM_ADDRESS_DEBUG == 1
@@ -296,7 +294,7 @@
{
int i;
- udelay_tsc(2000);
+ udelay(2000);
printk(BIOS_DEBUG, %04x:\n, port);
for(i=0;i256;i++) {
u8 val;
Modified: trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c
==
--- trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c Wed Apr 14
16:41:30 2010(r5428)
+++ trunk/src/northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c Wed Apr 14
17:44:21 2010(r5429)
@@ -42,7 +42,7 @@
/* give the NB a break, many CPUs spinning on one bit makes a
* lot of traffic and time is not too important to APs.
*/
- udelay_tsc(1000);
+ udelay(1000);
if(get_htic_bit(0, 9)) return;
}
}
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5430 - trunk/src/northbridge/amd/amdmct/mct
Author: stepan Date: Wed Apr 14 17:45:02 2010 New Revision: 5430 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5430 Log: HWHoleSz must be u32... Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Modified: trunk/src/northbridge/amd/amdmct/mct/mctndi_d.c Modified: trunk/src/northbridge/amd/amdmct/mct/mctndi_d.c == --- trunk/src/northbridge/amd/amdmct/mct/mctndi_d.c Wed Apr 14 17:44:21 2010(r5429) +++ trunk/src/northbridge/amd/amdmct/mct/mctndi_d.c Wed Apr 14 17:45:02 2010(r5430) @@ -33,7 +33,7 @@ u8 DoIntlv; u8 _NdIntCap; u8 _SWHole; - u8 HWHoleSz; + u32 HWHoleSz; u32 DramHoleAddrReg; u32 HoleBase; u32 dev0; -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] clarify and -
Signed-off-by: Stefan Reinauer ste...@coresystems.de Index: src/northbridge/amd/gx2/chipsetinit.c === --- src/northbridge/amd/gx2/chipsetinit.c (revision 5425) +++ src/northbridge/amd/gx2/chipsetinit.c (working copy) @@ -275,7 +275,7 @@ if ((msr.lo0xff) == 0x11) return; - totalmem = sizeram() 20 - 1; + totalmem = (sizeram() 20) - 1; totalmem = 12; totalmem = ~totalmem; totalmem = 0xf; -- coresystems GmbH • Brahmsstr. 16 • D-79104 Freiburg i. Br. Tel.: +49 761 7668825 • Fax: +49 761 7664613 Email: i...@coresystems.de • http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg • HRB 7656 Geschäftsführer: Stefan Reinauer • Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ASUS M2V-TVM....
Rudolf Marek wrote: 00K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 00after enable_fid_change No other messages after this? What was wrong last time? No more messages,but if I comment the fid/vid related code out(maybe due to my Sempron 3000 lack of CnQ??),every thing looks fine except the coreboot does not excute payload(SeaBIOS) correctly m2v-tvm.txt.bz2 Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] clarify and -
Index: src/northbridge/amd/gx2/chipsetinit.c === --- src/northbridge/amd/gx2/chipsetinit.c (revision 5425) +++ src/northbridge/amd/gx2/chipsetinit.c (working copy) @@ -275,7 +275,7 @@ if ((msr.lo0xff) == 0x11) return; - totalmem = sizeram() 20 - 1; + totalmem = (sizeram() 20) - 1; I agree that it looks right, but it changes the answer, since subtraction has a higher precedence than shift. I don't have a board to test which is right. Did you check v3? Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5432 - in trunk/src: arch/i386/include/arch mainboard/amd/dbm690t mainboard/amd/mahogany mainboard/amd/mahogany_fam10 mainboard/amd/pistachio mainboard/amd/serengeti_cheetah mainb
Author: myles
Date: Wed Apr 14 18:50:16 2010
New Revision: 5432
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5432
Log:
Remove few more warnings and some dead code.
Signed-off-by: Myles Watson myle...@gmail.com
Acked-by: Myles Watson myle...@gmail.com
Modified:
trunk/src/arch/i386/include/arch/acpi.h
trunk/src/mainboard/amd/dbm690t/acpi_tables.c
trunk/src/mainboard/amd/mahogany/acpi_tables.c
trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c
trunk/src/mainboard/amd/pistachio/acpi_tables.c
trunk/src/mainboard/amd/serengeti_cheetah/acpi_tables.c
trunk/src/mainboard/amd/serengeti_cheetah_fam10/acpi_tables.c
trunk/src/mainboard/asrock/939a785gmh/acpi_tables.c
trunk/src/mainboard/intel/eagleheights/acpi_tables.c
trunk/src/mainboard/iwill/dk8_htx/acpi_tables.c
trunk/src/mainboard/kontron/kt690/acpi_tables.c
trunk/src/mainboard/technexion/tim5690/acpi_tables.c
trunk/src/mainboard/technexion/tim8690/acpi_tables.c
trunk/src/mainboard/via/epia-m/acpi_tables.c
trunk/src/mainboard/via/epia-m700/wakeup.c
trunk/src/northbridge/amd/amdfam10/amdfam10_acpi.c
trunk/src/northbridge/amd/amdk8/amdk8_acpi.c
trunk/src/northbridge/via/vx800/examples/romstage.c
trunk/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
Modified: trunk/src/arch/i386/include/arch/acpi.h
==
--- trunk/src/arch/i386/include/arch/acpi.h Wed Apr 14 18:39:30 2010
(r5431)
+++ trunk/src/arch/i386/include/arch/acpi.h Wed Apr 14 18:50:16 2010
(r5432)
@@ -365,6 +365,9 @@
void acpi_create_ssdt_generator(acpi_header_t *ssdt, const char *oem_table_id);
void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs, void *dsdt);
+void update_ssdt(void* ssdt);
+void update_ssdtx(void* ssdtx, int i);
+
/* These can be used by the target port */
u8 acpi_checksum(u8 *table, u32 length);
Modified: trunk/src/mainboard/amd/dbm690t/acpi_tables.c
==
--- trunk/src/mainboard/amd/dbm690t/acpi_tables.c Wed Apr 14 18:39:30
2010(r5431)
+++ trunk/src/mainboard/amd/dbm690t/acpi_tables.c Wed Apr 14 18:50:16
2010(r5432)
@@ -92,28 +92,6 @@
return current;
}
-static void update_ssdtx(void *ssdtx, int i)
-{
- uint8_t *PCI;
- uint8_t *HCIN;
- uint8_t *UID;
-
- PCI = ssdtx + 0x32;
- HCIN = ssdtx + 0x39;
- UID = ssdtx + 0x40;
-
- if (i 7) {
- *PCI = (uint8_t) ('4' + i - 1);
- } else {
- *PCI = (uint8_t) ('A' + i - 1 - 6);
- }
- *HCIN = (uint8_t) i;
- *UID = (uint8_t) (i + 3);
-
- /* FIXME: need to update the GSI id in the ssdtx too */
-
-}
-
unsigned long acpi_fill_ssdt_generator(unsigned long current, const char
*oem_table_id) {
k8acpi_write_vars();
amd_model_fxx_generate_powernow(pm_base + 8, 6, 1);
Modified: trunk/src/mainboard/amd/mahogany/acpi_tables.c
==
--- trunk/src/mainboard/amd/mahogany/acpi_tables.c Wed Apr 14 18:39:30
2010(r5431)
+++ trunk/src/mainboard/amd/mahogany/acpi_tables.c Wed Apr 14 18:50:16
2010(r5432)
@@ -99,32 +99,6 @@
return current;
}
-
-
-#if CONFIG_ACPI_SSDTX_NUM = 1
-static void update_ssdtx(void *ssdtx, int i)
-{
- u8 *PCI;
- u8 *HCIN;
- u8 *UID;
-
- PCI = ssdtx + 0x32;
- HCIN = ssdtx + 0x39;
- UID = ssdtx + 0x40;
-
- if (i 7) {
- *PCI = (u8) ('4' + i - 1);
- } else {
- *PCI = (u8) ('A' + i - 1 - 6);
- }
- *HCIN = (u8) i;
- *UID = (u8) (i + 3);
-
- /* FIXME: need to update the GSI id in the ssdtx too */
-
-}
-#endif
-
unsigned long acpi_fill_ssdt_generator(unsigned long current, const char
*oem_table_id) {
k8acpi_write_vars();
amd_model_fxx_generate_powernow(pm_base + 8, 6, 1);
Modified: trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.c
==
--- trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.cWed Apr 14
18:39:30 2010(r5431)
+++ trunk/src/mainboard/amd/mahogany_fam10/acpi_tables.cWed Apr 14
18:50:16 2010(r5432)
@@ -89,34 +89,6 @@
return current;
}
-
-extern void update_ssdt(void *ssdt);
-
-/* not tested yet. */
-#if CONFIG_ACPI_SSDTX_NUM = 1
-static void update_ssdtx(void *ssdtx, int i)
-{
- u8 *PCI;
- u8 *HCIN;
- u8 *UID;
-
- PCI = ssdtx + 0x32;
- HCIN = ssdtx + 0x39;
- UID = ssdtx + 0x40;
-
- if (i 7) {
- *PCI = (u8) ('4' + i - 1);
- } else {
- *PCI = (u8) ('A' + i - 1 - 6);
- }
- *HCIN = (u8) i;
- *UID = (u8) (i + 3);
-
- /* FIXME: need to update the GSI id in the ssdtx too */
-
-}
-#endif
-
[coreboot] [commit] r5433 - in trunk/src: mainboard/via/epia-m700 northbridge/intel/e7501 northbridge/via/cn400 northbridge/via/vx800
Author: stepan
Date: Wed Apr 14 19:11:47 2010
New Revision: 5433
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5433
Log:
drop setup_ics code that was blatantly copied from cx700 and
was mainboard specific and unused there already.
some more minor warning fixes.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/mainboard/via/epia-m700/romstage.c
trunk/src/northbridge/intel/e7501/debug.c
trunk/src/northbridge/via/cn400/vgabios.c
trunk/src/northbridge/via/vx800/rank_map.c
trunk/src/northbridge/via/vx800/vgabios.c
trunk/src/northbridge/via/vx800/vx800_early_smbus.c
Modified: trunk/src/mainboard/via/epia-m700/romstage.c
==
--- trunk/src/mainboard/via/epia-m700/romstage.cWed Apr 14 18:50:16
2010(r5432)
+++ trunk/src/mainboard/via/epia-m700/romstage.cWed Apr 14 19:11:47
2010(r5433)
@@ -24,6 +24,7 @@
#define RAMINIT_SYSINFO 1
#define CACHE_AS_RAM_ADDRESS_DEBUG 0
+#define PAYLOAD_IS_SEABIOS 0
#include stdint.h
#include device/pci_def.h
@@ -85,11 +86,6 @@
return result;
}
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
/* All content of this function came from the cx700 port of coreboot. */
static void enable_mainboard_devices(void)
{
@@ -273,7 +269,8 @@
#define gCom1Base 0x3f8
#define gCom2Base 0x2f8
-void EmbedComInit(void)
+#if 0
+static void EmbedComInit(void)
{
u8 ByteVal;
u16 ComBase;
@@ -379,6 +376,7 @@
/* SOutput(Embedded COM output\n); */
/* while(1); */
}
+#endif
/* cache_as_ram.inc jumps to here. */
void main(unsigned long bist)
Modified: trunk/src/northbridge/intel/e7501/debug.c
==
--- trunk/src/northbridge/intel/e7501/debug.c Wed Apr 14 18:50:16 2010
(r5432)
+++ trunk/src/northbridge/intel/e7501/debug.c Wed Apr 14 19:11:47 2010
(r5433)
@@ -140,7 +140,7 @@
int j;
#if CONFIG_USE_PRINTK_IN_CAR
printk(BIOS_DEBUG, dimm: %02x.1: %02x, i, device);
-#else`
+#else
print_debug(dimm: );
print_debug_hex8(i);
print_debug(.1: );
Modified: trunk/src/northbridge/via/cn400/vgabios.c
==
--- trunk/src/northbridge/via/cn400/vgabios.c Wed Apr 14 18:50:16 2010
(r5432)
+++ trunk/src/northbridge/via/cn400/vgabios.c Wed Apr 14 19:11:47 2010
(r5433)
@@ -336,7 +336,7 @@
{
device_t dev;
unsigned long busdevfn;
- unsigned int rom = 0;
+ u32 rom;
unsigned char *buf;
unsigned int size = 64*1024;
int i;
@@ -357,7 +357,7 @@
/* declare rom address here - keep any config data out of the way
* of core LXB stuff */
-rom = cbfs_load_optionrom(dev-vendor, dev-device, 0);
+rom = (u32)cbfs_load_optionrom(dev-vendor, dev-device, 0);
pci_write_config32(dev, PCI_ROM_ADDRESS, rom|1);
printk(BIOS_DEBUG, VGA BIOS ROM base address: %x\n, rom);
Modified: trunk/src/northbridge/via/vx800/rank_map.c
==
--- trunk/src/northbridge/via/vx800/rank_map.c Wed Apr 14 18:50:16 2010
(r5432)
+++ trunk/src/northbridge/via/vx800/rank_map.c Wed Apr 14 19:11:47 2010
(r5433)
@@ -17,12 +17,6 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-extern void DRAMSetVRNum(DRAM_SYS_ATTR * DramAttr,
-u8 PhyRank, u8 VirRank, BOOLEAN Enable);
-
-extern void SetEndingAddr(DRAM_SYS_ATTR * DramAttr, u8 VirRank,//
Ending address register number indicator (INDEX
- INT8 Value); // (value) add or subtract value to
this and after banks
-
void DRAMClearEndingAddress(DRAM_SYS_ATTR * DramAttr);
void DRAMSizingEachRank(DRAM_SYS_ATTR * DramAttr);
Modified: trunk/src/northbridge/via/vx800/vgabios.c
==
--- trunk/src/northbridge/via/vx800/vgabios.c Wed Apr 14 18:50:16 2010
(r5432)
+++ trunk/src/northbridge/via/vx800/vgabios.c Wed Apr 14 19:11:47 2010
(r5433)
@@ -158,6 +158,7 @@
/* put the stack at the end of page zero.
* that way we can easily share it between
real and protected,
* since the 16-bit ESP at segment 0 will
work for any case.
+*/
/* Setup a stack */
mov $0x0, %ax \n
[coreboot] [commit] r5434 - trunk/src/northbridge/amd/amdmct/mct
Author: stepan
Date: Wed Apr 14 19:18:34 2010
New Revision: 5434
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5434
Log:
fix a case where the fam10 code would overwrite parts of a struct.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/northbridge/amd/amdmct/mct/mctardk3.c
trunk/src/northbridge/amd/amdmct/mct/mctardk4.c
Modified: trunk/src/northbridge/amd/amdmct/mct/mctardk3.c
==
--- trunk/src/northbridge/amd/amdmct/mct/mctardk3.c Wed Apr 14 19:11:47
2010(r5433)
+++ trunk/src/northbridge/amd/amdmct/mct/mctardk3.c Wed Apr 14 19:18:34
2010(r5434)
@@ -18,7 +18,7 @@
*/
-static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload,
+static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,
u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL);
Modified: trunk/src/northbridge/amd/amdmct/mct/mctardk4.c
==
--- trunk/src/northbridge/amd/amdmct/mct/mctardk4.c Wed Apr 14 19:11:47
2010(r5433)
+++ trunk/src/northbridge/amd/amdmct/mct/mctardk4.c Wed Apr 14 19:18:34
2010(r5434)
@@ -18,9 +18,9 @@
*/
-static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload,
+static void Get_ChannelPS_Cfg0_D(u8 MAAdimms, u8 Speed, u8 MAAload,
u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL,
- u32 *CMDmode);
+ u8 *CMDmode);
void mctGet_PS_Cfg_D(struct MCTStatStruc *pMCTstat,
@@ -102,7 +102,7 @@
static void Get_ChannelPS_Cfg0_D( u8 MAAdimms, u8 Speed, u8 MAAload,
u8 DATAAload, u32 *AddrTmgCTL, u32 *ODC_CTL,
- u32 *CMDmode)
+ u8 *CMDmode)
{
u8 *p;
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5435 - in trunk/src: . arch/i386 mainboard/kontron/kt690 mainboard/msi/ms9282 mainboard/nvidia/l1_2pvv mainboard/supermicro/h8dme mainboard/supermicro/h8dmr mainboard/supermicro/h
Author: stepan
Date: Wed Apr 14 20:59:42 2010
New Revision: 5435
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5435
Log:
zero warning days. Move RAMTOP and RAMBASE together.
Signed-off-by: Stefan Reinauer ste...@coresystems.de
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/Kconfig
trunk/src/arch/i386/Kconfig
trunk/src/mainboard/kontron/kt690/mainboard.c
trunk/src/mainboard/msi/ms9282/romstage.c
trunk/src/mainboard/nvidia/l1_2pvv/romstage.c
trunk/src/mainboard/supermicro/h8dme/romstage.c
trunk/src/mainboard/supermicro/h8dmr/romstage.c
trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
trunk/src/mainboard/technexion/tim5690/Kconfig
trunk/src/mainboard/technexion/tim5690/mainboard.c
trunk/src/mainboard/technexion/tim8690/mainboard.c
trunk/src/mainboard/tyan/s2735/reset.c
trunk/src/mainboard/tyan/s2735/romstage.c
trunk/src/mainboard/tyan/s2912/romstage.c
trunk/src/mainboard/tyan/s2912_fam10/romstage.c
trunk/src/mainboard/via/epia-cn/romstage.c
trunk/src/southbridge/via/vt8237r/vt8237r_usb.c
Modified: trunk/src/Kconfig
==
--- trunk/src/Kconfig Wed Apr 14 19:18:34 2010(r5434)
+++ trunk/src/Kconfig Wed Apr 14 20:59:42 2010(r5435)
@@ -152,10 +152,6 @@
bool
default n
-config RAMTOP
- hex
- default 0x20
-
config ATI_RAGE_XL
bool
Modified: trunk/src/arch/i386/Kconfig
==
--- trunk/src/arch/i386/Kconfig Wed Apr 14 19:18:34 2010(r5434)
+++ trunk/src/arch/i386/Kconfig Wed Apr 14 20:59:42 2010(r5435)
@@ -30,6 +30,10 @@
hex
default 0x10
+config RAMTOP
+ hex
+ default 0x20
+
config STACK_SIZE
hex
default 0x8000
Modified: trunk/src/mainboard/kontron/kt690/mainboard.c
==
--- trunk/src/mainboard/kontron/kt690/mainboard.c Wed Apr 14 19:18:34
2010(r5434)
+++ trunk/src/mainboard/kontron/kt690/mainboard.c Wed Apr 14 20:59:42
2010(r5435)
@@ -22,10 +22,11 @@
#include device/pci.h
#include arch/io.h
#include boot/coreboot_tables.h
+#include arch/coreboot_tables.h
#include cpu/x86/msr.h
#include cpu/amd/mtrr.h
#include device/pci_def.h
-#include ../southbridge/amd/sb600/sb600.h
+#include southbridge/amd/sb600/sb600.h
#include chip.h
#define ADT7461_ADDRESS 0x4C
@@ -185,11 +186,8 @@
* enable the dedicated function in dbm690t board.
* This function called early than rs690_enable.
*/
-void kt690_enable(device_t dev)
+static void kt690_enable(device_t dev)
{
- struct mainboard_config *mainboard =
- (struct mainboard_config *)dev-chip_info;
-
printk(BIOS_INFO, Mainboard KT690 Enable. dev=0x%p\n, dev);
#if (CONFIG_GFXUMA == 1)
@@ -229,8 +227,8 @@
/* TODO: TOP_MEM2 */
#else
- uma_memory_size = 0x800;/* 128M recommended UMA */
- uma_memory_base = 0x3800; /* 1GB system memory supposed */
+ uma_memory_size = 0x0;
+ uma_memory_base = 0x0;
#endif
enable_onboard_nic();
@@ -249,6 +247,7 @@
lb_add_memory_range(mem, LB_MEM_RESERVED,
uma_memory_base, uma_memory_size);
#endif
+ return 0;
}
struct chip_operations mainboard_ops = {
Modified: trunk/src/mainboard/msi/ms9282/romstage.c
==
--- trunk/src/mainboard/msi/ms9282/romstage.c Wed Apr 14 19:18:34 2010
(r5434)
+++ trunk/src/mainboard/msi/ms9282/romstage.c Wed Apr 14 20:59:42 2010
(r5435)
@@ -135,8 +135,6 @@
static void sio_setup(void)
{
-
-unsigned value;
uint32_t dword;
uint8_t byte;
@@ -147,7 +145,6 @@
dword = pci_read_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0);
dword |= (10);
pci_write_config32(PCI_DEV(0, MCP55_DEVN_BASE+1 , 0), 0xa0, dword);
-
}
//CPU 1 mem is on SMBUS_HUB channel 2, and CPU 2 mem is on channel 1.
@@ -156,19 +153,19 @@
void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
{
- static const uint16_t spd_addr [] = {
- RC0|(0xa3)|0, RC0|(0xa3)|2, RC0|(0xa3)|4,
RC0|(0xa3)|6,
- RC0|(0xa3)|1, RC0|(0xa3)|3, RC0|(0xa3)|5,
RC0|(0xa3)|7,
-#if CONFIG_MAX_PHYSICAL_CPUS 1
- RC1|(0xa3)|0, RC1|(0xa3)|2, RC1|(0xa3)|4,
RC1|(0xa3)|6,
- RC1|(0xa3)|1, RC1|(0xa3)|3, RC1|(0xa3)|5,
RC1|(0xa3)|7,
-#endif
- };
+ static const uint16_t spd_addr[] = {
+ // Node 0
+ RC0|(0xa3)|0, RC0|(0xa3)|2, RC0|(0xa3)|4,
RC0|(0xa3)|6,
+
Re: [coreboot] [PATCH] clarify and -
On 4/14/10 6:44 PM, Myles Watson wrote: Index: src/northbridge/amd/gx2/chipsetinit.c === --- src/northbridge/amd/gx2/chipsetinit.c (revision 5425) +++ src/northbridge/amd/gx2/chipsetinit.c (working copy) @@ -275,7 +275,7 @@ if ((msr.lo0xff) == 0x11) return; - totalmem = sizeram() 20 - 1; + totalmem = (sizeram() 20) - 1; I agree that it looks right, but it changes the answer, since subtraction has a higher precedence than shift. I don't have a board to test which is right. Did you check v3? Nor do I... v3 never supported gx2. -- coresystems GmbH . Brahmsstr. 16 . D-79104 Freiburg i. Br. Tel.: +49 761 7668825 . Fax: +49 761 7664613 Email: i...@coresystems.de . http://www.coresystems.de/ Registergericht: Amtsgericht Freiburg . HRB 7656 Geschäftsführer: Stefan Reinauer . Ust-IdNr.: DE245674866 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] clarify and -
On Wed, Apr 14, 2010 at 1:22 PM, Stefan Reinauer ste...@coresystems.dewrote: On 4/14/10 6:44 PM, Myles Watson wrote: Index: src/northbridge/amd/gx2/chipsetinit.c === --- src/northbridge/amd/gx2/chipsetinit.c (revision 5425) +++ src/northbridge/amd/gx2/chipsetinit.c (working copy) @@ -275,7 +275,7 @@ if ((msr.lo0xff) == 0x11) return; - totalmem = sizeram() 20 - 1; + totalmem = (sizeram() 20) - 1; I agree that it looks right, but it changes the answer, since subtraction has a higher precedence than shift. I don't have a board to test which is right. Did you check v3? Nor do I... v3 never supported gx2. I guess this should be the patch, then: - totalmem = sizeram() 20 - 1; + totalmem = sizeram() (20 - 1); Anyone with an OLPC board care to chime in? Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] clarify and -
On 14.04.2010 21:35, Myles Watson wrote: On Wed, Apr 14, 2010 at 1:22 PM, Stefan Reinauer ste...@coresystems.dewrote: On 4/14/10 6:44 PM, Myles Watson wrote: Index: src/northbridge/amd/gx2/chipsetinit.c === --- src/northbridge/amd/gx2/chipsetinit.c (revision 5425) +++ src/northbridge/amd/gx2/chipsetinit.c (working copy) @@ -275,7 +275,7 @@ if ((msr.lo0xff) == 0x11) return; - totalmem = sizeram() 20 - 1; + totalmem = (sizeram() 20) - 1; I agree that it looks right, but it changes the answer, since subtraction has a higher precedence than shift. I don't have a board to test which is right. Did you check v3? Nor do I... v3 never supported gx2. I guess this should be the patch, then: - totalmem = sizeram() 20 - 1; + totalmem = sizeram() (20 - 1); Anyone with an OLPC board care to chime in? I won't be able to test before April 20. If that's still to be tested by then, I'd appreciate a reminder. Regards, Carl-Daniel -- http://www.hailfinger.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] EP80579 reference platform
On 13/04/2010 11:56 PM, Stefan Reinauer wrote:
On 4/14/10 4:18 AM, Dustin Harrison wrote:
I've put several print_info statements in romstage.c and narrowed it
down to the following line in i3100_early_lpc.c:
pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1 7));
Further debug shows that in general I can not read a value and then
use the value. If I just perfrom a read operation it executes the
instruction and contiues. But if I do a read and try to use a
print_info_hexXX function it just hangs.
Can you try this patch please?
Hi Stefan,
I applied your patch and was able to reproduce the same results as
before -- I can move past the TCO initialization, but then I get stuck
the next time a variable is referenced. In the EP80579 case that is
spd_dump_registers:
void dump_spd_registers(void)
{
unsigned device;
device = SMBUS_MEM_DEVICE_START;
while(device = SMBUS_MEM_DEVICE_END) {
int status = 0;
int i;
print_debug(\n);
print_debug(dimm );
print_debug_hex8(device);
The print_debug_hex8(device) hangs now. I can re-create this behaviour
simply be doing any sort of read or variable assignment and then try to
use a print_XXX function on the data. For example if I change the above
function to the following:
Index: src/mainboard/intel/jarrell/debug.c
===
--- src/mainboard/intel/jarrell/debug.c (revision 5430)
+++ src/mainboard/intel/jarrell/debug.c (working copy)
@@ -275,12 +275,9 @@
while(device = SMBUS_MEM_DEVICE_END) {
int status = 0;
int i;
- print_debug(\n);
-print_debug(dimm );
- print_debug_hex8(device);
for(i = 0; (i 256) ; i++) {
- unsigned char byte;
+print_debug(here now.\n);
if ((i % 16) == 0) {
print_debug(\n);
print_debug_hex8(i);
I now get stuck on the for loop (I never see here now).
I have switched to using the coreboot toolchain and it doesn't seem to
make a difference.
These are the last few lines of assembly before the jump to the
print_debug_hex8(i) section:
0aaf: 66 0f 6e c7 movd %edi,%xmm0
0ab3: bc 00 00 00 00 mov$0x0,%esp
0ab8: e9 a8 05 00 00 jmp1065 L1496
1065 L1496:
1065: 66 0f 7e c7 movd %xmm0,%edi
1069: 81 fc 00 01 00 00 cmp$0x100,%esp
106f: 0f 8c 48 fa ff ff jl 0abd L1368
0abd L1368: /* At this point we are working on
print_debug_hex8(i) now */
0abd: bd 6a d0 ff ff mov$0xd06a,%ebp
I am also in the process of trying my BIOS in the truxton platform, but
it will take me a while to get things up and going. In the meantime I'm
out of ideas on how to narrow this down any further.
Cheers
Dustin
Index: src/southbridge/intel/i3100/i3100_early_lpc.c
===
--- src/southbridge/intel/i3100/i3100_early_lpc.c(revision 5413)
+++ src/southbridge/intel/i3100/i3100_early_lpc.c(working copy)
@@ -34,13 +34,14 @@
{
device_t dev = PCI_DEV(0x0, 0x1f, 0x0);
-/* Temporarily enable the ACPI I/O range at 0x4000 */
-pci_write_config32(dev, 0x40, 0x4000 | (1 0));
-pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) | (1
7));
+#define ABASE 0x400
+/* Temporarily enable the ACPI I/O range at ABASE */
+pci_write_config32(dev, 0x40, ABASE | (1 0));
+pci_write_config8(dev, 0x44, (1 7));
/* Halt the TCO timer, preventing SMI and automatic reboot */
-outw(inw(0x4068) | (1 11), 0x4068);
+outw(inw(ABASE + 0x68) | (1 11), ABASE + 0x68);
/* Disable the ACPI I/O range */
-pci_write_config32(dev, 0x44, pci_read_config32(dev, 0x44) ~(1
7));
+pci_write_config8(dev, 0x44, 0);
}
Any ideas on what to try next? Is there a recommended toolchain?
Yes, you can compile it with
$ cd coreboot/util/crossgcc
$ sh buildgcc
coreboot will automatically pick it up. You might have to delete
coreboot/.xcompile in order to have coreboot pick it up.
Stefan
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] clarify and -
On 4/14/10 9:35 PM, Myles Watson wrote: On Wed, Apr 14, 2010 at 1:22 PM, Stefan Reinauer ste...@coresystems.de mailto:ste...@coresystems.de wrote: On 4/14/10 6:44 PM, Myles Watson wrote: Index: src/northbridge/amd/gx2/chipsetinit.c === --- src/northbridge/amd/gx2/chipsetinit.c (revision 5425) +++ src/northbridge/amd/gx2/chipsetinit.c (working copy) @@ -275,7 +275,7 @@ if ((msr.lo0xff) == 0x11) return; - totalmem = sizeram() 20 - 1; + totalmem = (sizeram() 20) - 1; I agree that it looks right, but it changes the answer, since subtraction has a higher precedence than shift. I don't have a board to test which is right. Did you check v3? Nor do I... v3 never supported gx2. I guess this should be the patch, then: - totalmem = sizeram() 20 - 1; + totalmem = sizeram() (20 - 1); If we can't decide on the right fix we should leave the warning there as it keeps the question open until someone can answer it. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5436 - trunk/util/crossgcc
Author: oxygene
Date: Wed Apr 14 22:42:42 2010
New Revision: 5436
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5436
Log:
Update mingw source versions and allow parallel builds in buildgcc
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
Acked-by: Patrick Georgi patrick.geo...@coresystems.de
Modified:
trunk/util/crossgcc/buildgcc
Modified: trunk/util/crossgcc/buildgcc
==
--- trunk/util/crossgcc/buildgccWed Apr 14 20:59:42 2010(r5435)
+++ trunk/util/crossgcc/buildgccWed Apr 14 22:42:42 2010(r5436)
@@ -32,8 +32,8 @@
GCC_VERSION=4.4.2
BINUTILS_VERSION=2.20
GDB_VERSION=7.0
-W32API_VERSION=3.13
-MINGWRT_VERSION=3.16
+W32API_VERSION=3.14
+MINGWRT_VERSION=3.18
# archive locations
GMP_ARCHIVE=ftp://ftp.gmplib.org/pub/gmp-${GMP_VERSION}/gmp-${GMP_VERSION}.tar.bz2;
@@ -41,7 +41,7 @@
GCC_ARCHIVE=ftp://ftp.gwdg.de/pub/gnu/ftp/gnu/gcc/gcc-${GCC_VERSION}/gcc-core-${GCC_VERSION}.tar.bz2;
BINUTILS_ARCHIVE=http://ftp.gnu.org/gnu/binutils/binutils-${BINUTILS_VERSION}.tar.bz2;
GDB_ARCHIVE=http://ftp.gnu.org/gnu/gdb/gdb-${GDB_VERSION}.tar.bz2;
-W32API_ARCHIVE=http://downloads.sourceforge.net/project/mingw/MinGW%20API%20for%20MS-Windows/Current%20Release_%20w32api-${W32API_VERSION}/w32api-${W32API_VERSION}-mingw32-src.tar.gz;
+W32API_ARCHIVE=http://downloads.sourceforge.net/project/mingw/MinGW%20API%20for%20MS-Windows/w32api-${W32API_VERSION}/w32api-${W32API_VERSION}-mingw32-src.tar.gz;
MINGWRT_ARCHIVE=http://downloads.sourceforge.net/project/mingw/MinGW%20Runtime/mingwrt-${MINGWRT_VERSION}/mingwrt-${MINGWRT_VERSION}-mingw32-src.tar.gz;
GMP_DIR=gmp-${GMP_VERSION}
@@ -103,6 +103,7 @@
printf [-h|--help] print this help and exit\n
printf [-c|--clean] remove temporary files before
build\n
printf [-t|--savetemps] don't remove temporary files
after build\n
+ printf [-j|--jobs num] run num jobs in parallel in
make\n
printf [-p|--platform platform]target platform to build
cross compiler for\n
printf (defaults to $TARGETARCH)\n
printf [-d|--directory target dir] target directory to install
cross compiler to\n
@@ -140,11 +141,11 @@
getoptbrand=`getopt -V`
if [ ${getoptbrand:0:6} == getopt ]; then
# Detected GNU getopt that supports long options.
- args=`getopt -l
version,help,clean,directory:,platform:,destdir:,savetemps Vhcd:p:D:t -- $@`
+ args=`getopt -l
version,help,clean,directory:,platform:,jobs:,destdir:,savetemps Vhcd:p:j:D:t
-- $@`
eval set $args
else
# Detected non-GNU getopt
- args=`getopt Vhcd:p:D:t $*`
+ args=`getopt Vhcd:p:j:D:t $*`
set -- $args
fi
@@ -162,6 +163,7 @@
-d|--directory) shift; TARGETDIR=$1; shift;;
-p|--platform) shift; TARGETARCH=$1; shift;;
-D|--destdir) shift; DESTDIR=$1; shift;;
+ -j|--jobs) shift; JOBS=-j $1; shift;;
--) shift; break;;
-*) printf Invalid option\n\n; myhelp; exit 1;;
*) break;;
@@ -245,7 +247,7 @@
../${GMP_DIR}/configure --disable-shared --prefix=$TARGETDIR $OPTIONS \
|| touch .failed
- $MAKE || touch .failed
+ $MAKE $JOBS || touch .failed
$MAKE install DESTDIR=$DESTDIR || touch .failed
if [ ! -f .failed ]; then touch .success; fi
) build-gmp/crossgcc-build.log
@@ -272,7 +274,7 @@
../${MPFR_DIR}/configure --disable-shared --prefix=$TARGETDIR \
--infodir=$TARGETDIR/info \
--with-gmp=$DESTDIR$TARGETDIR CFLAGS=$HOSTCFLAGS || touch
.failed
- $MAKE || touch .failed
+ $MAKE $JOBS || touch .failed
$MAKE install DESTDIR=$DESTDIR || touch .failed
# work around build problem of libgmp.la
@@ -296,7 +298,7 @@
../binutils-${BINUTILS_VERSION}/configure --prefix=$TARGETDIR
--target=${TARGETARCH} \
--disable-werror --disable-nls \
CFLAGS=$HOSTCFLAGS || touch .failed
- $MAKE || touch .failed
+ $MAKE $JOBS || touch .failed
$MAKE install DESTDIR=$DESTDIR || touch .failed
if [ ! -f .failed ]; then touch .success; fi
) build-binutils/crossgcc-build.log
@@ -322,7 +324,7 @@
--disable-libssp --disable-bootstrap --disable-nls \
--with-gmp=$DESTDIR$TARGETDIR --with-mpfr=$DESTDIR$TARGETDIR \
|| touch .failed
- $MAKE CFLAGS_FOR_BUILD=$HOSTCFLAGS || touch .failed
+ $MAKE $JOBS CFLAGS_FOR_BUILD=$HOSTCFLAGS || touch .failed
$MAKE install DESTDIR=$DESTDIR || touch .failed
if [ ! -f .failed ]; then touch .success; fi
) build-gcc/crossgcc-build.log
@@ -340,7 +342,7 @@
rm -f .failed
[coreboot] [commit] r5437 - trunk
Author: oxygene Date: Wed Apr 14 22:47:45 2010 New Revision: 5437 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5437 Log: Quote test -f argument, so it doesn't fail on spaces. Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de Acked-by: Patrick Georgi patrick.geo...@coresystems.de Modified: trunk/Makefile Modified: trunk/Makefile == --- trunk/Makefile Wed Apr 14 22:42:42 2010(r5436) +++ trunk/Makefile Wed Apr 14 22:47:45 2010(r5437) @@ -295,7 +295,7 @@ printf /* build system definitions (autogenerated) */\n $(obj)/build.ht printf #ifndef __BUILD_H\n $(obj)/build.ht printf #define __BUILD_H\n\n $(obj)/build.ht - printf #define COREBOOT_VERSION \$(KERNELVERSION)-r$(shell if [ -d $(top)/.svn -a -f `which svnversion` ]; then svnversion $(top); else if [ -d $(top)/.git -a -f `which git` ]; then git --git-dir=/$(top)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)\\n $(obj)/build.ht + printf #define COREBOOT_VERSION \$(KERNELVERSION)-r$(shell if [ -d $(top)/.svn -a -f `which svnversion` ]; then svnversion $(top); else if [ -d $(top)/.git -a -f `which git` ]; then git --git-dir=/$(top)/.git log|grep git-svn-id|cut -f 2 -d@|cut -f 1 -d' '|sort -g|tail -1; fi; fi)\\n $(obj)/build.ht printf #define COREBOOT_EXTRA_VERSION \$(COREBOOT_EXTRA_VERSION)\\n $(obj)/build.ht printf #define COREBOOT_BUILD \`LANG= date`\\n $(obj)/build.ht printf \n $(obj)/build.ht -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] clarify and -
If we can't decide on the right fix we should leave the warning there as it keeps the question open until someone can answer it. I agree. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] warning days - m57sli/mcp55
On Tue, Apr 13, 2010 at 12:15:42AM +0200, Stefan Reinauer wrote:
Index: src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
===
--- src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c(revision 5411)
+++ src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c(working copy)
@@ -177,7 +177,7 @@
pci_write_config32(dev, 0xe4, dword);
// need to wait 100ms
- delayx(1000);
+ delayx(232);
}
it sounds a lot to do 0x8000 outb to wait 100us, but who knows...
I think it would be better to change the input type to something else
than uint8_t, supposedly unsigned as most other udelay functions.
That works, boot-tested.
Alternatively you could try if this works:
Index: src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
===
--- src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c (revision 5411)
+++ src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c (working copy)
@@ -131,15 +131,9 @@
}
-static void delayx(uint8_t value) {
-#if 1
- int i;
- for(i=0;i0x8000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
+#include pc80/udelay_io.c
+
static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx,
unsigned anactrl_io_base, unsigned pci_e_x)
{
uint32_t tgio_ctrl;
@@ -170,14 +164,14 @@
outl(tgio_ctrl, anactrl_io_base + 0xcc);
// wait 100us
- delayx(1);
+ udelay(100);
dword = pci_read_config32(dev, 0xe4);
dword = ~(0x3f0); // enable
pci_write_config32(dev, 0xe4, dword);
// need to wait 100ms
- delayx(1000);
+ udelay(100 * 1000);
}
static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
unsigned *devn, unsigned *io_base, unsigned *pci_e_x)
Hmm, that generates a conflict:
In file included from
src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c:143,
from src/mainboard/gigabyte/m57sli/romstage.c:133:
src/pc80/udelay_io.c:4: error: redefinition of 'udelay'
src/cpu/amd/model_fxx/apic_timer.c:19: note: previous definition of 'udelay'
was here
We do indeed have 2 different functions called udelay.
Ideas?
Index: src/mainboard/gigabyte/m57sli/fanctl.c
===
--- src/mainboard/gigabyte/m57sli/fanctl.c (revision 5411)
+++ src/mainboard/gigabyte/m57sli/fanctl.c (working copy)
@@ -71,6 +71,7 @@
/*
* Called from superio.c
*/
+extern void init_ec(uint16_t base);
void init_ec(uint16_t base)
{
int i;
init_ec() is the API between the superio drivers and the mainboard
drivers...
If this is a single hack, it's fine as it is.. If we're going to have an
API here, we should create a src/include/superio.h or some such
It's only used on this particular board. Myles expressed a preference for a
header file, so I moved the definition to fanctl.h, and I dropped the
'extern' as you suggested.
Index: src/northbridge/amd/amdk8/exit_from_self.c
===
--- src/northbridge/amd/amdk8/exit_from_self.c (revision 5411)
+++ src/northbridge/amd/amdk8/exit_from_self.c (working copy)
@@ -17,6 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301
USA
*/
+extern void exit_from_self(int controllers, const struct mem_controller
*ctrl,
+struct sys_info *sysinfo);
void exit_from_self(int controllers, const struct mem_controller *ctrl,
struct sys_info *sysinfo)
{
since this is a C file that is included in exactly one file,
raminit_f.c you could as well just mark the function static.
Done.
btw, for function prototypes the extern in not really needed. I keep
removing them from the tree, but if people think we should have them,
I'll try to be consistent and stop deleting them :-)
I'll not add any new ones then!
Updated patch attached. I see the ACPI warnings were already fixed in another
commit.
Thanks,
Ward.
--
Ward Vandewege w...@fsf.org
Free Software Foundation - Senior Systems Administrator
This fixes a number of warnings when building m57sli (and other boards with mcp55).
This patch is boot tested on m57sli.
Signed-off-by: Ward Vandewege w...@gnu.org
Index: src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
===
--- src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c (revision 5437)
+++ src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c (working copy)
@@ -131,7 +131,7 @@
}
-static void delayx(uint8_t value) {
+static void delayx(unsigned value) {
#if 1
int i;
for(i=0;i0x8000;i++) {
Index: src/mainboard/gigabyte/m57sli/fanctl.c
===
--- src/mainboard/gigabyte/m57sli/fanctl.c (revision 5437)
+++ src/mainboard/gigabyte/m57sli/fanctl.c (working copy)
@@ -1,5 +1,6 @@
#include arch/io.h
Re: [coreboot] [PATCH] warning days - m57sli/mcp55
Alternatively you could try if this works:
Index: src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c
===
--- src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c (revision 5411)
+++ src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c (working copy)
@@ -131,15 +131,9 @@
}
-static void delayx(uint8_t value) {
-#if 1
- int i;
- for(i=0;i0x8000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
+#include pc80/udelay_io.c
+
static void mcp55_early_pcie_setup(unsigned busnx, unsigned devnx,
unsigned anactrl_io_base, unsigned pci_e_x)
{
uint32_t tgio_ctrl;
@@ -170,14 +164,14 @@
outl(tgio_ctrl, anactrl_io_base + 0xcc);
// wait 100us
- delayx(1);
+ udelay(100);
dword = pci_read_config32(dev, 0xe4);
dword = ~(0x3f0); // enable
pci_write_config32(dev, 0xe4, dword);
// need to wait 100ms
- delayx(1000);
+ udelay(100 * 1000);
}
static void mcp55_early_setup(unsigned mcp55_num, unsigned *busn,
unsigned *devn, unsigned *io_base, unsigned *pci_e_x)
Hmm, that generates a conflict:
In file included from
src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c:143,
from src/mainboard/gigabyte/m57sli/romstage.c:133:
src/pc80/udelay_io.c:4: error: redefinition of 'udelay'
src/cpu/amd/model_fxx/apic_timer.c:19: note: previous definition of
'udelay'
was here
We do indeed have 2 different functions called udelay.
Ideas?
You could just call udelay without including pc80/udelay.c.
Index: src/mainboard/gigabyte/m57sli/fanctl.c
===
--- src/mainboard/gigabyte/m57sli/fanctl.c (revision 5411)
+++ src/mainboard/gigabyte/m57sli/fanctl.c (working copy)
@@ -71,6 +71,7 @@
/*
* Called from superio.c
*/
+extern void init_ec(uint16_t base);
void init_ec(uint16_t base)
{
int i;
init_ec() is the API between the superio drivers and the mainboard
drivers...
If this is a single hack, it's fine as it is.. If we're going to have an
API here, we should create a src/include/superio.h or some such
It's only used on this particular board.
Isn't there another init_ec function in the tree? Could they use the same
header file?
Acked-by: Myles Watson myle...@gmail.com
Thanks,
Myles
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] ASUS M2V-TVM....
does coreboot excute payload or not? On Thu, Apr 15, 2010 at 12:15 AM, Chi Min Wang cmw...@ms1.hinet.net wrote: Rudolf Marek wrote: 00K8T890 found at LDT 00 Agreed on width: 01 CPU programmed to HT freq: 05 VIA HT caps: 0075 00after enable_fid_change No other messages after this? What was wrong last time? No more messages,but if I comment the fid/vid related code out(maybe due to my Sempron 3000 lack of CnQ??),every thing looks fine except the coreboot does not excute payload(SeaBIOS) correctly -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Wang Qing Pei MSN:wangqing...@hotmail.com msn%3awangqing...@hotmail.com Gmail:wangqing...@gmail.com gmail%3awangqing...@gmail.com Phone:86+13426369984 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5439 - trunk/src/arch/i386
Author: stepan Date: Thu Apr 15 01:58:07 2010 New Revision: 5439 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5439 Log: get rid of this nerving crt0.d stuff Signed-off-by: Stefan Reinauer ste...@coresystems.de Acked-by: Stefan Reinauer ste...@coresystems.de Modified: trunk/src/arch/i386/Makefile.bigbootblock.inc trunk/src/arch/i386/Makefile.bootblock.inc Modified: trunk/src/arch/i386/Makefile.bigbootblock.inc == --- trunk/src/arch/i386/Makefile.bigbootblock.inc Wed Apr 14 23:47:24 2010(r5438) +++ trunk/src/arch/i386/Makefile.bigbootblock.inc Thu Apr 15 01:58:07 2010(r5439) @@ -26,7 +26,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/crt0.S @printf CC $(subst $(obj)/,,$(@))\n - $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $ $...@.new mv $...@.new $@ + $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -include $(obj)/config.h -I. -I$(src) $ -o $@ $(obj)/coreboot: $$(initobjs) $(obj)/ldscript.ld @printf LINK $(subst $(obj)/,,$(@))\n Modified: trunk/src/arch/i386/Makefile.bootblock.inc == --- trunk/src/arch/i386/Makefile.bootblock.inc Wed Apr 14 23:47:24 2010 (r5438) +++ trunk/src/arch/i386/Makefile.bootblock.inc Thu Apr 15 01:58:07 2010 (r5439) @@ -63,7 +63,7 @@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.s: $(obj)/bootblock/bootblock.c @printf CC $(subst $(obj)/,,$(@))\n - $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $ $...@.new mv $...@.new $@ + $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/bootblock -include $(obj)/config.h -I. -I$(src) $ -o $@ $(obj)/mainboard/$(MAINBOARDDIR)/bootblock.inc: $(src)/arch/i386/init/$(subst ,,$(CONFIG_BOOTBLOCK_SOURCE)) $(obj)/romcc @printf ROMCC $(subst $(obj)/,,$(@))\n @@ -107,5 +107,5 @@ $(obj)/mainboard/$(MAINBOARDDIR)/crt0.s: $(obj)/romstage/crt0.S @printf CC $(subst $(obj)/,,$(@))\n - $(CC) -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $ $...@.new mv $...@.new $@ + $(CC) -MMD -x assembler-with-cpp -DASSEMBLY -E -I$(src)/include -I$(src)/arch/i386/include -I$(obj) -I$(obj)/romstage -include $(obj)/config.h -I. -I$(src) $ -o $@ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Jetway PA78VM5-H support?
that would be very good, if you can mail me the board. But i would like to try order one first. On Wed, Apr 14, 2010 at 9:06 AM, Scott Olsen ole...@gmail.com wrote: Thank you very much. I have an extra board that I could mail to you if that would help? Scott On Tue, Apr 13, 2010 at 10:39 AM, Qing Pei Wang wangqing...@gmail.comwrote: hi, the only AMD 780 mainboard which coreboot support is mahogany. But there will be pretty much more, since i am trying to do several 780 mainboard porting.i think it's pretty find that we can port coreboot to this mainboard. I would like to add this mainboard into my GSOC mainboard list. I will try to order this mainboard if it can be bought in China. On Tue, Apr 13, 2010 at 7:23 AM, Scott Olsen ole...@gmail.com wrote: Hello, I noticed that AMD RS780/SB700 support has recently gotten initial support. I was wondering if the Jetway PA78VM5-H board is suitable for support? I've attached the lspci/superiotool/flashrom outputs. Thanks! Scott -- JetWay JPA78VM5-H-LF AM2+/AM2 AMD 780V HDMI Micro ATX AMD Motherboard - Retailhttp://www.newegg.com/Product/Product.aspx?Item=N82E16813153138cm_re=jetway_motherboard-_-13-153-138-_-Product Model Brand JetWay Model JPA78VM5-H-LF Supported CPU CPU Socket Type AM2+/AM2 CPU Type Phenom / Athlon 64 X2 / Athlon 64 / Sempron FSB 2600MHz Hyper Transport (5200 MT/s) Chipsets North Bridge AMD 780V South Bridge AMD SB700 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Wang Qing Pei MSN:wangqing...@hotmail.com msn%3awangqing...@hotmail.com Gmail:wangqing...@gmail.com gmail%3awangqing...@gmail.com Phone:86+13426369984 -- Wang Qing Pei MSN:wangqing...@hotmail.com msn%3awangqing...@hotmail.com Gmail:wangqing...@gmail.com gmail%3awangqing...@gmail.com Phone:86+13426369984 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [RFC] ACPI for ASUS P2B/P2B-LS (Intel 440BX/82371EB)
2010/4/14 Keith Hui buu...@gmail.com Hi all, Based on Idwer's RFC I tried adding ACPI to P2B-LS plus completing the rest of the PIIX4 function 3 initialization. This is a summary of what I did: * I used the DSDT table from the final vendor BIOS. Not provided here for obvious reasons, but I can tell you how to extract it. * I also replicated the content of the PIIX4 function 3 config space after booting with vendor BIOS, as below: 00:04.3 Bridge: Intel Corporation 82371AB/EB/MB PIIX4 ACPI (rev 02) 00: 86 80 13 71 03 00 80 02 02 00 80 06 00 00 00 00 10: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 20: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 30: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 40: 01 e4 00 00 00 00 00 20 1e 30 00 01 00 00 00 00 50: 00 58 19 00 c0 c8 3b 02 37 40 40 03 00 00 00 00 60: 90 02 e7 00 00 00 00 10 04 e4 11 00 00 00 00 00 70: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 90: 01 e8 00 00 00 00 00 00 00 00 00 00 00 00 00 00 a0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 b0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 c0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 d0: 00 00 01 00 00 00 00 00 00 00 00 00 00 00 00 00 e0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 f0: 00 00 00 00 00 00 00 00 30 0f 00 00 00 00 00 00 One exception is 0x90-0x91 which has the SMBus host base address. I kept it as 0x0f00. * Idwer is trying to build ACPI 4.0 (!) tables. Since P2B-LS is shipped when ACPI was still at 1.0, that's what I did. For booting XP, even ACPI 2.0 compliance is sufficient. Fixed the ACPI version, althought I'm not booting Windows. This is a summary of what happens: * I can no longer get POST codes on the PCI bus. POST codes still appear on the ISA bus. Glad I picked a POST card that works on both buses. What about POST codes on the serial port ? See http://www.coreboot.org/Coreboot_Options * Power off does not work. The last POST code to show before complete kernel shutdown and hard drive spinning down is 0xF5. * I don't how how to enter soft suspend in Linux (silly me -_-! ), so I have not tested it. http://acpi.sourceforge.net/documentation/sleep.html * the sensor appears on ISA bus port 0x290, just like vendor BIOS. * My SB AWE64 ISA card still got initialized and driver loaded, but no sound. In fact ALSA can't even do I/O to the card. That apparently is because PIIX4 needs to be configured to forward certain I/O port ranges to ISA, and some of those port ranges can be further configured. This would require detecting in runtime what ISA cards are installed, what are they, and what I/O port ranges they would use. Where in the source tree should I place such code? Southbridge? The changes I made are described in two attached patches, one to southbridge/intel/i82371eb, one to mainboard/asus/p2bls. My coreboot and linux boot log is also attached. Attached patch: coreboot_r5439_asus_p2b_ram+keithhui-pm+acpi-wip.patch coreboot's serial port log + dmesg and an incomplete bootlog from linux: http://coreboot.pastebin.com/x0QTfji7 This is also RFC and is not signed off at this point, but comments are welcome. When is it okay to sign off :) probably when the major functions like standby and soft poweroff/reset work like they should and the ACPI tables are created. Oh, and irq routing.. Self quote: Todo: - create PRT objects - finish/fix FADT - finish all other ACPI tables (RSDT, RSDP, DSDT etcetera) [0.00] ACPI: RSDP 000f7b20 00014 (v00 CORE ) [0.00] ACPI: RSDT 0fff1424 00034 (v01 CORE COREBOOT CORE ) [0.00] ACPI: FACP 0fff1aa2 000F4 (v01 COREBO COREBOOT CORE 002A) [0.00] ACPI: DSDT 0fff1508 0059A (v01 LXBIOS LXB-DSDT 0001 INTL 20090521) [0.00] ACPI: FACS 0fff14c8 00040 [0.00] ACPI: APIC 0fff1b96 0003E (v01 CORE COREBOOT CORE ) [0.00] ACPI: MCFG 0fff1bd4 0002C (v01 CORE COREBOOT CORE ) [0.00] ACPI: SRAT 0fff1c00 00030 (v01 CORE COREBOOT CORE ) - PIRQ routing [1.378731] irq 9: nobody cared (try booting with the irqpoll option) [1.380003] Pid: 1, comm: swapper Not tainted 2.6.32-21-generic #31-Ubuntu [1.380003] Call Trace: snip [1.380003] Disabling IRQ #9 [1.435077] ACPI: PCI Interrupt Link [LNKA] (IRQs) *15, disabled. [1.441889] ACPI: PCI Interrupt Link [LNKB] (IRQs 11) *15, disabled. [1.448908] ACPI: PCI Interrupt Link [LNKC] (IRQs 10) *15, disabled. [1.456644] ACPI: PCI Interrupt Link [LNKD] (IRQs 11) *15, disabled. [2.477092] ACPI: PCI Interrupt Link [LNKD] disabled and referenced, BIOS bug [3.173723] irq 11: nobody cared (try booting with the irqpoll option) [3.176017] Pid: 1, comm: swapper Not tainted 2.6.32-21-generic #31-Ubuntu [3.176017] Call Trace: snip [3.176017] Disabling IRQ #11 - standby/suspend [
[coreboot] [commit] r5440 - in trunk/src: cpu/amd/microcode cpu/amd/model_10xxx include/cpu/amd mainboard/amd/mahogany_fam10 mainboard/amd/serengeti_cheetah_fam10 mainboard/msi/ms9652_fam10 mainboard/
Author: myles
Date: Thu Apr 15 07:19:29 2010
New Revision: 5440
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5440
Log:
Remove a few more warnings from fam10.
Signed-off-by: Myles Watson myle...@gmail.com
Acked-by: Myles Watson myle...@gmail.com
Modified:
trunk/src/cpu/amd/microcode/microcode.c
trunk/src/cpu/amd/model_10xxx/init_cpus.c
trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c
trunk/src/cpu/amd/model_10xxx/update_microcode.c
trunk/src/include/cpu/amd/microcode.h
trunk/src/mainboard/amd/mahogany_fam10/romstage.c
trunk/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c
trunk/src/mainboard/msi/ms9652_fam10/romstage.c
trunk/src/mainboard/supermicro/h8dmr_fam10/romstage.c
trunk/src/mainboard/supermicro/h8qme_fam10/romstage.c
trunk/src/mainboard/tyan/s2912_fam10/romstage.c
trunk/src/northbridge/amd/amdfam10/amdfam10.h
trunk/src/northbridge/amd/amdfam10/debug.c
trunk/src/northbridge/amd/amdfam10/raminit_amdmct.c
trunk/src/northbridge/amd/amdht/h3finit.c
trunk/src/northbridge/amd/amdht/ht_wrapper.c
trunk/src/northbridge/amd/amdmct/mct/mct_d.c
trunk/src/northbridge/amd/amdmct/mct/mct_d_gcc.h
trunk/src/northbridge/amd/amdmct/mct/mct_fd.c
trunk/src/northbridge/amd/amdmct/mct/mctardk4.c
trunk/src/northbridge/amd/amdmct/wrappers/mcti_d.c
Modified: trunk/src/cpu/amd/microcode/microcode.c
==
--- trunk/src/cpu/amd/microcode/microcode.c Thu Apr 15 01:58:07 2010
(r5439)
+++ trunk/src/cpu/amd/microcode/microcode.c Thu Apr 15 07:19:29 2010
(r5440)
@@ -17,15 +17,16 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#ifndef __PRE_RAM__
-
+#ifndef __ROMCC__
#include stdint.h
#include console/console.h
-#include cpu/cpu.h
#include cpu/x86/msr.h
#include cpu/amd/microcode.h
-#include cpu/x86/cache.h
+#endif
+#ifndef __PRE_RAM__
+#include cpu/cpu.h
+#include cpu/x86/cache.h
#endif
struct microcode {
Modified: trunk/src/cpu/amd/model_10xxx/init_cpus.c
==
--- trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Apr 15 01:58:07 2010
(r5439)
+++ trunk/src/cpu/amd/model_10xxx/init_cpus.c Thu Apr 15 07:19:29 2010
(r5440)
@@ -30,7 +30,6 @@
#define SET_FIDVID_CORE0_ONLY 0
#endif
-void update_microcode(u32 cpu_deviceid);
static void prep_fid_change(void);
static void init_fidvid_stage2(u32 apicid, u32 nodeid);
void cpuSetAMDMSR(void);
Modified: trunk/src/cpu/amd/model_10xxx/model_10xxx_init.c
==
--- trunk/src/cpu/amd/model_10xxx/model_10xxx_init.cThu Apr 15 01:58:07
2010(r5439)
+++ trunk/src/cpu/amd/model_10xxx/model_10xxx_init.cThu Apr 15 07:19:29
2010(r5440)
@@ -37,8 +37,6 @@
#include cpu/amd/multicore.h
#include cpu/amd/model_10xxx_msr.h
-extern device_t get_node_pci(u32 nodeid, u32 fn);
-
#define MCI_STATUS 0x401
msr_t rdmsr_amd(u32 index)
Modified: trunk/src/cpu/amd/model_10xxx/update_microcode.c
==
--- trunk/src/cpu/amd/model_10xxx/update_microcode.cThu Apr 15 01:58:07
2010(r5439)
+++ trunk/src/cpu/amd/model_10xxx/update_microcode.cThu Apr 15 07:19:29
2010(r5440)
@@ -23,7 +23,9 @@
#include device/device.h
#include device/pci.h
#include string.h
+#endif
+#ifndef __ROMCC__
#include cpu/amd/microcode.h
#endif
Modified: trunk/src/include/cpu/amd/microcode.h
==
--- trunk/src/include/cpu/amd/microcode.h Thu Apr 15 01:58:07 2010
(r5439)
+++ trunk/src/include/cpu/amd/microcode.h Thu Apr 15 07:19:29 2010
(r5440)
@@ -2,6 +2,7 @@
#define CPU_AMD_MICORCODE_H
void amd_update_microcode(void *microcode_updates, unsigned processor_rev_id);
+void update_microcode(u32 processor_rev_id);
void model_fxx_update_microcode(unsigned cpu_deviceid);
#endif /* CPU_AMD_MICROCODE_H */
Modified: trunk/src/mainboard/amd/mahogany_fam10/romstage.c
==
--- trunk/src/mainboard/amd/mahogany_fam10/romstage.c Thu Apr 15 01:58:07
2010(r5439)
+++ trunk/src/mainboard/amd/mahogany_fam10/romstage.c Thu Apr 15 07:19:29
2010(r5440)
@@ -93,6 +93,8 @@
#include cpu/amd/quadcore/quadcore.c
#include cpu/amd/car/post_cache_as_ram.c
+#include cpu/amd/microcode/microcode.c
+#include cpu/amd/model_10xxx/update_microcode.c
#include cpu/amd/model_10xxx/init_cpus.c
#include cpu/amd/model_10xxx/fidvid.c
@@ -100,8 +102,6 @@
#include southbridge/amd/sb700/sb700_early_setup.c
//#include spd_addr.h
-#include cpu/amd/microcode/microcode.c
-#include cpu/amd/model_10xxx/update_microcode.c
#define RC00 0
#define RC01 1
