[coreboot] [PATCH] Add AES to devicetree.cb for AMD LX boards
Signed-off-by: Nathan Williams nat...@traverse.com.au Index: src/mainboard/digitallogic/msm800sev/devicetree.cb === --- src/mainboard/digitallogic/msm800sev/devicetree.cb (revision 5521) +++ src/mainboard/digitallogic/msm800sev/devicetree.cb (working copy) @@ -1,7 +1,8 @@ chip northbridge/amd/lx device pci_domain 0 on - device pci 1.0 on end - device pci 1.1 on end + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power Index: src/mainboard/amd/norwich/devicetree.cb === --- src/mainboard/amd/norwich/devicetree.cb (revision 5521) +++ src/mainboard/amd/norwich/devicetree.cb (working copy) @@ -2,6 +2,7 @@ device pci_domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power Index: src/mainboard/amd/db800/devicetree.cb === --- src/mainboard/amd/db800/devicetree.cb (revision 5521) +++ src/mainboard/amd/db800/devicetree.cb (working copy) @@ -2,6 +2,7 @@ device pci_domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power Index: src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb === --- src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb(revision 5521) +++ src/mainboard/iei/pcisa-lx-800-r10/devicetree.cb(working copy) @@ -2,6 +2,7 @@ device pci_domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power Index: src/mainboard/pcengines/alix1c/devicetree.cb === --- src/mainboard/pcengines/alix1c/devicetree.cb(revision 5521) +++ src/mainboard/pcengines/alix1c/devicetree.cb(working copy) @@ -1,7 +1,8 @@ chip northbridge/amd/lx device pci_domain 0 on - device pci 1.0 on end - device pci 1.1 on end + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power Index: src/mainboard/artecgroup/dbe61/devicetree.cb === --- src/mainboard/artecgroup/dbe61/devicetree.cb(revision 5521) +++ src/mainboard/artecgroup/dbe61/devicetree.cb(working copy) @@ -2,6 +2,7 @@ device pci_domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power Index: src/mainboard/winent/pl6064/devicetree.cb === --- src/mainboard/winent/pl6064/devicetree.cb (revision 5521) +++ src/mainboard/winent/pl6064/devicetree.cb (working copy) @@ -2,6 +2,7 @@ device pci_domain 0 on device pci 1.0 on end # Northbridge device pci 1.1 on end # Graphics + device pci 1.2 on end # AES chip southbridge/amd/cs5536 # IRQ 12 and 1 unmasked, Keyboard and Mouse IRQs. OK # SIRQ Mode = Active(Quiet) mode. Save power
Re: [coreboot] [PATCH] Add AES to devicetree.cb for AMD LX boards
On 5/4/10 10:07 AM, Nathan Williams wrote: Signed-off-by: Nathan Williams nat...@traverse.com.au - device pci 1.0 on end - device pci 1.1 on end + device pci 1.0 on end # Northbridge + device pci 1.1 on end # Graphics + device pci 1.2 on end # AES What's the impact of that change? Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Hardware damaged?
Hi, Please try to unplug the board completely from the power outlet and retry. Also dont forget to clear the CMOS. Then re-try with orig bios. Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Porting to RS780/SB700 board
I think there must be some MTRR setup problem. Maybe you could print out the MTRRs just before the slow parts? Here's a dump of various MSRs right after the call to raminit_amdmct() in romstage.c: /* fixed MTRRs */ msr 0250=1e1e1e1e1e1e1e1e msr 0258=1e1e1e1e1e1e1e1e msr 0259= msr 0268=1e1e1e1e msr 0269=1e1e1e1e1e1e1e1e msr 026a= msr 026b= msr 026c=0404040404040404 msr 026d=0404040404040404 msr 026e=0404040404040404 msr 026f=0404040404040404 I don't understand these values. I would have expected msr 0268=1e1e1e1e1e1e1e1e (0xc-c7fff) (only if CAR size = 64K) msr 0269=1e1e1e1e1e1e1e1e (0xc8000-c) Why are we setting anything in the 0-0x8 range ( msr 0x250) or the 0x8-0x9 range (msr 0x258)? Same question for 0xe-0xf (0x26d-26f). Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Hardware damaged?
Hi, Please try to unplug the board completely from the power outlet and retry. Also dont forget to clear the CMOS. Then re-try with orig bios. I unplugged the power, set the clear cmos jumper, waited some time and even removed the battery, but this doesn't help, still the same symptoms after powering on again. Mark signature.asc Description: This is a digitally signed message part. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Hardware damaged?
Hi, Hm no idea what went wrong. Do you see something on serial with the coreboot? Most likely 115200 bauds... Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Hardware damaged?
On Tue, May 4, 2010 at 8:49 AM, mark m...@tvk.rwth-aachen.de wrote: Hi, Please try to unplug the board completely from the power outlet and retry. Also dont forget to clear the CMOS. Then re-try with orig bios. I unplugged the power, set the clear cmos jumper, waited some time and even removed the battery, but this doesn't help, still the same symptoms after powering on again. Is there any output on the serial console with Coreboot? There should have been a lot of it the first time when you got to VGA init. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Hardware damaged?
Am 04.05.2010 16:49, schrieb mark: I unplugged the power, set the clear cmos jumper, waited some time and even removed the battery, but this doesn't help, still the same symptoms after powering on again. has a pin of the socket or the flash been bent? Greetings, Frieder -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard
On 05/04/2010 11:14 AM, Joop Boonen wrote: On Tue, May 4, 2010 1:02 am, Myles Watson wrote: I've build Coreboot for this main board with FILO with and without VGA ROM. But it doesn't get trough the boot process. It quits really early in device enumeration. You could put some debugging statements (printk) in amdk8_scan_chains and friends to see why it quits. I will, try this after I try rev 4920. rev 4920 works without a problem, also with the extracted VGA. I get the FILO screen. Can someone help me? It worked around rev 4920. Have you tried multiple revisions? It's not getting close to starting FILO or initializing the VGA. I will try this first (rev 4920). I'll let you know the outcome as soon as I've tested it. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard
rev 4920 works without a problem, also with the extracted VGA. I get the FILO screen. Great. You could check the values from Kconfig (build/config.h) and compare them to the values from 4920. That would be the easiest thing to fix. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard
On Tue, May 4, 2010 at 11:54 AM, Myles Watson myle...@gmail.com wrote: rev 4920 works without a problem, also with the extracted VGA. I get the FILO screen. Great. You could check the values from Kconfig (build/config.h) and compare them to the values from 4920. That would be the easiest thing to fix. I think the most likely culprit is SB_HT_CHAIN_ON_BUS0. Could you change it to 1 in src/mainboard/arima/hdama/Kconfig, make oldconfig, and test? Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Porting to RS780/SB700 board
-BEGIN PGP SIGNED MESSAGE- Hash: SHA1 Why are we setting anything in the 0-0x8 range ( msr 0x250) or the 0x8-0x9 range (msr 0x258)? addr = 0x250; --lo = 0x1E1E1E1E; --hi = lo; --_WRMSR(addr, lo, hi);---/* 0 - 512K = WB Mem */ --addr = 0x258; --_WRMSR(addr, lo, hi);---/* 512K - 640K = WB Mem */ In mctmtr_d.c Thanks, Rudolf -BEGIN PGP SIGNATURE- Version: GnuPG v1.4.10 (GNU/Linux) Comment: Using GnuPG with Mozilla - http://enigmail.mozdev.org iEYEARECAAYFAkvgiKIACgkQ3J9wPJqZRNUingCdGXpLI64NIXQoyAPLYYIussJr yjEAni1NY76Xn+IzFR5bFKU7pnVnL/BK =IuTW -END PGP SIGNATURE- -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Hardware damaged?
mark wrote: Did I brick the board somehow, or is it possible that coreboot bricked it somehow? I don't understand, what part of the board could have been damaged here. Short circuit? There could have been a short when you inserted the new flash chip with coreboot, but then you would not have gotten the one start with the colorful display. You could check the capacitors on the board for leaks - several on my EPIA-M board have leaked and the board doesn't start, but that's not likely because of coreboot, rather because of bad capacitors. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5522 - trunk/src/mainboard/arima/hdama
Author: myles Date: Wed May 5 00:30:33 2010 New Revision: 5522 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5522 Log: Fix arima/hdama. It was changed to match newconfig, which was broken. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson myle...@gmail.com Modified: trunk/src/mainboard/arima/hdama/Kconfig Modified: trunk/src/mainboard/arima/hdama/Kconfig == --- trunk/src/mainboard/arima/hdama/Kconfig Mon May 3 18:21:52 2010 (r5521) +++ trunk/src/mainboard/arima/hdama/Kconfig Wed May 5 00:30:33 2010 (r5522) @@ -62,7 +62,7 @@ config SB_HT_CHAIN_ON_BUS0 int - default 0 + default 1 depends on BOARD_ARIMA_HDAMA config HT_CHAIN_END_UNITID_BASE -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard
I think the most likely culprit is SB_HT_CHAIN_ON_BUS0. Could you change it to 1 in src/mainboard/arima/hdama/Kconfig, make oldconfig, and test? I've tested it. I get the filo screen now. Great. I checked that in Rev 5522. When I do a probe I don't see any IDE device yet. Neither IDE nor SATA SIL3114 drive. This also didn't work for version 4920. Have you tried SeaBIOS? I haven't used FILO much. In your log it looks like FILO is expecting to find something in your CMOS that it doesn't find. ERROR: No such CMOS option (boot_devices) menu: hda3:/boot/filo/menu.lst You could look into that. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Add AES to devicetree.cb for AMD LX boards
On 5/05/2010 12:15 AM, Stefan Reinauer wrote: On 5/4/10 10:07 AM, Nathan Williams wrote: Signed-off-by: Nathan Williams nat...@traverse.com.au -device pci 1.0 on end -device pci 1.1 on end +device pci 1.0 on end # Northbridge +device pci 1.1 on end # Graphics +device pci 1.2 on end # AES What's the impact of that change? Stefan I don't think it makes any difference. I just added it for completeness/documentation. Nathan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Coreboot doesn't boot on Arima HDAMA rev.G mainboard
On Tue, May 04, 2010 at 11:59:26PM +0200, Joop Boonen wrote: On Tue, May 4, 2010 8:16 pm, Myles Watson wrote: On Tue, May 4, 2010 at 11:54 AM, Myles Watson myle...@gmail.com wrote: rev 4920 works without a problem, also with the extracted VGA. I get the FILO screen. Great. You could check the values from Kconfig (build/config.h) and compare them to the values from 4920. That would be the easiest thing to fix. I think the most likely culprit is SB_HT_CHAIN_ON_BUS0. Could you change it to 1 in src/mainboard/arima/hdama/Kconfig, make oldconfig, and test? I've tested it. I get the filo screen now. When I do a probe I don't see any IDE device yet. Neither IDE nor SATA SIL3114 drive. This also didn't work for version 4920. Yeah, the Sil3114 needs special handling for its SATA ports. The Tyan S2881 board has the same problem. I'm not sure about the IDE ports. In the past I've used a linux kernel payload to get around that. Rudolf has had success with SeaBIOS (and the SiL3114 option rom, I believe) http://www.coreboot.org/pipermail/coreboot/2009-February/044781.htm but I have not been able to replicate that yet on my Tyan s2881. I wonder if we could make Coreboot do the necessary to initialize that controller, so that we don't need that binary blob or a full blown linux kernel anymore. There appear to be public datasheets for Sil3114, referenced here https://ata.wiki.kernel.org/index.php/Sata_sil And the kernel driver also knows how to bring it up, since using a linux kernel as a payload has worked for me in the past. Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Selfboot error checking fix
Check the return value of ulzma, and quit instead of loading the next
segment if there's an error.
Size pointers 8 characters instead of 16 to beautify the common case
where selfboot is loading something into memory below 4GB.
Signed-off-by: Myles Watson myle...@gmail.com
Thanks,
Myles
Index: src/boot/selfboot.c
===
--- src/boot/selfboot.c (revision 5521)
+++ src/boot/selfboot.c (working copy)
@@ -473,6 +473,8 @@
case CBFS_COMPRESS_LZMA: {
printk(BIOS_DEBUG, using LZMA\n);
len = ulzma(src, dest);
+ if (!len) /* Decompression Error. */
+ return 0;
break;
}
#if CONFIG_COMPRESSED_PAYLOAD_NRV2B==1
@@ -495,7 +497,7 @@
}
end = dest + ptr-s_memsz;
middle = dest + len;
- printk(BIOS_SPEW, [ 0x%016lx, %016lx, 0x%016lx) - %016lx\n,
+ printk(BIOS_SPEW, [ 0x%08lx, %08lx, 0x%08lx) - %08lx\n,
(unsigned long)dest,
(unsigned long)middle,
(unsigned long)end,
--
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