Re: [coreboot] [PATCH]libpayload: libc-style headers, some more functions
On 15.06.2010 21:25, Patrick Georgi wrote:
attached patch moves functions out of the huge libpayload.h into headers
according to libc/posix traditions, to simplify porting applications to
payloads.
Very much appreciated. This makes working with libpayload a lot easier.
It also adds a couple of functions:
strcasecmp, strncasecmp, strcat, strtol, strspn, strcspn, strtok_r,
strtok, perror, exit, getpagesize
Could you make perror() a wrapper for strerror()? flashrom will move to
strerror() soon to behave more like a library.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
I didn't review the code in depth, so my comments may be incomplete.
Did you write those functions from scratch, or did you merge proven code
from a BSD licensed codebase?
+int strtol(const char *ptr, char **endptr, int base)
strtol is long int, not int.
+char *strcat(char *d, const char *s)
What about more descriptive argument names?
char *strcat(char *dest, const char *src);
+size_t strspn(const char *s, const char *a)
size_t strspn(const char *s, const char *accept);
+size_t strcspn(const char *s, const char *a)
size_t strcspn(const char *s, const char *reject);
+char* strtok_r(char *str, const char *delim, char **ptr)
char *strtok_r(char *str, const char *delim, char **saveptr);
Index: include/pci.h
===
--- include/pci.h (Revision 5631)
+++ include/pci.h (Arbeitskopie)
@@ -36,8 +36,11 @@
#define REG_VENDOR_ID 0x00
#define REG_COMMAND 0x04
+#define REG_CLASS_DEV 0x0A
#define REG_HEADER_TYPE 0x0E
#define REG_PRIMARY_BUS 0x18
+#define REG_SUBSYS_VENDOR_ID 0x2C
+#define REG_SUBSYS_ID0x2E
#define REG_COMMAND_BM (1 2)
Here is seems you're using both spaces and tabs between the identifier
and the value. Apart from that, I found that some places use spaces for
indentation instead of tabs.
Index: libc/lib.c
===
--- libc/lib.c(Revision 5631)
+++ libc/lib.c(Arbeitskopie)
@@ -113,3 +113,13 @@
halt();
}
+void exit(int status)
+{
+ printf(exited with status %d\n, status);
+ halt();
+}
+
+int getpagesize(void)
+{
+ return 4096;
Maybe wrap that in a check for x86. OTOH, if this function is used to
determine mmap granularity, it should return 1 instead of 4096.
Regards,
Carl-Daniel
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Re: [coreboot] Porting to Asus M4A785-M
Juhana Helovuo kirjoitti: Hello, I am trying to get coreboot working on Asus M4A785-M with Athlon II X2 240e CPU (Socket AM3). So far there is no success. Hello again, There is now some progress in this port. - Found out that the northbridge was wrong. We should use AMD Family 10 instead of AMD K8. - Started porting effort again, this time from AMD Tilapia board, since it seemed to be a closer match. - Configured for AM3 CPU socket and DDR2 settings for memory controller (not DDR3). Coreboot now boots past the romstage and starts setting up PCI devices. Unfortunately, it crashes at some point during PCI setup. I do not have access to the boot log right now, but could post it later. I suspect that the devicetree.cb source file is somehow wrong and therefore coreboot does some wrong initialization or probe, which causes an immediate reboot. Is there a reference manual for writing the devicetree.cb file? All the documents I found in the Coreboot wiki seemed to describe some past version of it. Can the correctness of devicetree.cb be somehow verified against lspci output? If so, how? Best regards, Juhana Helovuo -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH]libpayload: libc-style headers, some more functions
Am 16.06.2010 09:35, schrieb Carl-Daniel Hailfinger:
Could you make perror() a wrapper for strerror()? flashrom will move to
strerror() soon to behave more like a library.
We don't have sterror, so I simply let it print the error code (which
isn't set anywhere). This is stubbed until there's actually some real
user of errno.
Signed-off-by: Patrick Georgi patrick.geo...@coresystems.de
I didn't review the code in depth, so my comments may be incomplete.
Did you write those functions from scratch, or did you merge proven code
from a BSD licensed codebase?
I adapted libpayload functions where possible (strtoul - strtol, for
example). Everything else is written from scratch.
strtol is long int, not int.
I'll change that for both strtol and strtoul, thanks.
+char *strcat(char *d, const char *s)
What about more descriptive argument names?
I adopted naming style (ie. single character names) from the other
functions (strncat for strcat, specifically).
This should be done globally, in a separate patch, in my opinion.
Index: include/pci.h
Here is seems you're using both spaces and tabs between the identifier
and the value. Apart from that, I found that some places use spaces for
indentation instead of tabs.
Fixed.
+int getpagesize(void)
+{
+return 4096;
Maybe wrap that in a check for x86. OTOH, if this function is used to
determine mmap granularity, it should return 1 instead of 4096.
I stuck with the meaning of the function (and x86 has 4k pages by default).
Instead of #ifdef-hell, I moved the function to arch/*/virtual.c - both
x86 and powerpc claim 4k pages now.
Patrick
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[coreboot] jetway PA78VM5 spi flashing
hi all, Recently i found that the mainboard which i used(Jetway PA78VM-H-LF) is not stable, most of the spi flashing caused data error. the data writing is ok, but the bios data does not as the same as the original. the SPI FLASH is Winbond W25X80A In the other hand, the board can not boot correctly, i am wondering if it's because of the CPU. Olsen, have you ever met this problem? -- Wang Qing Pei MSN:wangqing...@hotmail.com msn%3awangqing...@hotmail.com Gmail:wangqing...@gmail.com gmail%3awangqing...@gmail.com Phone:86+13426369984 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] SuperIO PNP resource allocation help
Hello,
Need some help understanding how the SuperIO PNP resource allocation works.
Particularly src/superio/smsc/smscsuperio pnp_dev_info. I need to reserve
128 bytes for device { ops, LD_PME, } but I am not really sure how the
magic behind this works. Anyone that could shed a light I would be much
appreciated.
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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Re: [coreboot] Porting to Asus M4A785-M
Coreboot now boots past the romstage and starts setting up PCI devices. Unfortunately, it crashes at some point during PCI setup. I do not have access to the boot log right now, but could post it later. That would be helpful. I suspect that the devicetree.cb source file is somehow wrong and therefore coreboot does some wrong initialization or probe, which causes an immediate reboot. Usually an incorrect device tree wouldn't cause a reboot. Do the devices selected in your Kconfig file match the devices in your device tree? Is there a reference manual for writing the devicetree.cb file? All the documents I found in the Coreboot wiki seemed to describe some past version of it. The best thing to do is copy a device tree from a similar board. The hard thing about AMD device trees is that the chips in a HyperTransport chain need to be listed in reverse order. You'll get a lot more malloc debugging statements if your device tree is incorrect, since it will find the devices (just not where it expects to), and the devices from the tree will be disabled. Can the correctness of devicetree.cb be somehow verified against lspci output? If so, how? The best way is looking through the log to see which devices are allocated with malloc, and which get disabled. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Will my board be supported?
Hello! I am interested in Coreboot and want to try it on my old desktop. It is an ASUS A7V880, but i cannot find it in the list of boards. So here is my hardware, i hope everything is included: ASUS A7V880 with AthlonXP 2600+, 2GB Ram, HD connected to the SATA controller. The Manual says (highlights): Chipset VIA KT880, VIA VT8237 FSB 400,333,266,200 1x AGPx8, 5xPCI 2x UDMA(IDE) 133 2x SATA ASUS EZ Flash ASUS CrashFree BIOS 2 ASUS Q-Fan 4Mb Flash EEPROM, Award BIOS, PnP, DMI2.0, WfM2.0, SM Bios 2.3, ACPI $ lspci -tvnn -[:00]-+-00.0 VIA Technologies, Inc. KT880 Host Bridge [1106:0269] +-00.1 VIA Technologies, Inc. KT880 Host Bridge [1106:1269] +-00.2 VIA Technologies, Inc. KT880 Host Bridge [1106:2269] +-00.3 VIA Technologies, Inc. KT880 Host Bridge [1106:3269] +-00.4 VIA Technologies, Inc. KT880 Host Bridge [1106:4269] +-00.7 VIA Technologies, Inc. KT880 Host Bridge [1106:7269] +-01.0-[:01]00.0 nVidia Corporation NV34 [GeForce FX 5200] [10de:0322] +-0a.0 Intel Corporation 82557/8/9/0/1 Ethernet Pro 100 [8086:1229] +-0e.0 VIA Technologies Inc. VT1720/24 [Envy24PT/HT] PCI Multi-Channel Audio Controller [1412:1724] +-0f.0 VIA Technologies, Inc. VIA VT6420 SATA RAID Controller [1106:3149] +-0f.1 VIA Technologies, Inc. VT82C586A/B/VT82C686/A/B/VT823x/A/C PIPC Bus Master IDE [1106:0571] +-10.0 VIA Technologies, Inc. VT82x UHCI USB 1.1 Controller [1106:3038] +-10.1 VIA Technologies, Inc. VT82x UHCI USB 1.1 Controller [1106:3038] +-10.2 VIA Technologies, Inc. VT82x UHCI USB 1.1 Controller [1106:3038] +-10.3 VIA Technologies, Inc. VT82x UHCI USB 1.1 Controller [1106:3038] +-10.4 VIA Technologies, Inc. USB 2.0 [1106:3104] +-11.0 VIA Technologies, Inc. VT8237 ISA bridge [KT600/K8T800/K8T890 South] [1106:3227] +-11.5 VIA Technologies, Inc. VT8233/A/8235/8237 AC97 Audio Controller [1106:3059] \-11.6 VIA Technologies, Inc. AC'97 Modem Controller [1106:3068] $superiotool -d (I skipped V because it reports only failed) superiotool r3125 Found ITE IT8712F (id=0x8712, rev=0x5) at 0x2e Register dump: idx 07 20 21 22 23 24 2b val 0a 87 12 05 01 00 00 def NA 87 12 08 00 00 00 LDN 0x00 (Floppy) idx 30 60 61 70 74 f0 f1 val 01 03 f0 06 02 00 00 def 00 03 f0 06 02 00 00 LDN 0x01 (COM1) idx 30 60 61 70 f0 f1 f2 f3 val 00 00 00 00 00 50 00 7f def 00 03 f8 04 00 50 00 7f LDN 0x02 (COM2) idx 30 60 61 70 f0 f1 f2 f3 val 00 02 f8 03 00 50 00 7f def 00 02 f8 03 00 50 00 7f LDN 0x03 (Parallel port) idx 30 60 61 62 63 70 74 f0 val 00 00 00 00 00 00 04 00 def 00 03 78 07 78 07 03 03 LDN 0x04 (Environment controller) idx 30 60 61 62 63 70 f0 f1 f2 f3 f4 f5 f6 val 01 0c 00 0b 00 00 00 00 06 00 80 00 ff def 00 02 90 02 30 09 00 00 00 00 00 NA NA LDN 0x05 (Keyboard) idx 30 60 61 62 63 70 71 f0 val 01 00 60 00 64 01 02 00 def 01 00 60 00 64 01 02 08 LDN 0x06 (Mouse) idx 30 70 71 f0 val 01 0c 02 00 def 00 0c 02 00 LDN 0x07 (GPIO) idx 25 26 27 28 29 2a 2c 60 61 62 63 64 65 70 71 72 73 74 b0 b1 b2 b3 b4 b5 b8 b9 ba bb bc bd c0 c1 c2 c3 c4 c8 c9 ca cb cc e0 e1 e2 e3 e4 f0 f1 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd val 00 00 36 80 00 00 00 00 00 04 80 00 00 00 00 00 00 04 00 00 00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 34 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 16 00 def 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 c0 00 00 00 00 00 00 00 00 00 00 00 00 00 01 00 00 40 00 01 00 00 40 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 NA 00 LDN 0x08 (MIDI port) idx 30 60 61 70 f0 val 00 00 00 00 00 def 00 03 00 0a 00 LDN 0x09 (Game port) idx 30 60 61 val 00 00 00 def 00 02 01 LDN 0x0a (Consumer IR) idx 30 60 61 70 f0 val 00 03 10 0b 06 def 00 03 10 0b 00 $ flashrom -v Calibrating delay loop... OK. No coreboot table found. Found chipset VIA VT8237, enabling flash write... OK. Found chip PMC Pm49FL004 (512 KB) at physical address 0xfff8. URL to ASUS http://support.asus.com/download/download.aspx?SLanguage=de-demodel=A7V880product=1 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Strange ROMCC failure with Rev 5623
When compiling asus/p2b (and several others), Rev 5622 succeeds, but 5623 fails. make: *** [build/mainboard/asus/p2b/romstage.inc] Segmentation fault make: *** Deleting file `build/mainboard/asus/p2b/romstage.inc' The only difference for these boards is this line in config.h: #define CONFIG_VENDOR_ECS 0 Removing this line lets 5623 build correctly. Is there some limit on the length of this file? The number of #defines? I'm using the reference compiler to compile romcc. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Strange ROMCC failure with Rev 5623
On Wed, Jun 16, 2010 at 12:00 PM, Myles Watson myle...@gmail.com wrote: When compiling asus/p2b (and several others), Rev 5622 succeeds, but 5623 fails. make: *** [build/mainboard/asus/p2b/romstage.inc] Segmentation fault make: *** Deleting file `build/mainboard/asus/p2b/romstage.inc' The only difference for these boards is this line in config.h: #define CONFIG_VENDOR_ECS 0 Removing this line lets 5623 build correctly. Removing any line from the file that doesn't affect the build works. (CONFIG_VENDOR_*, CONFIG_DEFAULT_CONSOLE_LEVEL_*, etc.) Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Porting to Asus M4A785-M
On Wed, 2010-06-16 at 08:30 -0600, Myles Watson wrote:
Coreboot now boots past the romstage and starts setting up PCI devices.
Unfortunately, it crashes at some point during PCI setup. I do not have
access to the boot log right now, but could post it later.
That would be helpful.
Ok, here I have a boot log attached, in case anyone is interested.
At the end of the log the machine resets and the same starts over from
the beginning.
I do not know what the PCI device setup should look like, but towards
the end of the log it seems to iterate over the same devices many times.
Best regards,
Juhana Helovuo
coreboot-4.0-r5631M Thu Jun 17 06:40:35 EEST 2010 starting...
BSP Family_Model: 00100f62
*sysinfo range: [000cc000,000cdfa0]
bsp_apicid = 00
cpu_init_detectedx =
microcode: equivalent rev id = 0x1062, current patch id = 0x
microcode: rev id (1043) does not match this patch.
microcode: Not updated! Fix microcode_updates[]
POST: 0x33
cpuSetAMDMSR done
POST: 0x34
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 02
event: 2005
data: 05 00 00 00 01
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 00 ff
Exit amd_ht_init()
POST: 0x35
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c8810f26
F3xD8: 032c1416
F3xDC: 0027532c
POST: 0x36
core0 started:
start_other_cores()
init node: 00 cores: 01
Start other core - nodeid: 00 cores: 01
POST: 0x37
started ap apicid: POST: 0x30
corex: --- { APICID = 01 NODEID = 00 COREID = 01} ---
* miAPcr 0oc1sotdae:rt eedqu
iv
alPeOSntT: r 0evx 38id
pars= 780x0_10e6ar2,ly c_suretruenp(t )
gtceht _icpd u_= re0vx0 E00AX00=000x010
0fmi62cr.o
coCdPUe: R reev v isid K (8_11040.3)
pdfoames1 0_noopt timamtizchat tiohins( )
atrchs.78
: mipocrr_oiconidet
d Not updatsebd7! 00Fi_xea mrlicy_rosectodupe_()up
astb7es00[]_d e
dccpeuSs_etpoAMr_DiMSniR t()
sonbe70
_idnievti_fceids_vipod_ra_ip(nistt(ag)e: 1)SM aBupisc Didev: ic01e,
APBDIDF:VI0-D2 0o-n 0
: 01
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()
Begin FIDVID MSR 0xc0010071 0x30b80093 0x3c00240c
POST: 0x39
FIDVID on BSP, APIC_id: 00
BSP fid = 10600
Wait for AP stage 1: ap_apicid = 1
readback = 1010601
common_fid(packed) = 10600
common_fid = 10600
FID Change Node:00, F3xD4: c8810f26
POST: 0x3a
End FIDVIDMSR 0xc0010071 0x30b80093 0x3c00240c
rs780_htinit cpu_ht_freq=b.
rs780_htinit: HT3 mode
...WARM RESET...
coreboot-4.0-r5631M Thu Jun 17 06:40:35 EEST 2010 starting...
BSP Family_Model: 00100f62
*sysinfo range: [000cc000,000cdfa0]
bsp_apicid = 00
cpu_init_detectedx =
microcode: equivalent rev id = 0x1062, current patch id = 0x
microcode: rev id (1043) does not match this patch.
microcode: Not updated! Fix microcode_updates[]
POST: 0x33
cpuSetAMDMSR done
POST: 0x34
Enter amd_ht_init()
AMD_CB_EventNotify()
event class: 02
event: 2005
data: 05 00 00 00 01
AMD_CB_EventNotify()
event class: 05
event: 2006
data: 04 00 00 ff
Exit amd_ht_init()
POST: 0x35
cpuSetAMDPCI 00 done
Prep FID/VID Node:00
F3x80: e600a681
F3x84: a0e641e6
F3xD4: c8810f26
F3xD8: 032c1416
F3xDC: 0027532c
POST: 0x36
core0 started:
start_other_cores()
init node: 00 cores: 01
Start other core - nodeid: 00 cores: 01
POST: 0x37
started ap apicid: POST: 0x30
corex: --- { APICID = 01 NODEID = 00 COREID = 01} ---
* miAPcr 0oc1osdtae:rt eedqu
av
PleOSntT: r e0xv 38id
par=s7 08x0_10ea62rl, yc_suretreupnt( )
gtceth _icpd u_=r 0evx0 E00AX0=000x0010
ocm6ic2.r
) oCPdUe : Rerev vi is d K8(1_10043.
dfoaem1s 0_noopt tmimatizchat tihonis( )p
0trcsh.78
m_picorro_icnodite:
Not updatsebd7! 00Fi_ex amrlicy_rosecotdupe_()up
eastb7es00[]_d
dicpceuSs_etpAorMD_iMSniR t()
00sonb7e
vii_ndeitvi_fceidsv_pidor_s_itnagite2() a:p SicMBidus: 0De1
ce, BDF:0-20-0
SMBus controller enabled, sb revision is A14
sb700_devices_por_init(): IDE Device, BDF:0-20-1
sb700_devices_por_init(): LPC Device, BDF:0-20-3
sb700_devices_por_init(): P2P Bridge, BDF:0-20-4
sb700_devices_por_init(): SATA Device, BDF:0-18-0
sb700_pmio_por_init()
Begin FIDVID MSR 0xc0010071 0x30b80093 0x3c00240c
POST: 0x39
POST: 0x3a
End FIDVIDMSR 0xc0010071 0x30b80093 0x3c00240c
rs780_htinit cpu_ht_freq=b.
rs780_htinit: HT3 mode
POST: 0x3b
fill_mem_ctrl()
POST: 0x40
raminit_amdmct()
raminit_amdmct begin:
Node: 00 base: 00 limit: 7f BottomIO: e0
raminit_amdmct end:
POST: 0x41
POST: 0x42
*** Yes, the copy/decompress is taking a while, FIXME!
v_esp=000cbf38
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing
[coreboot] request for comments: Gigabyte GA-945PL-S3 (rev. 1.0)
I'm really interested in using coreboot and tried to follow http://www.coreboot.org/FAQ to find out about the chances for my motherboard. Note: I disabled line wrapping for better readability of command line tools output. No annoying intended. * Step 1: A very brief description of your system: board vendor, board name, CPU, northbridge, southbridge, and optionally other important details. Board: Gigabyte GA-945PL-S3 (rev. 1.0) CPU: Intel Core Duo # Northbridge: Intel® 945PL Express Chipset # Southbridge: Intel® ICH7 # Realtek 8111B Gigabit Ethernet controller further Bios details: BIOS 1. 4 Mbit flash ROM 2. Use of licensed AWARD BIOS 3. Supports Virtual Dual BIOS 4. PnP 1.0a, DMI 2.0, SM BIOS 2.3, ACPI 1.0b. Other Features 1. Supports @BIOS 2. Supports Download Center 3. Supports Q-Flash 4. Supports EasyTune 5 5. Supports Xpress Install 6. Supports Xpress Recovery2 7. Supports Virtual DualBIOS * Step 2: Linux lspci -tvnn output for your system, generated by booting Linux via the original BIOS and runnning lspci. -[:00]-+-00.0 Intel Corporation 82945G/GZ/P/PL Memory Controller Hub [8086:2770] +-1b.0 Intel Corporation 82801G (ICH7 Family) High Definition Audio Controller [8086:27d8] +-1c.0-[01]--+-00.0 JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller [197b:2363] |\-00.1 JMicron Technology Corp. JMB362/JMB363 Serial ATA Controller [197b:2363] +-1c.3-[02]00.0 Realtek Semiconductor Co., Ltd. RTL8111/8168B PCI Express Gigabit Ethernet controller [10ec:8168] +-1d.0 Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #1 [8086:27c8] +-1d.1 Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #2 [8086:27c9] +-1d.2 Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #3 [8086:27ca] +-1d.3 Intel Corporation 82801G (ICH7 Family) USB UHCI Controller #4 [8086:27cb] +-1d.7 Intel Corporation 82801G (ICH7 Family) USB2 EHCI Controller [8086:27cc] +-1e.0-[03]--+-00.0 VIA Technologies, Inc. VT82x UHCI USB 1.1 Controller [1106:3038] |+-00.1 VIA Technologies, Inc. VT82x UHCI USB 1.1 Controller [1106:3038] |+-00.2 VIA Technologies, Inc. USB 2.0 [1106:3104] |+-00.3 VIA Technologies, Inc. VT6306/7/8 [Fire II(M)] IEEE 1394 OHCI Controller [1106:3044] |\-02.0 ATI Technologies Inc 3D Rage Pro 215GP [1002:4750] +-1f.0 Intel Corporation 82801GB/GR (ICH7 Family) LPC Interface Bridge [8086:27b8] +-1f.1 Intel Corporation 82801G (ICH7 Family) IDE Controller [8086:27df] +-1f.2 Intel Corporation 82801GB/GR/GH (ICH7 Family) SATA IDE Controller [8086:27c0] \-1f.3 Intel Corporation 82801G (ICH7 Family) SMBus Controller [8086:27da] * Step 3: Super I/O chip on the mainboard (report the model numbers on the actual chip, for example Winbond W83627HF and/or run superiotool -dV). superiotool said: Found ITE IT8718F (id=0x8718, rev=0x1) at 0x2e * Step 4: Type of BIOS device (see the question How do I identify the BIOS chip on my mainboard? below). Please send us the output of flashrom -V flashrom -V said in between: [...] Found ITE Super I/O, id 8718 Found chipset Intel ICH7/ICH7R, enabling flash write... [...] Found chip SST SST25VF040.REMS (512 KB, SPI) at physical address 0xfff8. [...] * Step 5: URL to the mainboard specifications page (optional). All non-generated information comes from from http://www.gigabyte.us/Support/Motherboard/BIOS_Model.aspx?ProductID=2325 * Step 6: Any other relevant information you can provide. I'm extremely comfortable with C and linux in general and willing to invest time into making this work if possible. Please let me know if there's a chance to get coreboot running and/or if there is anything I can do to help. Please CC me - I'm subscribed but disabled reception until it makes sense to get further involved. Best regards! John -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Porting to Asus M4A785-M
On Wed, Jun 16, 2010 at 1:55 PM, Juhana Helovuo j...@iki.fi wrote: On Wed, 2010-06-16 at 08:30 -0600, Myles Watson wrote: Coreboot now boots past the romstage and starts setting up PCI devices. Unfortunately, it crashes at some point during PCI setup. I do not have access to the boot log right now, but could post it later. That would be helpful. Ok, here I have a boot log attached, in case anyone is interested. At the end of the log the machine resets and the same starts over from the beginning. I do not know what the PCI device setup should look like, but towards the end of the log it seems to iterate over the same devices many times. Yes. I'm not sure why that's happening. Could you send your devicetree.cb? Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Porting to Asus M4A785-M
I think the IT8712 has a watchdog enabled. You need to disable it. Call it8712f_kill_watchdog() Thanks, Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] rommcc bugs
Hi all,
Second problem is very strange:
mare...@kiur:~/dilna/coreboot$ make
GENbuild.h
ROMCC romstage.inc
ne2k.c:83.0: warning: comment next line causes stuff to compile again
ne2k.c:126.0: warning: Add timeout
romstage.c:74.0:
Internal compiler error: constant for unknown type
make: *** [build/mainboard/soyo/sy-6ba-plus-iii/romstage.inc] Aborted
The board is Soyo, you need to apply the attached patch.
If you comment out in ne2k.c line 84 it will compile again :/
I tried to isolate the problem but i was able to compile the ne2k.c just fine. I
suspect romcc runs out of some resources.
Please let me know if you are able to reproduce the problem,
Thanks,
Rudolf
Index: src/include/ip_checksum.h
===
--- src/include/ip_checksum.h (revision 5631)
+++ src/include/ip_checksum.h (working copy)
@@ -1,7 +1,10 @@
#ifndef IP_CHECKSUM_H
#define IP_CHECKSUM_H
+#ifndef __ROMCC__
unsigned long compute_ip_checksum(void *addr, unsigned long length);
unsigned long add_ip_checksums(unsigned long offset, unsigned long sum, unsigned long new);
-
+void str2ip(const char *str, unsigned char *ip);
+void str2mac(const char *str, unsigned char *mac);
+#endif
#endif /* IP_CHECKSUM_H */
Index: src/include/console/ne2k.h
===
--- src/include/console/ne2k.h (revision 0)
+++ src/include/console/ne2k.h (revision 0)
@@ -0,0 +1,27 @@
+#ifndef _NE2K_H__
+#define _NE2K_H__
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Rudolf Marek r.ma...@assembler.cz
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __ROMCC__
+void ne2k_append_data(unsigned char *d, int len, unsigned int base);
+int ne2k_init(unsigned int eth_nic_base);
+void ne2k_transmit(unsigned int eth_nic_base);
+#endif
+#endif /* _NE2K_H */
Index: src/include/console/console.h
===
--- src/include/console/console.h (revision 5631)
+++ src/include/console/console.h (working copy)
@@ -131,6 +131,10 @@
#include pc80/serial.c
+#if CONFIG_CONSOLE_NE2K
+#include lib/ne2k.c
+#endif
+
/* __ROMCC__ */
static void __console_tx_byte(unsigned char byte)
{
@@ -191,10 +195,18 @@
if (console_loglevel = loglevel) {
unsigned char ch;
while((ch = *str++) != '\0') {
+#if CONFIG_CONSOLE_NE2K
+ unsigned char *ptr;
+ ptr = (unsigned char *) (str - 1);
+ ne2k_append_data(ptr, 1, CONFIG_CONSOLE_NE2K_IO_PORT);
+#endif
if (ch == '\n')
__console_tx_byte('\r');
__console_tx_byte(ch);
}
+#if CONFIG_CONSOLE_NE2K
+ ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT);
+#endif
}
}
Index: src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
===
--- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c (revision 5631)
+++ src/mainboard/soyo/sy-6ba-plus-iii/romstage.c (working copy)
@@ -54,6 +54,8 @@
it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
+ //ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT);
+
console_init();
report_bist_failure(bist);
Index: src/mainboard/asus/p2b/romstage.c.orig
===
Index: src/mainboard/asus/p2b/acpi_tables.c
===
Index: src/mainboard/asus/p2b/dsdt.asl
===
Index: src/console/Kconfig
===
--- src/console/Kconfig (revision 5631)
+++ src/console/Kconfig (working copy)
@@ -1,5 +1,4 @@
menu Console options
-
# TODO: Rename to SERIAL_CONSOLE once Kconfig transition is complete.
config CONSOLE_SERIAL8250
bool Serial port console output
@@ -130,6 +129,48 @@
help
If not selected, the last adapter found will be used.
+config CONSOLE_NE2K
+ bool Network console over NE2000 compatible Ethernet adapter
+ default y
+ help
+ Send coreboot debug output to a Ethernet console, it works
+ same way as Linux netconsole, packets are received to UDP
+ port on IP/MAC specified with options bellow.
+
+config CONSOLE_NE2K_DST_MAC
+ depends on CONSOLE_NE2K
+ string Destination MAC address of remote system
+ default 00:13:d4:76:a2:ac
+ help
+ Type in
Re: [coreboot] rommcc bugs
On Wed, Jun 16, 2010 at 2:41 PM, Rudolf Marek r.ma...@assembler.cz wrote: Hi all, Second problem is very strange: mare...@kiur:~/dilna/coreboot$ make GEN build.h ROMCC romstage.inc ne2k.c:83.0: warning: comment next line causes stuff to compile again ne2k.c:126.0: warning: Add timeout romstage.c:74.0: Internal compiler error: constant for unknown type make: *** [build/mainboard/soyo/sy-6ba-plus-iii/romstage.inc] Aborted The board is Soyo, you need to apply the attached patch. If you comment out in ne2k.c line 84 it will compile again :/ This is what I get: Internal compiler error: constant for unknown type If I comment out lines 83 84 I get: src/lib/ne2k.c:71: warning: no previous prototype for 'eth_pio_write_byte' src/lib/ne2k.c:125:2: warning: #warning Add timeout src/lib/ne2k.c:89: warning: 'eth_pio_read_byte' defined but not used CC lib/compute_ip_checksum.initobj.o CC console/vtxprintf.initobj.o CC arch/i386/lib/printk_init.initobj.o CC arch/i386/lib/cbfs_and_run.initobj.o LINK coreboot OBJCOPYcoreboot.bootblock CC arch/i386/lib/c_start.o CC lib/ne2k.driver.o src/lib/ne2k.c:71: warning: no previous prototype for 'eth_pio_write_byte' src/lib/ne2k.c:125:2: warning: #warning Add timeout src/lib/ne2k.c:89: warning: 'eth_pio_read_byte' defined but not used CC console/uart8250_console.driver.o make: *** No rule to make target `build/console/ne2k_console.driver.o', needed by `build/coreboot_ram.o'. Stop. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] i810E and ICH2 inteltool support
This patch adds inteltool support for i810E and ICH2.
Signed-off-by: Joseph Smith j...@settoplinux.org
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
Index: util/inteltool/gpio.c
===
--- util/inteltool/gpio.c (revision 5631)
+++ util/inteltool/gpio.c (working copy)
@@ -39,6 +39,25 @@
{ 0x3C, 4, RESERVED }
};
+static const io_register_t ich2_gpio_registers[] = {
+ { 0x00, 4, GPIO_USE_SEL },
+ { 0x04, 4, GP_IO_SEL },
+ { 0x08, 4, RESERVED },
+ { 0x0c, 4, GP_LVL },
+ { 0x10, 4, RESERVED },
+ { 0x14, 4, GPO_TTL },
+ { 0x18, 4, GPO_BLINK },
+ { 0x1c, 4, RESERVED },
+ { 0x20, 4, RESERVED },
+ { 0x24, 4, RESERVED },
+ { 0x28, 4, RESERVED },
+ { 0x2c, 4, GPI_INV },
+ { 0x30, 4, RESERVED },
+ { 0x34, 4, RESERVED },
+ { 0x38, 4, RESERVED },
+ { 0x3C, 4, RESERVED }
+};
+
static const io_register_t ich4_gpio_registers[] = {
{ 0x00, 4, GPIO_USE_SEL },
{ 0x04, 4, GP_IO_SEL },
@@ -176,6 +195,11 @@
gpio_registers = ich4_gpio_registers;
size = ARRAY_SIZE(ich4_gpio_registers);
break;
+ case PCI_DEVICE_ID_INTEL_ICH2:
+ gpiobase = pci_read_word(sb, 0x58) 0xfffc;
+ gpio_registers = ich2_gpio_registers;
+ size = ARRAY_SIZE(ich2_gpio_registers);
+ break;
case PCI_DEVICE_ID_INTEL_ICH:
case PCI_DEVICE_ID_INTEL_ICH0:
gpiobase = pci_read_word(sb, 0x58) 0xfffc;
Index: util/inteltool/inteltool.h
===
--- util/inteltool/inteltool.h (revision 5631)
+++ util/inteltool/inteltool.h (working copy)
@@ -55,6 +55,7 @@
#define PCI_DEVICE_ID_INTEL_82810 0x7120
#define PCI_DEVICE_ID_INTEL_82810DC 0x7122
+#define PCI_DEVICE_ID_INTEL_82810E_MC 0x7124
#define PCI_DEVICE_ID_INTEL_82830M 0x3575
#define PCI_DEVICE_ID_INTEL_82845 0x1a30
#define PCI_DEVICE_ID_INTEL_82915 0x2580
Index: util/inteltool/pcie.c
===
--- util/inteltool/pcie.c (revision 5631)
+++ util/inteltool/pcie.c (working copy)
@@ -49,6 +49,7 @@
break;
case PCI_DEVICE_ID_INTEL_82810:
case PCI_DEVICE_ID_INTEL_82810DC:
+ case PCI_DEVICE_ID_INTEL_82810E_MC:
case PCI_DEVICE_ID_INTEL_82830M:
printf(This northbrigde does not have EPBAR.\n);
return 1;
@@ -102,6 +103,7 @@
break;
case PCI_DEVICE_ID_INTEL_82810:
case PCI_DEVICE_ID_INTEL_82810DC:
+ case PCI_DEVICE_ID_INTEL_82810E_MC:
printf(This northbrigde does not have DMIBAR.\n);
return 1;
default:
@@ -156,6 +158,7 @@
break;
case PCI_DEVICE_ID_INTEL_82810:
case PCI_DEVICE_ID_INTEL_82810DC:
+ case PCI_DEVICE_ID_INTEL_82810E_MC:
printf(Error: This northbrigde does not have PCIEXBAR.\n);
return 1;
default:
Index: util/inteltool/powermgt.c
===
--- util/inteltool/powermgt.c (revision 5631)
+++ util/inteltool/powermgt.c (working copy)
@@ -299,6 +299,69 @@
{ 0x7c, 4, RESERVED },
};
+static const io_register_t ich2_pm_registers[] = {
+ { 0x00, 2, PM1_STS },
+ { 0x02, 2, PM1_EN },
+ { 0x04, 4, PM1_CNT },
+ { 0x08, 4, PM1_TMR },
+ { 0x0c, 4, RESERVED },
+ { 0x10, 4, PROC_CNT },
+#if DANGEROUS_REGISTERS
+ /* This register returns 0 on read, but reading it may cause
+ * the system to enter C2 state, which might hang the system.
+ */
+ { 0x14, 1, LV2 },
+ { 0x15, 1, RESERVED },
+ { 0x16, 2, RESERVED },
+#endif
+ { 0x18, 4, RESERVED },
+ { 0x1c, 4, RESERVED },
+ { 0x20, 4, RESERVED },
+ { 0x24, 4, RESERVED },
+ { 0x28, 2, GPE0_STS },
+ { 0x2a, 2, GPE0_EN },
+ { 0x2c, 2, GPE1_STS },
+ { 0x2e, 2, GPE1_EN },
+ { 0x30, 2, SMI_EN },
+ { 0x32, 2, RESERVED },
+ { 0x34, 2, SMI_STS },
+ { 0x36, 2, RESERVED },
+ { 0x38, 4, RESERVED },
+ { 0x3c, 4, RESERVED },
+ { 0x40, 2, MON_SMI_STS },
+ { 0x42, 2, RESERVED },
+ { 0x44, 2, DEV_TRP_STS },
+ { 0x46, 2, RESERVED },
+ { 0x48, 2, TRP_EN },
+ { 0x4A, 2, RESERVED },
+ { 0x4c, 2, BUS_ADDR_TRACK },
+ { 0x4e, 1, BUS_CYC_TRACK },
+ { 0x4f, 1, RESERVED },
+ { 0x50, 4, RESERVED },
+ { 0x54, 4, RESERVED },
+ { 0x58, 4, RESERVED },
+ { 0x5c, 4, RESERVED },
+ /* Here start the TCO registers */
+ { 0x60, 1, TCO_RLD },
+ { 0x61, 1, TCO_TMR },
+ { 0x62, 1, TCO_DAT_IN },
+ { 0x63, 1, TCO_DAT_OUT },
+ { 0x64, 2, TCO1_STS },
+ { 0x66, 2, TCO2_STS },
+ { 0x68, 2, TCO1_CNT },
+ { 0x6a, 2, TCO2_CNT },
+ { 0x6c, 1, TCO_MESSAGE1 },
+ { 0x6d, 1, TCO_MESSAGE2 },
+ { 0x6e, 1, TCO_WDSTATUS },
+ { 0x6f, 1, RESERVED },
+ { 0x70, 1, SW_IRQ_GEN },
+ { 0x71, 1, RESERVED },
+ { 0x72, 2, RESERVED },
+ { 0x74, 4, RESERVED },
+ { 0x78, 4, RESERVED },
+ { 0x7c, 4, RESERVED },
+};
+
static const io_register_t ich0_pm_registers[] = {
{ 0x00, 2, PM1_STS },
{ 0x02, 2, PM1_EN },
@@ -443,6 +506,11 @@
pm_registers = ich4_pm_registers;
size = ARRAY_SIZE(ich4_pm_registers);
break;
+ case PCI_DEVICE_ID_INTEL_ICH2:
+ pmbase = pci_read_word(sb, 0x40) 0xfffc;
+ pm_registers = ich2_pm_registers;
+ size = ARRAY_SIZE(ich2_pm_registers);
+ break;
case PCI_DEVICE_ID_INTEL_ICH0:
pmbase =
Re: [coreboot] rommcc bugs
Ah sorry I forgot one more file. Now it should be better.
But yes I got same error.
Thanks,
Rudolf
Index: src/include/ip_checksum.h
===
--- src/include/ip_checksum.h (revision 5631)
+++ src/include/ip_checksum.h (working copy)
@@ -1,7 +1,10 @@
#ifndef IP_CHECKSUM_H
#define IP_CHECKSUM_H
+#ifndef __ROMCC__
unsigned long compute_ip_checksum(void *addr, unsigned long length);
unsigned long add_ip_checksums(unsigned long offset, unsigned long sum, unsigned long new);
-
+void str2ip(const char *str, unsigned char *ip);
+void str2mac(const char *str, unsigned char *mac);
+#endif
#endif /* IP_CHECKSUM_H */
Index: src/include/console/ne2k.h
===
--- src/include/console/ne2k.h (revision 0)
+++ src/include/console/ne2k.h (revision 0)
@@ -0,0 +1,27 @@
+#ifndef _NE2K_H__
+#define _NE2K_H__
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Rudolf Marek r.ma...@assembler.cz
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef __ROMCC__
+void ne2k_append_data(unsigned char *d, int len, unsigned int base);
+int ne2k_init(unsigned int eth_nic_base);
+void ne2k_transmit(unsigned int eth_nic_base);
+#endif
+#endif /* _NE2K_H */
Index: src/include/console/console.h
===
--- src/include/console/console.h (revision 5631)
+++ src/include/console/console.h (working copy)
@@ -131,6 +131,10 @@
#include pc80/serial.c
+#if CONFIG_CONSOLE_NE2K
+#include lib/ne2k.c
+#endif
+
/* __ROMCC__ */
static void __console_tx_byte(unsigned char byte)
{
@@ -191,10 +195,18 @@
if (console_loglevel = loglevel) {
unsigned char ch;
while((ch = *str++) != '\0') {
+#if CONFIG_CONSOLE_NE2K
+ unsigned char *ptr;
+ ptr = (unsigned char *) (str - 1);
+ ne2k_append_data(ptr, 1, CONFIG_CONSOLE_NE2K_IO_PORT);
+#endif
if (ch == '\n')
__console_tx_byte('\r');
__console_tx_byte(ch);
}
+#if CONFIG_CONSOLE_NE2K
+ ne2k_transmit(CONFIG_CONSOLE_NE2K_IO_PORT);
+#endif
}
}
Index: src/mainboard/soyo/sy-6ba-plus-iii/romstage.c
===
--- src/mainboard/soyo/sy-6ba-plus-iii/romstage.c (revision 5631)
+++ src/mainboard/soyo/sy-6ba-plus-iii/romstage.c (working copy)
@@ -54,6 +54,8 @@
it8671f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
+ //ne2k_init(CONFIG_CONSOLE_NE2K_IO_PORT);
+
console_init();
report_bist_failure(bist);
Index: src/mainboard/asus/p2b/romstage.c.orig
===
Index: src/mainboard/asus/p2b/acpi_tables.c
===
Index: src/mainboard/asus/p2b/dsdt.asl
===
Index: src/console/Kconfig
===
--- src/console/Kconfig (revision 5631)
+++ src/console/Kconfig (working copy)
@@ -1,5 +1,4 @@
menu Console options
-
# TODO: Rename to SERIAL_CONSOLE once Kconfig transition is complete.
config CONSOLE_SERIAL8250
bool Serial port console output
@@ -130,6 +129,48 @@
help
If not selected, the last adapter found will be used.
+config CONSOLE_NE2K
+ bool Network console over NE2000 compatible Ethernet adapter
+ default y
+ help
+ Send coreboot debug output to a Ethernet console, it works
+ same way as Linux netconsole, packets are received to UDP
+ port on IP/MAC specified with options bellow.
+
+config CONSOLE_NE2K_DST_MAC
+ depends on CONSOLE_NE2K
+ string Destination MAC address of remote system
+ default 00:13:d4:76:a2:ac
+ help
+ Type in either MAC address of logging system or MAC address
+ of the router.
+
+config CONSOLE_NE2K_DST_IP
+ depends on CONSOLE_NE2K
+ string Destination IP of logging system
+ default 10.0.1.27
+ help
+ This is IP adress of the system running for example
+ netcat command to dump the packets.
+
+config CONSOLE_NE2K_SRC_IP
+ depends on CONSOLE_NE2K
+ string IP adress of Coreboot system
+ default 10.0.1.253
+ help
+ This is the IP of the Coreboot system
+
+config CONSOLE_NE2K_IO_PORT
+ depends on CONSOLE_NE2K
+ hex NE2000 adapter fixed IO port address
+ default 0xe00
+ help
+ This is the IO
Re: [coreboot] rommcc bugs
Sorry Rudolf, I forgot to copy the list.
It looks like romcc doesn't support unsigned char there. I did this:
- outb(datxa, eth_nic_base + NE_ASIC_OFFSET + NE_DATA);
+ outb((char)datxa, eth_nic_base + NE_ASIC_OFFSET + NE_DATA);
And it compiles again.
Here's the code from romcc.c:
static struct triple *int_const(
struct compile_state *state, struct type *type, ulong_t value)
{
struct triple *result;
switch(type-type TYPE_MASK) {
case TYPE_CHAR:
case TYPE_INT: case TYPE_UINT:
case TYPE_LONG: case TYPE_ULONG:
break;
default:
internal_error(state, 0, constant for unknown type);
}
result = triple(state, OP_INTCONST, type, 0, 0);
result-u.cval = value;
return result;
}
Thanks,
Myles
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] rommcc bugs
Hm, It does not work here. If i change it I still got mare...@kiur:~/dilna/coreboot$ make GENbuild.h ROMCC romstage.inc ne2k.c:83.0: warning: comment next line causes stuff to compile again ne2k.c:126.0: warning: Add timeout romstage.c:74.0: Internal compiler error: constant for unknown type make: *** [build/mainboard/soyo/sy-6ba-plus-iii/romstage.inc] Aborted outb((char)datxa, eth_nic_base + NE_ASIC_OFFSET + NE_DATA); this is how it looks now. Maybe you changed more? Thanks, Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] rommcc bugs
On Wed, Jun 16, 2010 at 4:03 PM, Rudolf Marek r.ma...@assembler.cz wrote: Hm, It does not work here. If i change it I still got You're right. I added TYPE_UCHAR: before: case TYPE_CHAR: case TYPE_INT: case TYPE_UINT: after: case TYPE_CHAR: case TYPE_UCHAR: case TYPE_INT: case TYPE_UINT: I don't know how safe that is, but it seems like it should work. I don't know the difference between constants that are unsigned or signed characters. In the past it's been better to work around romcc than modify it unless Eric helps. Sorry for the confusion. I thought I changed it back before I tried it last. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] i810E and ICH2 inteltool support
Great, thank you. Acked-by: Stefan Reinauer ste...@coresystems.de -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5632 - trunk/util/inteltool
Author: linux_junkie
Date: Thu Jun 17 00:21:19 2010
New Revision: 5632
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5632
Log:
This patch adds inteltool support for i810E and ICH2.
Signed-off-by: Joseph Smith j...@settoplinux.org
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/util/inteltool/gpio.c
trunk/util/inteltool/inteltool.c
trunk/util/inteltool/inteltool.h
trunk/util/inteltool/memory.c
trunk/util/inteltool/pcie.c
trunk/util/inteltool/powermgt.c
trunk/util/inteltool/rootcmplx.c
Modified: trunk/util/inteltool/gpio.c
==
--- trunk/util/inteltool/gpio.c Fri Jun 11 16:25:40 2010(r5631)
+++ trunk/util/inteltool/gpio.c Thu Jun 17 00:21:19 2010(r5632)
@@ -39,6 +39,25 @@
{ 0x3C, 4, RESERVED }
};
+static const io_register_t ich2_gpio_registers[] = {
+ { 0x00, 4, GPIO_USE_SEL },
+ { 0x04, 4, GP_IO_SEL },
+ { 0x08, 4, RESERVED },
+ { 0x0c, 4, GP_LVL },
+ { 0x10, 4, RESERVED },
+ { 0x14, 4, GPO_TTL },
+ { 0x18, 4, GPO_BLINK },
+ { 0x1c, 4, RESERVED },
+ { 0x20, 4, RESERVED },
+ { 0x24, 4, RESERVED },
+ { 0x28, 4, RESERVED },
+ { 0x2c, 4, GPI_INV },
+ { 0x30, 4, RESERVED },
+ { 0x34, 4, RESERVED },
+ { 0x38, 4, RESERVED },
+ { 0x3C, 4, RESERVED }
+};
+
static const io_register_t ich4_gpio_registers[] = {
{ 0x00, 4, GPIO_USE_SEL },
{ 0x04, 4, GP_IO_SEL },
@@ -176,6 +195,11 @@
gpio_registers = ich4_gpio_registers;
size = ARRAY_SIZE(ich4_gpio_registers);
break;
+ case PCI_DEVICE_ID_INTEL_ICH2:
+ gpiobase = pci_read_word(sb, 0x58) 0xfffc;
+ gpio_registers = ich2_gpio_registers;
+ size = ARRAY_SIZE(ich2_gpio_registers);
+ break;
case PCI_DEVICE_ID_INTEL_ICH:
case PCI_DEVICE_ID_INTEL_ICH0:
gpiobase = pci_read_word(sb, 0x58) 0xfffc;
Modified: trunk/util/inteltool/inteltool.c
==
--- trunk/util/inteltool/inteltool.cFri Jun 11 16:25:40 2010(r5631)
+++ trunk/util/inteltool/inteltool.cThu Jun 17 00:21:19 2010(r5632)
@@ -34,6 +34,7 @@
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, 82443BX
without AGP },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, i810 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, i810-DC100 },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_MC, i810E DC-133 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, i830M },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, i845 },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915,
82915G/P/GV/GL/PL/910GL },
Modified: trunk/util/inteltool/inteltool.h
==
--- trunk/util/inteltool/inteltool.hFri Jun 11 16:25:40 2010(r5631)
+++ trunk/util/inteltool/inteltool.hThu Jun 17 00:21:19 2010(r5632)
@@ -55,6 +55,7 @@
#define PCI_DEVICE_ID_INTEL_82810 0x7120
#define PCI_DEVICE_ID_INTEL_82810DC0x7122
+#define PCI_DEVICE_ID_INTEL_82810E_MC 0x7124
#define PCI_DEVICE_ID_INTEL_82830M 0x3575
#define PCI_DEVICE_ID_INTEL_82845 0x1a30
#define PCI_DEVICE_ID_INTEL_82915 0x2580
Modified: trunk/util/inteltool/memory.c
==
--- trunk/util/inteltool/memory.c Fri Jun 11 16:25:40 2010(r5631)
+++ trunk/util/inteltool/memory.c Thu Jun 17 00:21:19 2010(r5632)
@@ -50,6 +50,7 @@
case PCI_DEVICE_ID_INTEL_82443LX:
case PCI_DEVICE_ID_INTEL_82443BX:
case PCI_DEVICE_ID_INTEL_82810:
+ case PCI_DEVICE_ID_INTEL_82810E_MC:
case PCI_DEVICE_ID_INTEL_82810DC:
case PCI_DEVICE_ID_INTEL_82830M:
printf(This northbrigde does not have MCHBAR.\n);
Modified: trunk/util/inteltool/pcie.c
==
--- trunk/util/inteltool/pcie.c Fri Jun 11 16:25:40 2010(r5631)
+++ trunk/util/inteltool/pcie.c Thu Jun 17 00:21:19 2010(r5632)
@@ -49,6 +49,7 @@
break;
case PCI_DEVICE_ID_INTEL_82810:
case PCI_DEVICE_ID_INTEL_82810DC:
+ case PCI_DEVICE_ID_INTEL_82810E_MC:
case PCI_DEVICE_ID_INTEL_82830M:
printf(This northbrigde does not have EPBAR.\n);
return 1;
@@ -102,6 +103,7 @@
break;
case PCI_DEVICE_ID_INTEL_82810:
case PCI_DEVICE_ID_INTEL_82810DC:
+ case PCI_DEVICE_ID_INTEL_82810E_MC:
printf(This northbrigde does not have DMIBAR.\n);
return 1;
default:
@@ -156,6 +158,7 @@
Re: [coreboot] [PATCH] i810E and ICH2 inteltool support
On 06/16/2010 06:18 PM, Stefan Reinauer wrote: Great, thank you. Acked-by: Stefan Reinauerste...@coresystems.de Thanks r5632 -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Strange ROMCC failure with Rev 5623
On Wed, Jun 16, 2010 at 12:06 PM, Myles Watson myle...@gmail.com wrote:
On Wed, Jun 16, 2010 at 12:00 PM, Myles Watson myle...@gmail.com wrote:
When compiling asus/p2b (and several others), Rev 5622 succeeds, but 5623
fails.
make: *** [build/mainboard/asus/p2b/romstage.inc] Segmentation fault
make: *** Deleting file `build/mainboard/asus/p2b/romstage.inc'
The only difference for these boards is this line in config.h:
#define CONFIG_VENDOR_ECS 0
Removing this line lets 5623 build correctly.
Removing any line from the file that doesn't affect the build works.
(CONFIG_VENDOR_*, CONFIG_DEFAULT_CONSOLE_LEVEL_*, etc.)
Program received signal SIGSEGV, Segmentation fault.
0x00423bbe in free_basic_block (state=0x7fff5dbcbb20, block=0x1392ff0)
at /home/myles/try/buildrom-devel/work/coreboot/svn/util/romcc/romcc.c:15165
15165 if (child (child-vertex != -1)) {
(gdb) print child
$1 = (struct block *) 0x1c95950
(gdb) print child-vertex
Cannot access memory at address 0x1c959b8
Thanks,
Myles
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Re: [coreboot] Strange ROMCC failure with Rev 5623
On Wed, Jun 16, 2010 at 4:34 PM, Myles Watson myle...@gmail.com wrote:
On Wed, Jun 16, 2010 at 12:06 PM, Myles Watson myle...@gmail.com wrote:
On Wed, Jun 16, 2010 at 12:00 PM, Myles Watson myle...@gmail.com wrote:
When compiling asus/p2b (and several others), Rev 5622 succeeds, but 5623
fails.
make: *** [build/mainboard/asus/p2b/romstage.inc] Segmentation fault
make: *** Deleting file `build/mainboard/asus/p2b/romstage.inc'
The only difference for these boards is this line in config.h:
#define CONFIG_VENDOR_ECS 0
Removing this line lets 5623 build correctly.
Removing any line from the file that doesn't affect the build works.
(CONFIG_VENDOR_*, CONFIG_DEFAULT_CONSOLE_LEVEL_*, etc.)
Program received signal SIGSEGV, Segmentation fault.
0x00423bbe in free_basic_block (state=0x7fff5dbcbb20, block=0x1392ff0)
at
/home/myles/try/buildrom-devel/work/coreboot/svn/util/romcc/romcc.c:15165
15165 if (child (child-vertex != -1)) {
(gdb) print child
$1 = (struct block *) 0x1c95950
(gdb) print child-vertex
Cannot access memory at address 0x1c959b8
It looks like Patrick found this before:
http://www.coreboot.org/pipermail/coreboot/2009-November/054387.html
If I take out the free it works fine. It seems like there must be a better fix.
Thanks,
Myles
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Re: [coreboot] request for comments: Gigabyte GA-945PL-S3 (rev. 1.0)
On 16/06/10 22:00, John Wyzer wrote: Board: Gigabyte GA-945PL-S3 (rev. 1.0) For the BIOS: I looked around and saw that SST25VF040.REMS cannot be written yet. I'd be willing to buy a few, desolder the current one and volunteer to run flashrom via trial and error (in August). Would that help or is someone already working on something equivalent? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Simplify device enabling and initialization
On Wed, Jun 16, 2010 at 02:50:42PM -0600, Myles Watson wrote: This patch breaks the s2881, which was doing some odd acrobatics in order to get a device initialized after its parent. It should be an easy fix to do it correctly now, but I don't have an s2881 to test on. Ward? Yep, I've got (the guts) of an s2881 lying on my desk here, and can test any patches you throw at me :) Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Strange ROMCC failure with Rev 5623
Myles Watson myle...@gmail.com writes:
On Wed, Jun 16, 2010 at 4:34 PM, Myles Watson myle...@gmail.com wrote:
On Wed, Jun 16, 2010 at 12:06 PM, Myles Watson myle...@gmail.com wrote:
On Wed, Jun 16, 2010 at 12:00 PM, Myles Watson myle...@gmail.com wrote:
When compiling asus/p2b (and several others), Rev 5622 succeeds, but 5623
fails.
make: *** [build/mainboard/asus/p2b/romstage.inc] Segmentation fault
make: *** Deleting file `build/mainboard/asus/p2b/romstage.inc'
The only difference for these boards is this line in config.h:
#define CONFIG_VENDOR_ECS 0
Removing this line lets 5623 build correctly.
Removing any line from the file that doesn't affect the build works.
(CONFIG_VENDOR_*, CONFIG_DEFAULT_CONSOLE_LEVEL_*, etc.)
Program received signal SIGSEGV, Segmentation fault.
0x00423bbe in free_basic_block (state=0x7fff5dbcbb20,
block=0x1392ff0)
at
/home/myles/try/buildrom-devel/work/coreboot/svn/util/romcc/romcc.c:15165
15165 if (child (child-vertex != -1)) {
(gdb) print child
$1 = (struct block *) 0x1c95950
(gdb) print child-vertex
Cannot access memory at address 0x1c959b8
It looks like Patrick found this before:
http://www.coreboot.org/pipermail/coreboot/2009-November/054387.html
If I take out the free it works fine. It seems like there must be a better
fix.
Agreed.
I took a look at this a little bit with Stefan and he helped me track where
the double free is.
The routine doing the freeing badly needs to be rewritten to use simpler logic
as the recursive logic it is using now just doesn't work, and it winds
up to be a bit of a crap shoot if your compile gets killed by this or not.
Eric
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[coreboot] AMD740G - Not supported yet?
I noticed that there is still a request for AMD740G chipset info almost a year later after I first posted some info regarding it. Is it in limbo now? Cheers, Gary -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
