Re: [coreboot] [patch] Added dependency checking for the USB EHCI debug Kconfig option
On Sun, 2010-06-20 at 02:00 +0200, Stefan Reinauer wrote: On 6/19/10 11:48 PM, Cristi Magherusan wrote: See attached patch. I had to add that ifdef because config.h didn't have defined the CONFIG_USBDEBUG_DIRECT option and compilation failed. If anyone has an idea how I can get it defined there, I'm all ears. Why not just leave it as it is? Someone might plug an USB2 card into a system that doesn't have the chip onboard. Stefan Compilation fails if you select the option and the support is not implemented. If anyone wants to use the device with another motherboard, he could easily mark it as supported by adding it to this list after the support code done. Regards, Cristi -- Cristi Măgherușan, alumnus System/Network Engineer Technical University of Cluj-Napoca, Romania http://cc.utcluj.ro +40264 401247 signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] i810 GFXUMA and Northbridge fixes
On 6/20/10 7:59 AM, Joseph Smith wrote:
+ if (CONFIG_VIDEO_MB == 512) {
+ igd_memory = (CONFIG_VIDEO_MB);
+ printk(BIOS_DEBUG, %dKB IGD UMA\n, igd_memory 10);
+ } else {
+ igd_memory = (CONFIG_VIDEO_MB * 1024);
+ printk(BIOS_DEBUG, %dMB IGD UMA\n, igd_memory 10);
+ }
You might want to read the SMRAM register intead of relying on the
setting of the config variable in case an invalid value sneaked in.
Other than that:
Acked-by: Stefan Reinauer ste...@coresystems.de
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Re: [coreboot] [PATCH] New Socket370 and Model 68x for CAR
On 6/20/10 10:04 AM, Joseph Smith wrote:
Hello,
This patch adds a new socket for FCPGA370 and PGA370 CPU's. This new
socket (called socket_FC_PGA370) will make the CAR transition alot
easier. When done transitioning all the boards and cpu's the old
socket_PGA370 (kind of misleading for the FC's) can be deleted as well
as model_6xx. I will be testing a bunch of 370 cpu's this week so
hopefully the model_6xx will be no longer needed. This patch also
includes first CAR support for model_68x FCPGA CPU's.
Build and boot tested.
Signed-off by: Joseph Smith j...@settoplinux.org
with two caveats:
Acked-by: Stefan Reinauer ste...@coresystems.de
Index: src/cpu/intel/Kconfig
===
--- src/cpu/intel/Kconfig (revision 5634)
+++ src/cpu/intel/Kconfig (working copy)
@@ -17,6 +18,7 @@
source src/cpu/intel/bga956/Kconfig
source src/cpu/intel/slot_2/Kconfig
source src/cpu/intel/slot_1/Kconfig
+source src/cpu/intel/socket_FC_PGA370/Kconfig
FCPGA
Index: src/cpu/intel/Makefile.inc
===
--- src/cpu/intel/Makefile.inc(revision 5634)
+++ src/cpu/intel/Makefile.inc(working copy)
@@ -6,6 +6,7 @@
subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441
subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += bga956
subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_FC_PGA370) += socket_FC_PGA370
FCPGA
Index: src/cpu/intel/socket_FC_PGA370/Kconfig
===
--- src/cpu/intel/socket_FC_PGA370/Kconfig(revision 0)
+++ src/cpu/intel/socket_FC_PGA370/Kconfig(revision 0)
+
+config CPU_INTEL_SOCKET_FC_PGA370
FCPGA
Index: src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c
===
--- src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c (revision 0)
+++ src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c (revision 0)
@@ -0,0 +1,26 @@
+
+#include device/device.h
+#include chip.h
+
+struct chip_operations cpu_intel_socket_FC_PGA370_ops = {
FCPGA
+ CHIP_NAME((FC)PGA370 CPU)
+};
Index: src/cpu/intel/socket_FC_PGA370/Makefile.inc
===
--- src/cpu/intel/socket_FC_PGA370/Makefile.inc (revision 0)
+++ src/cpu/intel/socket_FC_PGA370/Makefile.inc (revision 0)
@@ -0,0 +1,30 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Joseph Smith j...@settoplinux.org
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+obj-y += socket_FC_PGA370.o
FCPGA
+
+extern struct chip_operations cpu_intel_socket_FC_PGA370_ops;
+
+struct cpu_intel_socket_FC_PGA370_config {
+};
This should be FCPGA370 or mFCPGA370
Index: src/cpu/intel/model_68x/model_68x_init.c
===
--- src/cpu/intel/model_68x/model_68x_init.c (revision 0)
+++ src/cpu/intel/model_68x/model_68x_init.c (revision 0)
[..]
+
+static struct cpu_device_id cpu_table[] = {
Do add 680 here too. In fact, if you add 680 all the others can be omitted.
+ { X86_VENDOR_INTEL, 0x0681 },
+ { X86_VENDOR_INTEL, 0x0683 },
+ { X86_VENDOR_INTEL, 0x0686 },
+ { X86_VENDOR_INTEL, 0x068a },
+ { 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+ .ops = cpu_dev_ops,
+ .id_table = cpu_table,
+};
+
--
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Re: [coreboot] [PATCH] Support for Intel D810E2CB (i810e/ICH2)
Hello, This patch adds support for the Intel D810E2CB desktop board. This patch has to go in after the other two patches I have submitted, it is dependent on them. Hurray, this is the first i810 board running CAR :-) Build and boot (bootlog attached) tested: Signed-off by: Joseph Smith j...@settoplinux.org Acked-by: Stefan Reinauer ste...@coresystems.de with some caveats: Index: src/mainboard/intel/d810e2cb/gpio.c === --- src/mainboard/intel/d810e2cb/gpio.c (revision 0) +++ src/mainboard/intel/d810e2cb/gpio.c (revision 0) @@ -0,0 +1,212 @@ +#define ICH_IO_BASE_ADDR 0x0500 /* GPIO base address register */ This is duplicated from i82801ax_lpc.c ... Can it go into i82801ax.h and be included here instead? (It's also called GPIO_BASE_ADDRESS elsewhere) + + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(dev, 0x58, (ICH_IO_BASE_ADDR | 1)); + pci_write_config8(dev, 0x5c, 0x10); + 0x58 is GPIO_BASE_ICH0_5 in i82801ax.h (should be renamed to GPIO_BASE I guess) + udelay(10); Index: src/mainboard/intel/d810e2cb/Kconfig === --- src/mainboard/intel/d810e2cb/Kconfig (revision 0) +++ src/mainboard/intel/d810e2cb/Kconfig (revision 0) @@ -0,0 +1,65 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Joseph Smith j...@settoplinux.org +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_INTEL_D810E2CB + bool D810E2CB + select ARCH_X86 + select CPU_INTEL_SOCKET_FC_PGA370 + select NORTHBRIDGE_INTEL_I82810 + select SOUTHBRIDGE_INTEL_I82801BX + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select UDELAY_TSC + select BOARD_ROMSIZE_KB_512 + select HAVE_MAINBOARD_RESOURCES + select USE_PRINTK_IN_CAR can this go into the CPU's Kconfig? + select GFXUMA + select USE_DCACHE_RAM And this, too? + select TINY_BOOTBLOCK And this? + +config MAINBOARD_DIR + string + default intel/d810e2cb + depends on BOARD_INTEL_D810E2CB + +config MAINBOARD_PART_NUMBER + string + default D810E2CB + depends on BOARD_INTEL_D810E2CB + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_INTEL_D810E2CB + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + depends on BOARD_INTEL_D810E2CB And this. + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_INTEL_D810E2CB + And this. +config IRQ_SLOT_COUNT + int + default 7 + depends on BOARD_INTEL_D810E2CB + Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] i810 GFXUMA and Northbridge fixes
On 06/20/2010 07:37 AM, Stefan Reinauer wrote:
On 6/20/10 7:59 AM, Joseph Smith wrote:
+ if (CONFIG_VIDEO_MB == 512) {
+ igd_memory = (CONFIG_VIDEO_MB);
+ printk(BIOS_DEBUG, %dKB IGD UMA\n, igd_memory 10);
+ } else {
+ igd_memory = (CONFIG_VIDEO_MB * 1024);
+ printk(BIOS_DEBUG, %dMB IGD UMA\n, igd_memory 10);
+ }
You might want to read the SMRAM register intead of relying on the
setting of the config variable in case an invalid value sneaked in.
Other than that:
Acked-by: Stefan Reinauer ste...@coresystems.de
Ok, I can do that :-)
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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Re: [coreboot] [PATCH] New Socket370 and Model 68x for CAR
On 06/20/2010 07:46 AM, Stefan Reinauer wrote:
On 6/20/10 10:04 AM, Joseph Smith wrote:
Hello,
This patch adds a new socket for FCPGA370 and PGA370 CPU's. This new
socket (called socket_FC_PGA370) will make the CAR transition alot
easier. When done transitioning all the boards and cpu's the old
socket_PGA370 (kind of misleading for the FC's) can be deleted as well
as model_6xx. I will be testing a bunch of 370 cpu's this week so
hopefully the model_6xx will be no longer needed. This patch also
includes first CAR support for model_68x FCPGA CPU's.
Build and boot tested.
Signed-off by: Joseph Smith j...@settoplinux.org
with two caveats:
Acked-by: Stefan Reinauer ste...@coresystems.de
Index: src/cpu/intel/Kconfig
===
--- src/cpu/intel/Kconfig (revision 5634)
+++ src/cpu/intel/Kconfig (working copy)
@@ -17,6 +18,7 @@
source src/cpu/intel/bga956/Kconfig
source src/cpu/intel/slot_2/Kconfig
source src/cpu/intel/slot_1/Kconfig
+source src/cpu/intel/socket_FC_PGA370/Kconfig
FCPGA
I wanted to keep them separated because Socket 370 supports PGA370 and
FCPGA370 processors, this way they are both covered.
Index: src/cpu/intel/Makefile.inc
===
--- src/cpu/intel/Makefile.inc (revision 5634)
+++ src/cpu/intel/Makefile.inc (working copy)
@@ -6,6 +6,7 @@
subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441
subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += bga956
subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_FC_PGA370) += socket_FC_PGA370
FCPGA
Index: src/cpu/intel/socket_FC_PGA370/Kconfig
===
--- src/cpu/intel/socket_FC_PGA370/Kconfig (revision 0)
+++ src/cpu/intel/socket_FC_PGA370/Kconfig (revision 0)
+
+config CPU_INTEL_SOCKET_FC_PGA370
FCPGA
Index: src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c
===
--- src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c (revision 0)
+++ src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c (revision 0)
@@ -0,0 +1,26 @@
+
+#includedevice/device.h
+#include chip.h
+
+struct chip_operations cpu_intel_socket_FC_PGA370_ops = {
FCPGA
+ CHIP_NAME((FC)PGA370 CPU)
+};
Index: src/cpu/intel/socket_FC_PGA370/Makefile.inc
===
--- src/cpu/intel/socket_FC_PGA370/Makefile.inc (revision 0)
+++ src/cpu/intel/socket_FC_PGA370/Makefile.inc (revision 0)
@@ -0,0 +1,30 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Joseph Smithj...@settoplinux.org
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; either version 2 of the License, or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+obj-y += socket_FC_PGA370.o
FCPGA
+
+extern struct chip_operations cpu_intel_socket_FC_PGA370_ops;
+
+struct cpu_intel_socket_FC_PGA370_config {
+};
This should be FCPGA370 or mFCPGA370
No, m means mobile chip. Socket 370 is not a mobile chip.
Index: src/cpu/intel/model_68x/model_68x_init.c
===
--- src/cpu/intel/model_68x/model_68x_init.c(revision 0)
+++ src/cpu/intel/model_68x/model_68x_init.c(revision 0)
[..]
+
+static struct cpu_device_id cpu_table[] = {
Do add 680 here too. In fact, if you add 680 all the others can be omitted.
ok, why? 680 will cover everything?
+ { X86_VENDOR_INTEL, 0x0681 },
+ { X86_VENDOR_INTEL, 0x0683 },
+ { X86_VENDOR_INTEL, 0x0686 },
+ { X86_VENDOR_INTEL, 0x068a },
+ { 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+ .ops =cpu_dev_ops,
+ .id_table = cpu_table,
+};
+
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
--
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Re: [coreboot] [PATCH] New Socket370 and Model 68x for CAR
On 20.06.2010, at 14:44, Joseph Smith j...@settoplinux.org wrote:
On 06/20/2010 07:46 AM, Stefan Reinauer wrote:
On 6/20/10 10:04 AM, Joseph Smith wrote:
Hello,
This patch adds a new socket for FCPGA370 and PGA370 CPU's. This new
socket (called socket_FC_PGA370) will make the CAR transition alot
easier. When done transitioning all the boards and cpu's the old
socket_PGA370 (kind of misleading for the FC's) can be deleted as
well
as model_6xx. I will be testing a bunch of 370 cpu's this week so
hopefully the model_6xx will be no longer needed. This patch also
includes first CAR support for model_68x FCPGA CPU's.
Build and boot tested.
Signed-off by: Joseph Smith j...@settoplinux.org
with two caveats:
Acked-by: Stefan Reinauer ste...@coresystems.de
Index: src/cpu/intel/Kconfig
===
--- src/cpu/intel/Kconfig(revision 5634)
+++ src/cpu/intel/Kconfig(working copy)
@@ -17,6 +18,7 @@
source src/cpu/intel/bga956/Kconfig
source src/cpu/intel/slot_2/Kconfig
source src/cpu/intel/slot_1/Kconfig
+source src/cpu/intel/socket_FC_PGA370/Kconfig
FCPGA
I wanted to keep them separated because Socket 370 supports PGA370
and FCPGA370 processors, this way they are both covered.
Hm ok
Index: src/cpu/intel/Makefile.inc
===
--- src/cpu/intel/Makefile.inc(revision 5634)
+++ src/cpu/intel/Makefile.inc(working copy)
@@ -6,6 +6,7 @@
subdirs-$(CONFIG_CPU_INTEL_SOCKET_441) += socket_441
subdirs-$(CONFIG_CPU_INTEL_SOCKET_BGA956) += bga956
subdirs-$(CONFIG_CPU_INTEL_EP80579) += ep80579
+subdirs-$(CONFIG_CPU_INTEL_SOCKET_FC_PGA370) += socket_FC_PGA370
FCPGA
Index: src/cpu/intel/socket_FC_PGA370/Kconfig
===
--- src/cpu/intel/socket_FC_PGA370/Kconfig(revision 0)
+++ src/cpu/intel/socket_FC_PGA370/Kconfig(revision 0)
+
+config CPU_INTEL_SOCKET_FC_PGA370
FCPGA
Index: src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c
===
--- src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c(revision
0)
+++ src/cpu/intel/socket_FC_PGA370/socket_FC_PGA370.c(revision
0)
@@ -0,0 +1,26 @@
+
+#includedevice/device.h
+#include chip.h
+
+struct chip_operations cpu_intel_socket_FC_PGA370_ops = {
FCPGA
+CHIP_NAME((FC)PGA370 CPU)
+};
Index: src/cpu/intel/socket_FC_PGA370/Makefile.inc
===
--- src/cpu/intel/socket_FC_PGA370/Makefile.inc(revision 0)
+++ src/cpu/intel/socket_FC_PGA370/Makefile.inc(revision 0)
@@ -0,0 +1,30 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2010 Joseph Smithj...@settoplinux.org
+##
+## This program is free software; you can redistribute it and/or
modify
+## it under the terms of the GNU General Public License as
published by
+## the Free Software Foundation; either version 2 of the License,
or
+## (at your option) any later version.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public
License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
02110-1301 USA
+##
+
+obj-y += socket_FC_PGA370.o
FCPGA
+
+extern struct chip_operations cpu_intel_socket_FC_PGA370_ops;
+
+struct cpu_intel_socket_FC_PGA370_config {
+};
This should be FCPGA370 or mFCPGA370
No, m means mobile chip. Socket 370 is not a mobile chip.
Afaik the m in mfcpga means micro
Index: src/cpu/intel/model_68x/model_68x_init.c
===
--- src/cpu/intel/model_68x/model_68x_init.c(revision 0)
+++ src/cpu/intel/model_68x/model_68x_init.c(revision 0)
[..]
+
+static struct cpu_device_id cpu_table[] = {
Do add 680 here too. In fact, if you add 680 all the others can be
omitted.
ok, why? 680 will cover everything?
Yes. It will mask the ID with fff0
+{ X86_VENDOR_INTEL, 0x0681 },
+{ X86_VENDOR_INTEL, 0x0683 },
+{ X86_VENDOR_INTEL, 0x0686 },
+{ X86_VENDOR_INTEL, 0x068a },
+{ 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+.ops =cpu_dev_ops,
+.id_table = cpu_table,
+};
+
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
--
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Re: [coreboot] [PATCH] Support for Intel D810E2CB (i810e/ICH2)
On 06/20/2010 07:55 AM, Stefan Reinauer wrote: Hello, This patch adds support for the Intel D810E2CB desktop board. This patch has to go in after the other two patches I have submitted, it is dependent on them. Hurray, this is the first i810 board running CAR :-) Build and boot (bootlog attached) tested: Signed-off by: Joseph Smith j...@settoplinux.org Acked-by: Stefan Reinauer ste...@coresystems.de with some caveats: Index: src/mainboard/intel/d810e2cb/gpio.c === --- src/mainboard/intel/d810e2cb/gpio.c (revision 0) +++ src/mainboard/intel/d810e2cb/gpio.c (revision 0) @@ -0,0 +1,212 @@ +#define ICH_IO_BASE_ADDR 0x0500 /* GPIO base address register */ This is duplicated from i82801ax_lpc.c ... Can it go into i82801ax.h and be included here instead? (It's also called GPIO_BASE_ADDRESS elsewhere) You mean i82801bx_lpc.c? Sure, can I have a big i82801bx cleanup patch coming, it may be easier to just do it then? + + /* Set the value for GPIO base address register and enable GPIO. */ + pci_write_config32(dev, 0x58, (ICH_IO_BASE_ADDR | 1)); + pci_write_config8(dev, 0x5c, 0x10); + 0x58 is GPIO_BASE_ICH0_5 in i82801ax.h (should be renamed to GPIO_BASE I guess) Yes like I said i82801bx code is still a mess from the ich seperation. + udelay(10); Index: src/mainboard/intel/d810e2cb/Kconfig === --- src/mainboard/intel/d810e2cb/Kconfig(revision 0) +++ src/mainboard/intel/d810e2cb/Kconfig(revision 0) @@ -0,0 +1,65 @@ +## +## This file is part of the coreboot project. +## +## Copyright (C) 2010 Joseph Smithj...@settoplinux.org +## +## This program is free software; you can redistribute it and/or modify +## it under the terms of the GNU General Public License as published by +## the Free Software Foundation; version 2 of the License. +## +## This program is distributed in the hope that it will be useful, +## but WITHOUT ANY WARRANTY; without even the implied warranty of +## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +## GNU General Public License for more details. +## +## You should have received a copy of the GNU General Public License +## along with this program; if not, write to the Free Software +## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +## + +config BOARD_INTEL_D810E2CB + bool D810E2CB + select ARCH_X86 + select CPU_INTEL_SOCKET_FC_PGA370 + select NORTHBRIDGE_INTEL_I82810 + select SOUTHBRIDGE_INTEL_I82801BX + select SUPERIO_SMSC_SMSCSUPERIO + select HAVE_PIRQ_TABLE + select UDELAY_TSC + select BOARD_ROMSIZE_KB_512 + select HAVE_MAINBOARD_RESOURCES + select USE_PRINTK_IN_CAR can this go into the CPU's Kconfig? Sure, it would make life easier for me when switching over the other i810 boards. + select GFXUMA + select USE_DCACHE_RAM And this, too? + select TINY_BOOTBLOCK And this? + +config MAINBOARD_DIR + string + default intel/d810e2cb + depends on BOARD_INTEL_D810E2CB + +config MAINBOARD_PART_NUMBER + string + default D810E2CB + depends on BOARD_INTEL_D810E2CB + +config HAVE_OPTION_TABLE + bool + default n + depends on BOARD_INTEL_D810E2CB + +config DCACHE_RAM_BASE + hex + default 0xffdf8000 + depends on BOARD_INTEL_D810E2CB And this. + +config DCACHE_RAM_SIZE + hex + default 0x8000 + depends on BOARD_INTEL_D810E2CB + And this. +config IRQ_SLOT_COUNT + int + default 7 + depends on BOARD_INTEL_D810E2CB + Stefan -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] New Socket370 and Model 68x for CAR
This should be FCPGA370 or mFCPGA370
No, m means mobile chip. Socket 370 is not a mobile chip.
Afaik the m in mfcpga means micro
Ah yes sorry. No the Socket 370 is still not a micro or mobile chip.
Index: src/cpu/intel/model_68x/model_68x_init.c
===
--- src/cpu/intel/model_68x/model_68x_init.c (revision 0)
+++ src/cpu/intel/model_68x/model_68x_init.c (revision 0)
[..]
+
+static struct cpu_device_id cpu_table[] = {
Do add 680 here too. In fact, if you add 680 all the others can be
omitted.
ok, why? 680 will cover everything?
Yes. It will mask the ID with fff0
ok
+ { X86_VENDOR_INTEL, 0x0681 },
+ { X86_VENDOR_INTEL, 0x0683 },
+ { X86_VENDOR_INTEL, 0x0686 },
+ { X86_VENDOR_INTEL, 0x068a },
+ { 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+ .ops =cpu_dev_ops,
+ .id_table = cpu_table,
+};
+
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
--
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[coreboot] [commit] r5635 - in trunk/src: mainboard/asus/mew-am mainboard/asus/mew-vm mainboard/ecs/p6iwp-fe mainboard/hp/e_vectra_p2706t mainboard/mitac/6513wu mainboard/msi/ms6178 mainboard/nec/powe
Author: linux_junkie
Date: Sun Jun 20 20:59:40 2010
New Revision: 5635
URL: https://tracker.coreboot.org/trac/coreboot/changeset/5635
Log:
This patch implements GFXUMA on all supported i810 boards. Also some fix-ups to
the i810 northbridge.c code.
Signed-off-by: Joseph Smith j...@settoplinux.org
Acked-by: Stefan Reinauer ste...@coresystems.de
Modified:
trunk/src/mainboard/asus/mew-am/Kconfig
trunk/src/mainboard/asus/mew-am/mainboard.c
trunk/src/mainboard/asus/mew-vm/Kconfig
trunk/src/mainboard/asus/mew-vm/mainboard.c
trunk/src/mainboard/ecs/p6iwp-fe/Kconfig
trunk/src/mainboard/ecs/p6iwp-fe/mainboard.c
trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig
trunk/src/mainboard/hp/e_vectra_p2706t/mainboard.c
trunk/src/mainboard/mitac/6513wu/Kconfig
trunk/src/mainboard/mitac/6513wu/mainboard.c
trunk/src/mainboard/msi/ms6178/Kconfig
trunk/src/mainboard/msi/ms6178/mainboard.c
trunk/src/mainboard/nec/powermate2000/Kconfig
trunk/src/mainboard/nec/powermate2000/mainboard.c
trunk/src/northbridge/intel/i82810/northbridge.c
Modified: trunk/src/mainboard/asus/mew-am/Kconfig
==
--- trunk/src/mainboard/asus/mew-am/Kconfig Sat Jun 19 08:55:17 2010
(r5634)
+++ trunk/src/mainboard/asus/mew-am/Kconfig Sun Jun 20 20:59:40 2010
(r5635)
@@ -28,6 +28,8 @@
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
+ select HAVE_MAINBOARD_RESOURCES
+ select GFXUMA
config MAINBOARD_DIR
string
Modified: trunk/src/mainboard/asus/mew-am/mainboard.c
==
--- trunk/src/mainboard/asus/mew-am/mainboard.c Sat Jun 19 08:55:17 2010
(r5634)
+++ trunk/src/mainboard/asus/mew-am/mainboard.c Sun Jun 20 20:59:40 2010
(r5635)
@@ -19,8 +19,14 @@
*/
#include device/device.h
+#include boot/tables.h
#include chip.h
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return add_northbridge_resources(mem);
+}
+
struct chip_operations mainboard_ops = {
CHIP_NAME(ASUS MEW-AM Mainboard)
};
Modified: trunk/src/mainboard/asus/mew-vm/Kconfig
==
--- trunk/src/mainboard/asus/mew-vm/Kconfig Sat Jun 19 08:55:17 2010
(r5634)
+++ trunk/src/mainboard/asus/mew-vm/Kconfig Sun Jun 20 20:59:40 2010
(r5635)
@@ -28,6 +28,8 @@
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
+ select HAVE_MAINBOARD_RESOURCES
+ select GFXUMA
config MAINBOARD_DIR
string
Modified: trunk/src/mainboard/asus/mew-vm/mainboard.c
==
--- trunk/src/mainboard/asus/mew-vm/mainboard.c Sat Jun 19 08:55:17 2010
(r5634)
+++ trunk/src/mainboard/asus/mew-vm/mainboard.c Sun Jun 20 20:59:40 2010
(r5635)
@@ -1,6 +1,12 @@
#include device/device.h
+#include boot/tables.h
#include chip.h
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return add_northbridge_resources(mem);
+}
+
struct chip_operations mainboard_ops = {
CHIP_NAME(ASUS MEW-VM Mainboard)
};
Modified: trunk/src/mainboard/ecs/p6iwp-fe/Kconfig
==
--- trunk/src/mainboard/ecs/p6iwp-fe/KconfigSat Jun 19 08:55:17 2010
(r5634)
+++ trunk/src/mainboard/ecs/p6iwp-fe/KconfigSun Jun 20 20:59:40 2010
(r5635)
@@ -29,6 +29,8 @@
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
+ select HAVE_MAINBOARD_RESOURCES
+ select GFXUMA
config MAINBOARD_DIR
string
Modified: trunk/src/mainboard/ecs/p6iwp-fe/mainboard.c
==
--- trunk/src/mainboard/ecs/p6iwp-fe/mainboard.cSat Jun 19 08:55:17
2010(r5634)
+++ trunk/src/mainboard/ecs/p6iwp-fe/mainboard.cSun Jun 20 20:59:40
2010(r5635)
@@ -19,8 +19,14 @@
*/
#include device/device.h
+#include boot/tables.h
#include chip.h
+int add_mainboard_resources(struct lb_memory *mem)
+{
+ return add_northbridge_resources(mem);
+}
+
struct chip_operations mainboard_ops = {
CHIP_NAME(ECS P6IWP-Fe Mainboard)
};
Modified: trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig
==
--- trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig Sat Jun 19 08:55:17
2010(r5634)
+++ trunk/src/mainboard/hp/e_vectra_p2706t/Kconfig Sun Jun 20 20:59:40
2010(r5635)
@@ -31,6 +31,8 @@
select HAVE_PIRQ_TABLE
select UDELAY_TSC
select BOARD_ROMSIZE_KB_512
+ select HAVE_MAINBOARD_RESOURCES
+ select GFXUMA
config MAINBOARD_DIR
string
Modified:
Re: [coreboot] [PATCH] i810 GFXUMA and Northbridge fixes
On 06/20/2010 07:37 AM, Stefan Reinauer wrote:
On 6/20/10 7:59 AM, Joseph Smith wrote:
+ if (CONFIG_VIDEO_MB == 512) {
+ igd_memory = (CONFIG_VIDEO_MB);
+ printk(BIOS_DEBUG, %dKB IGD UMA\n, igd_memory 10);
+ } else {
+ igd_memory = (CONFIG_VIDEO_MB * 1024);
+ printk(BIOS_DEBUG, %dMB IGD UMA\n, igd_memory 10);
+ }
You might want to read the SMRAM register intead of relying on the
setting of the config variable in case an invalid value sneaked in.
Other than that:
Acked-by: Stefan Reinauer ste...@coresystems.de
Done, thanks. r5635
--
Thanks,
Joseph Smith
Set-Top-Linux
www.settoplinux.org
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[coreboot] Geode GX2 CAR.
Hi all,
I ported the Geode LX Cache As Ram code to GX2.
It works nice and it reduces the boot time with ~35 seconds.
Though there is a piece of code i would like some more information on.
It is in /src/northbridge/amd/lx/raminit.c :
/* SWAPSiF for PBZ 4112 (Errata 34) */
/* check for failed DLL settings now that we have done a memory write. */
msrnum = GLCP_DELAY_CONTROLS;
msr = rdmsr(msrnum);
if ((msr.lo 0x7FF) == 0x104) {
/* If you had it you would need to clear out the fail boot count flag */
/* (depending on where it counts from etc). */
/* The reset we are about to perform clears the PM_SSC register in the */
/* 5536 so will need to store the S3 resume flag in NVRAM otherwise */
/* it would do a normal boot */
/* Reset the system */
msrnum = MDD_SOFT_RESET;
msr = rdmsr(msrnum);
msr.lo |= 1;
wrmsr(msrnum, msr);
I omitted this routine in my patch because i could not find a description
about PBZ 4112 (Errata 34) and according to the LX databook the tested bit 8
is Reserved.
My questions are:
1. Where could i find information on Errata 34 ?
2.Would a similar test be needed/desired for GX2 ?
Thanks,Nils.
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Re: [coreboot] [PATCH] Simplify device enabling and initialization
Hi Myles, Everything seems fine with either patch - but there are some differences in the boot output. I also ran the 'sensors' command. Output here: http://ward.vandewege.net/coreboot/s2881/20100617-myles/ I ran 4 tests: stock r5635 (head), stock r5632 (revision prior to this changeset), r5635 + patch 1 and r5635 + patch 2. Let me know if you need anything else... Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
