Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?
On Fri, Aug 20, 2010 at 8:32 AM, Oskar Enoksson e...@lysator.liu.se wrote: Myles Watson wrote: I'll send the updated patch when I'm at the office in the morning. I want to say also: this code should probably be regarded as experimental. I already know it doesn't boot with Opteron 248 CPU's, and sometimes it hangs on my 280 CPU's also. I don't remember seeing the boot logs. Have you compared the failing boot logs with the working ones? I think I solved a problem with the memory (mux) initialization (memreset and memreset_setup), now I can safely boot on both the 2x 248 server and the 2x 280 server. Good news. But I noticed that memtest86+ hangs. After some trial-and-error I noticed that if I use CONFIG_WRITE_HIGH_TABLES=y then everything works fine in Linux, but memtest86+ hangs. If I use CONFIG_WRITE_HIGH_TABLES=n memtest86+ works fine, but the Linux kernel fails to initialize the ethernet NIC's. What could be wrong? My guess is that memtest doesn't like the reserved area in the middle of RAM, but I don't know for sure. The original BIOS reports this memory map: BIOS-e820: - 0009fc00 (usable) BIOS-e820: 0009fc00 - 000a (reserved) BIOS-e820: 000e - 0010 (reserved) BIOS-e820: 0010 - f9ff (usable) BIOS-e820: f9ff - f9fff000 (ACPI data) BIOS-e820: f9fff000 - fa00 (ACPI NVS) BIOS-e820: ffb8 - 0001 (reserved) My coreboot reports: BIOS-e820: - 0009fc00 (usable) BIOS-e820: 0009fc00 - 000a (reserved) BIOS-e820: 000f - 0010 (reserved) BIOS-e820: 0010 - 7fff (usable) BIOS-e820: 7fff - 8000 (reserved) BIOS-e820: 8000 - f7fff000 (usable) BIOS-e820: f7fff000 - f800 (reserved) Is there something that looks wrong with the coreboot table? I'm surprised that the high tables ended up in the middle of RAM. I'd reccommend looking through the log to see why that area gets reserved there (is it reserved twice?) One more oddity that could be related: when booting with coreboot and then running flashrom I always get an error like this: flashrom is free software, get the source code at http://www.flashrom.org Error accessing high tables, 0x10 bytes at 0x7fff2000 Odd that it wants to acess 1M of high tables at an unaligned address. /dev/mem mmap failed: Invalid argument In Linux this error can be caused by the CONFIG_NONPROMISC_DEVMEM (2.6.27), CONFIG_STRICT_DEVMEM (=2.6.27) and CONFIG_X86_PAT kernel options. Please check if either is enabled in your kernel before reporting a failure. You can override CONFIG_X86_PAT at boot with the nopat kernel parameter but disabling the other option unfortunately requires a kernel recompile. Sorry! Failed getting access to coreboot high tables. Found chipset AMD AMD8111, enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... delay loop is unreliable, trying to continue OK. Found chip SST SST49LF040 (512 KB, LPC) at physical address 0xfff8. It works though and I can write to the flash. With the factory BIOS there are no error messages: flashrom is free software, get the source code at http://www.flashrom.org No coreboot table found. Found chipset AMD AMD8111, enabling flash write... OK. This chipset supports the following protocols: Non-SPI. Calibrating delay loop... OK. Found chip SST SST49LF040 (512 KB, LPC) at physical address 0xfff8. Using the mailing list will generally get you a better response and help others later. Thanks, Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?
Oskar Enoksson wrote: Myles Watson wrote: I think Myles was right, there is a i2c mux in this server that somehow multiplexes DIMM devices on the i2c bus. I was able to guess which i2c ports contain the DIMM info, and which port is the mux, then added the mux to devicetree.cb and the DIMM ports under it. Now I'm able to use memory from both CPU's, at least for the combination of DIMM's I have (2x2x1GB and 2x2x512MB). I'm glad it worked out! So I'm basically able to use these servers now. I would love to have ACPI and Cool'nQuiet of course, perhaps I'll try to do that later. Thanks very much for all help! If you want me to commit the new mainboard to your svn repository let me know. Yes, please. If you'll send your latest patch with a Signed-off-by: line, I'll take it from there. Thanks, Myles I hope this file is the way you want it. I did svn cp src/mainboard/tyan/s2881 src/mainboard/hp/dl145_g1 and then modified the files, then svn diff src/mainboard so I assume you should do the same svn cp operation, then apply my patch, then commit to retain the original files' history. I have fixed several problems and now it boots reliably for both and older dual Opteron 248 server and an upgraded dual Opteron 280 server. memtest86+ doesn't work, but according to another mailinglist thread memtest cannot handle tables in high memory, so that seems to be a memtest issue. Attached is a cleaned-up patch. Thanks to Myles and others for excellent help and support. I hope someone finds the result useful. Signed-off-by: Oskar Enoksson osk...@foi.se Index: src/mainboard/hp/Kconfig === --- src/mainboard/hp/Kconfig (revision 5719) +++ src/mainboard/hp/Kconfig (working copy) @@ -2,6 +2,7 @@ prompt Mainboard model depends on VENDOR_HP +source src/mainboard/hp/dl145_g1/Kconfig source src/mainboard/hp/dl145_g3/Kconfig source src/mainboard/hp/e_vectra_p2706t/Kconfig Index: src/mainboard/hp/dl145_g1/Kconfig === --- src/mainboard/hp/dl145_g1/Kconfig (revision 5719) +++ src/mainboard/hp/dl145_g1/Kconfig (working copy) @@ -1,5 +1,5 @@ -config BOARD_TYAN_S2881 - bool S2881 (Thunder K8SR) +config BOARD_HP_DL145_G1 + bool ProLiant DL145 G1 select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 @@ -13,65 +13,69 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select DRIVERS_SIL_3114 +# select SB_HT_CHAIN_UNITID_OFFSET_ONLY config MAINBOARD_DIR string - default tyan/s2881 - depends on BOARD_TYAN_S2881 + default hp/dl145_g1 + depends on BOARD_HP_DL145_G1 config APIC_ID_OFFSET hex default 0x0 - depends on BOARD_TYAN_S2881 + depends on BOARD_HP_DL145_G1 config SB_HT_CHAIN_ON_BUS0 int default 2 - depends on BOARD_TYAN_S2881 + depends on BOARD_HP_DL145_G1 config MAINBOARD_PART_NUMBER string - default S2881 - depends on BOARD_TYAN_S2881 + default ProLiant DL145 G1 + depends on BOARD_HP_DL145_G1 +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1022 + depends on BOARD_HP_DL145_G1 + config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex - default 0x2881 - depends on BOARD_TYAN_S2881 + default 0x7460 + depends on BOARD_HP_DL145_G1 config HW_MEM_HOLE_SIZEK hex default 0x10 - depends on BOARD_TYAN_S2881 + depends on BOARD_HP_DL145_G1 config MAX_CPUS int default 4 - depends on BOARD_TYAN_S2881 + depends on BOARD_HP_DL145_G1 config MAX_PHYSICAL_CPUS int default 2 - depends on BOARD_TYAN_S2881 + depends on BOARD_HP_DL145_G1 config HW_MEM_HOLE_SIZE_AUTO_INC bool default n - depends on BOARD_TYAN_S2881 + depends on BOARD_HP_DL145_G1 config HT_CHAIN_UNITID_BASE hex - default 0xa - depends on BOARD_TYAN_S2881 + default 0x1 + depends on BOARD_HP_DL145_G1 config HT_CHAIN_END_UNITID_BASE hex default 0x6 - depends on BOARD_TYAN_S2881 + depends on BOARD_HP_DL145_G1 config IRQ_SLOT_COUNT int default 9 - depends on BOARD_TYAN_S2881 + depends on BOARD_HP_DL145_G1 Index: src/mainboard/hp/dl145_g1/devicetree.cb === --- src/mainboard/hp/dl145_g1/devicetree.cb (revision 5719) +++ src/mainboard/hp/dl145_g1/devicetree.cb (working copy) @@ -11,30 +11,29 @@ device pci 18.0 on # link 2 chip southbridge/amd/amd8131 # the on/off keyword is mandatory - device pci 0.0 on -device pci 9.0 on end # Broadcom 5704 -device pci 9.1 on end -device pci a.0 on end # Adaptic -device pci a.1 on end - end + device pci 0.0 on end device pci 0.1 on end device pci 1.0 on end device pci 1.1 on end + device pci 2.0 on end + device pci 2.1 on end + device pci 3.0 off end
[coreboot] [commit] r5723 - in trunk/src/mainboard/hp: . dl145_g1
Author: myles Date: Fri Aug 20 22:37:27 2010 New Revision: 5723 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5723 Log: Add support for the HP DL145 G1, based on the Tyan s2881. Signed-off-by: Oskar Enoksson osk...@foi.se Acked-by: Myles Watson myle...@gmail.com Added: trunk/src/mainboard/hp/dl145_g1/ - copied from r5722, trunk/src/mainboard/tyan/s2881/ Modified: trunk/src/mainboard/hp/Kconfig trunk/src/mainboard/hp/dl145_g1/Kconfig trunk/src/mainboard/hp/dl145_g1/Makefile.inc trunk/src/mainboard/hp/dl145_g1/devicetree.cb trunk/src/mainboard/hp/dl145_g1/mainboard.c trunk/src/mainboard/hp/dl145_g1/mptable.c trunk/src/mainboard/hp/dl145_g1/resourcemap.c trunk/src/mainboard/hp/dl145_g1/romstage.c Modified: trunk/src/mainboard/hp/Kconfig == --- trunk/src/mainboard/hp/Kconfig Wed Aug 18 23:23:27 2010(r5722) +++ trunk/src/mainboard/hp/Kconfig Fri Aug 20 22:37:27 2010(r5723) @@ -2,6 +2,7 @@ prompt Mainboard model depends on VENDOR_HP +source src/mainboard/hp/dl145_g1/Kconfig source src/mainboard/hp/dl145_g3/Kconfig source src/mainboard/hp/e_vectra_p2706t/Kconfig Modified: trunk/src/mainboard/hp/dl145_g1/Kconfig == --- trunk/src/mainboard/tyan/s2881/Kconfig Wed Aug 18 23:23:27 2010 (r5722) +++ trunk/src/mainboard/hp/dl145_g1/Kconfig Fri Aug 20 22:37:27 2010 (r5723) @@ -1,5 +1,5 @@ -config BOARD_TYAN_S2881 - bool S2881 (Thunder K8SR) +config BOARD_HP_DL145_G1 + bool ProLiant DL145 G1 select ARCH_X86 select CPU_AMD_SOCKET_940 select NORTHBRIDGE_AMD_AMDK8 @@ -13,65 +13,69 @@ select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select BOARD_ROMSIZE_KB_512 - select SB_HT_CHAIN_UNITID_OFFSET_ONLY - select DRIVERS_SIL_3114 +# select SB_HT_CHAIN_UNITID_OFFSET_ONLY config MAINBOARD_DIR string - default tyan/s2881 - depends on BOARD_TYAN_S2881 + default hp/dl145_g1 + depends on BOARD_HP_DL145_G1 config APIC_ID_OFFSET hex default 0x0 - depends on BOARD_TYAN_S2881 + depends on BOARD_HP_DL145_G1 config SB_HT_CHAIN_ON_BUS0 int default 2 - depends on BOARD_TYAN_S2881 + depends on BOARD_HP_DL145_G1 config MAINBOARD_PART_NUMBER string - default S2881 - depends on BOARD_TYAN_S2881 + default ProLiant DL145 G1 + depends on BOARD_HP_DL145_G1 + +config MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID + hex + default 0x1022 + depends on BOARD_HP_DL145_G1 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID hex - default 0x2881 - depends on BOARD_TYAN_S2881 + default 0x7460 + depends on BOARD_HP_DL145_G1 config HW_MEM_HOLE_SIZEK hex default 0x10 - depends on BOARD_TYAN_S2881 + depends on BOARD_HP_DL145_G1 config MAX_CPUS int default 4 - depends on BOARD_TYAN_S2881 + depends on BOARD_HP_DL145_G1 config MAX_PHYSICAL_CPUS int default 2 - depends on BOARD_TYAN_S2881 + depends on BOARD_HP_DL145_G1 config HW_MEM_HOLE_SIZE_AUTO_INC bool default n - depends on BOARD_TYAN_S2881 + depends on BOARD_HP_DL145_G1 config HT_CHAIN_UNITID_BASE hex - default 0xa - depends on BOARD_TYAN_S2881 + default 0x1 + depends on BOARD_HP_DL145_G1 config HT_CHAIN_END_UNITID_BASE hex default 0x6 - depends on BOARD_TYAN_S2881 + depends on BOARD_HP_DL145_G1 config IRQ_SLOT_COUNT int default 9 - depends on BOARD_TYAN_S2881 + depends on BOARD_HP_DL145_G1 Modified: trunk/src/mainboard/hp/dl145_g1/Makefile.inc == --- trunk/src/mainboard/tyan/s2881/Makefile.inc Wed Aug 18 23:23:27 2010 (r5722) +++ trunk/src/mainboard/hp/dl145_g1/Makefile.incFri Aug 20 22:37:27 2010(r5723) @@ -1 +1 @@ -obj-y += ../../../drivers/i2c/adt7463/adt7463.o +obj-y += ../../../drivers/i2c/i2cmux/i2cmux.o \ No newline at end of file Modified: trunk/src/mainboard/hp/dl145_g1/devicetree.cb == --- trunk/src/mainboard/tyan/s2881/devicetree.cbWed Aug 18 23:23:27 2010(r5722) +++ trunk/src/mainboard/hp/dl145_g1/devicetree.cb Fri Aug 20 22:37:27 2010(r5723) @@ -11,30 +11,29 @@ device pci 18.0 on # link 2 chip southbridge/amd/amd8131 # the on/off keyword is mandatory - device pci 0.0 on -device pci 9.0 on end # Broadcom 5704 -device pci 9.1 on end -device pci a.0 on end # Adaptic -device pci a.1 on end -
Re: [coreboot] DL145 G1 with dual dualcore CPU using coreboot ?
Attached is a cleaned-up patch. Thanks to Myles and others for excellent help and support. I hope someone finds the result useful. Rev 5723. Thanks for contributing! Myles -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r5724 - trunk/src/mainboard/hp/dl145_g1
Author: myles Date: Fri Aug 20 22:45:04 2010 New Revision: 5724 URL: https://tracker.coreboot.org/trac/coreboot/changeset/5724 Log: Remove a couple of warnings. Trivial. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson myle...@gmail.com Modified: trunk/src/mainboard/hp/dl145_g1/mptable.c trunk/src/mainboard/hp/dl145_g1/romstage.c Modified: trunk/src/mainboard/hp/dl145_g1/mptable.c == --- trunk/src/mainboard/hp/dl145_g1/mptable.c Fri Aug 20 22:37:27 2010 (r5723) +++ trunk/src/mainboard/hp/dl145_g1/mptable.c Fri Aug 20 22:45:04 2010 (r5724) @@ -29,8 +29,6 @@ unsigned char bus_num; - int i; - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); memset(mc, 0, sizeof(*mc)); Modified: trunk/src/mainboard/hp/dl145_g1/romstage.c == --- trunk/src/mainboard/hp/dl145_g1/romstage.c Fri Aug 20 22:37:27 2010 (r5723) +++ trunk/src/mainboard/hp/dl145_g1/romstage.c Fri Aug 20 22:45:04 2010 (r5724) @@ -95,7 +95,6 @@ #include northbridge/amd/amdk8/raminit.c #include resourcemap.c -#include northbridge/amd/amdk8/resourcemap.c #include northbridge/amd/amdk8/coherent_ht.c #include lib/generic_sdram.c -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r5723
Dear coreboot readers! This is the automatic build system of coreboot. The developer myles checked in revision 5723 to the coreboot repository. This caused the following changes: Change Log: Add support for the HP DL145 G1, based on the Tyan s2881. Signed-off-by: Oskar Enoksson osk...@foi.se Acked-by: Myles Watson myle...@gmail.com Build Log: Compilation of hp:dl145_g1 is still broken See the error log at http://qa.coreboot.org/log_buildbrd.php?revision=5723device=dl145_g1vendor=hpnum=2 If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] build service results for r5724
Dear coreboot readers! This is the automatic build system of coreboot. The developer myles checked in revision 5724 to the coreboot repository. This caused the following changes: Change Log: Remove a couple of warnings. Trivial. Signed-off-by: Myles Watson myle...@gmail.com Acked-by: Myles Watson myle...@gmail.com Build Log: Compilation of hp:dl145_g1 has been fixed If something broke during this checkin please be a pain in myles's neck until the issue is fixed. If this issue is not fixed within 24h the revision should be backed out. Best regards, coreboot automatic build system -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] Gigabyte MA785GMT support
Hi Niels, On Sat, Aug 14, 2010 at 01:38:26AM +0800, Qing Pei Wang wrote: In my eyes, you can flash the M_BIOS with coreboot. It should not need any hardware modification. Although i did some of them, but they are just used to let me find out the problems of dual bios things Qing Pei is right, no hardware modification necessary. I started a page on the MA785GMT-UD2H that explains how to recover from an unbootable M_BIOS, by using the B_BIOS feature. It boils down to shorting pins 4 (GND) and 7 (#HOLD) on the M_BIOS chip for a few seconds on cold boot, and then releasing the short. See http://www.coreboot.org/GIGABYTE_GA-MA785GMT-UD2H Thanks, Ward. -- Ward Vandewege w...@gnu.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
