Re: [coreboot] MCP55 Mac Address copying/change
Harald Gutmann wrote:
Just for my personal interest, could someone explain me what
actually is called romstrap?
It's a horrible name for permanent settings that are stored in the
boot flash.
Is there any fast method to read the onboards NIC mac address faster?
ip l sh eth0|grep link/ether|awk '{print $2}'
//Peter
--
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Re: [coreboot] [RFC]Static testing of our tree
Patrick Georgi wrote: I propose to store this script (and similar ones) somewhere under util/, and hook them up in the Makefile (make lint?) and in the autobuilder (qa.coreboot.org), and have that report failure if they return any output. How long does it take to run? As soon as there are no more warnings I think it should be in the commit hook. //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Trac reminder: list of new ticket(s)
Ticket Owner Status Description #168 ste...@coresystems.de new USBDEBUG might slow down coreboot #162 oxygene new Move SYSTEM_TYPE to Kconfig #160 oxygene new Build system: There's no convincing CFLAGS management for util/* #158 w...@gnu.org new buildrom svn error #156 hailfinger new Add Layout File capability to v3 and LAR tool #154 hailfinger new Flashing BIOSes from Fujitsu/Siemens is not supported #150 somebody new AMD DB800 dev board PLL strapping leaves CPU and GLIU in non-optimal clock #147 somebody new Linux kernel halts when scanning the PCI bus below 0:14.4 on RS690 #145 somebody new Fix CMOS handling #143 oxygene new unify intel car for model_6[ef]x #135 ward new Flashrom deletes MAC addresses on Tyan Tomcat n3400B (S2925-E) #129 stepan new etherboot payload does not work with HIGH_TABLES #128 somebody new Improve email user interface for trac #125 somebody new BCM5785 / HT1000 reset functions #111 somebody new Add i18n support for translating strings e.g. for bayou / coreinfo #110 somebody new Allow for per-device subsystem IDs #77 somebody new hang on the "Jumping to coreboot" step on via epia-m with 4-chip 128Mbyte DDR module #76 rminnich new coreboot messages should be accessible in dmesg #18 oxygene new autoprobe apic cluster and application processors on K8 systems #17 stepan new clean up coreboot table handling #16 ollie new I2C driver and mainboard Config.lb #11 yhlu new pirq table automation #5 uwe new Add license header to all source files #2 somebody new Complete tables of supported motherboards -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r6047 - in trunk/src/superio/ite: it8661f it8671f it8673f it8705f it8712f it8716f it8718f
Author: uwe Date: Mon Nov 8 16:16:30 2010 New Revision: 6047 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6047 Log: Random ITE Super I/O fixes. - Drop some of the less useful / outdated / duplicated comments. - Simplify and streamline some code to look like the other Super I/Os. - Use u8/16/etc. everywhere. - ITE IT8718F: Add missing GPIO LDN. - Add missing braces around SIO_DATA #defines, potential bug even. Signed-off-by: Uwe Hermann u...@hermann-uwe.de Acked-by: Uwe Hermann u...@hermann-uwe.de Modified: trunk/src/superio/ite/it8661f/Makefile.inc trunk/src/superio/ite/it8661f/chip.h trunk/src/superio/ite/it8661f/it8661f.h trunk/src/superio/ite/it8661f/it8661f_early_serial.c trunk/src/superio/ite/it8661f/superio.c trunk/src/superio/ite/it8671f/Makefile.inc trunk/src/superio/ite/it8671f/chip.h trunk/src/superio/ite/it8671f/it8671f.h trunk/src/superio/ite/it8671f/it8671f_early_serial.c trunk/src/superio/ite/it8671f/superio.c trunk/src/superio/ite/it8673f/Makefile.inc trunk/src/superio/ite/it8673f/chip.h trunk/src/superio/ite/it8673f/it8673f.h trunk/src/superio/ite/it8673f/it8673f_early_serial.c trunk/src/superio/ite/it8673f/superio.c trunk/src/superio/ite/it8705f/Makefile.inc trunk/src/superio/ite/it8705f/chip.h trunk/src/superio/ite/it8705f/it8705f.h trunk/src/superio/ite/it8705f/it8705f_early_serial.c trunk/src/superio/ite/it8705f/superio.c trunk/src/superio/ite/it8712f/Makefile.inc trunk/src/superio/ite/it8712f/chip.h trunk/src/superio/ite/it8712f/it8712f.h trunk/src/superio/ite/it8712f/it8712f_early_serial.c trunk/src/superio/ite/it8712f/superio.c trunk/src/superio/ite/it8716f/Makefile.inc trunk/src/superio/ite/it8716f/chip.h trunk/src/superio/ite/it8716f/it8716f.h trunk/src/superio/ite/it8716f/it8716f_early_init.c trunk/src/superio/ite/it8716f/it8716f_early_serial.c trunk/src/superio/ite/it8716f/superio.c trunk/src/superio/ite/it8718f/Makefile.inc trunk/src/superio/ite/it8718f/chip.h trunk/src/superio/ite/it8718f/it8718f.h trunk/src/superio/ite/it8718f/it8718f_early_serial.c trunk/src/superio/ite/it8718f/superio.c Modified: trunk/src/superio/ite/it8661f/Makefile.inc == --- trunk/src/superio/ite/it8661f/Makefile.inc Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8661f/Makefile.inc Mon Nov 8 16:16:30 2010 (r6047) @@ -18,5 +18,5 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -#config chip.h ramstage-$(CONFIG_SUPERIO_ITE_IT8661F) += superio.c + Modified: trunk/src/superio/ite/it8661f/chip.h == --- trunk/src/superio/ite/it8661f/chip.hSun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8661f/chip.hMon Nov 8 16:16:30 2010 (r6047) @@ -18,10 +18,10 @@ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA */ -#ifndef _SUPERIO_ITE_IT8661F -#define _SUPERIO_ITE_IT8661F +#ifndef SUPERIO_ITE_IT8661F_CHIP_H +#define SUPERIO_ITE_IT8661F_CHIP_H -/* This chip doesn't seem to have keyboard and mouse support. */ +/* This chip doesn't have keyboard and mouse support. */ #include device/device.h #include uart8250.h @@ -32,4 +32,4 @@ struct uart8250 com1, com2; }; -#endif /* _SUPERIO_ITE_IT8661F */ +#endif Modified: trunk/src/superio/ite/it8661f/it8661f.h == --- trunk/src/superio/ite/it8661f/it8661f.h Sun Nov 7 21:11:39 2010 (r6046) +++ trunk/src/superio/ite/it8661f/it8661f.h Mon Nov 8 16:16:30 2010 (r6047) @@ -19,9 +19,6 @@ */ /* Datasheet: http://www.ite.com.tw/product_info/PC/Brief-IT8661_2.asp */ -/* Status: Untested on real hardware, but it compiles. */ - -/* This chip doesn't seem to have keyboard and mouse support. */ #define IT8661F_FDC 0x00 /* Floppy */ #define IT8661F_SP1 0x01 /* Com1 */ Modified: trunk/src/superio/ite/it8661f/it8661f_early_serial.c == --- trunk/src/superio/ite/it8661f/it8661f_early_serial.cSun Nov 7 21:11:39 2010(r6046) +++ trunk/src/superio/ite/it8661f/it8661f_early_serial.cMon Nov 8 16:16:30 2010(r6047) @@ -24,7 +24,7 @@ /* The base address is 0x3f0, 0x3bd, or 0x370, depending on config bytes. */ #define SIO_BASE 0x3f0 #define SIO_INDEX SIO_BASE -#define SIO_DATA SIO_BASE+1 +#define SIO_DATA (SIO_BASE + 1) /* Global configuration registers. */ #define IT8661F_CONFIG_REG_CC 0x02 /* Configure Control (write-only). */ @@ -34,18 +34,18 @@ #define IT8661F_CONFIGURATION_PORT 0x0279 /* Write-only. */ -/* Special values used for entering MB PnP
Re: [coreboot] coreboot on dell mini 9
The i945 chipset is supported. It will be some work to get that Dell supported but if you want to try adding a new port, there are two similar laptops in the tree already Stefan On 07.11.2010, at 07:09, HacKurx hack...@gmail.com wrote: Hello, Is it possible to install coreboot on dell mini9? I enclose my command to see. Thank you for your help and sorry for my English. - [hack...@admin ~]$ su root Mot de passe : [r...@admin hackurx]# cd Dell-mini9/ [r...@admin Dell-mini9]# lspci -nnvvv lscpi.log [r...@admin Dell-mini9]# lspnp -vv lspnp.log Commande non trouvée [r...@admin Dell-mini9]# lsusb -vvv lsusb.log [r...@admin Dell-mini9]# superiotool -deV superiotool.log [r...@admin Dell-mini9]# inteltool -a inteltool.log [r...@admin Dell-mini9]# ectool ectool.log [r...@admin Dell-mini9]# msrtool msrtool.log msrtool 5566 Detected system linux: Linux with /dev/cpu/*/msr Unable to detect a known target; can not decode any MSRs! (Use -t to force) Please send a report or patch to coreb...@coreboot.org. Thanks for your help! [r...@admin Dell-mini9]# msrtool -t msrtool.log msrtool: option requires an argument -- 't' msrtool 5566 Detected system linux: Linux with /dev/cpu/*/msr Unable to detect a known target; can not decode any MSRs! (Use -t to force) Please send a report or patch to coreb...@coreboot.org. Thanks for your help! [r...@admin Dell-mini9]# msrtool --t msrtool.log msrtool: invalid option -- '-' msrtool: option requires an argument -- 't' msrtool 5566 Detected system linux: Linux with /dev/cpu/*/msr Unable to detect a known target; can not decode any MSRs! (Use -t to force) Please send a report or patch to coreb...@coreboot.org. Thanks for your help! [r...@admin Dell-mini9]# msrtool t msrtool.log msrtool 5566 Detected system linux: Linux with /dev/cpu/*/msr Unable to detect a known target; can not decode any MSRs! (Use -t to force) Please send a report or patch to coreb...@coreboot.org. Thanks for your help! [r...@admin Dell-mini9]# msrtool -t msrtool.log msrtool: option requires an argument -- 't' msrtool 5566 Detected system linux: Linux with /dev/cpu/*/msr Unable to detect a known target; can not decode any MSRs! (Use -t to force) Please send a report or patch to coreb...@coreboot.org. Thanks for your help! [r...@admin Dell-mini9]# dmidecode dmidecode.log [r...@admin Dell-mini9]# biosdecode biosdecode.log [r...@admin Dell-mini9]# nvramtool -x nvramtool.log [r...@admin Dell-mini9]# dmesg dmesg.log [r...@admin Dell-mini9]# flashrom -V -p internal:laptop=force_I_want_a_brick flashrom_info.log WARNING! You seem to be running flashrom on a laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. Proceeding anyway because user specified laptop=force_I_want_a_brick [r...@admin Dell-mini9]# flashrom -V -p internal:laptop=force_I_want_a_brick -r rom.bin flashrom_read.log WARNING! You seem to be running flashrom on a laptop. Laptops, notebooks and netbooks are difficult to support and we recommend to use the vendor flashing utility. The embedded controller (EC) in these machines often interacts badly with flashing. See http://www.flashrom.org/Laptops for details. If flash is shared with the EC, erase is guaranteed to brick your laptop and write may brick your laptop. Read and probe may irritate your EC and cause fan failure, backlight failure and sudden poweroff. You have been warned. Proceeding anyway because user specified laptop=force_I_want_a_brick [r...@admin Dell-mini9]# biosdecode.log dmesg.log dmidecode.log ectool.log flashrom_info.log flashrom_read.log inteltool.log lscpi.log lsusb.log nvramtool.log superiotool.log -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r6048 - trunk/src/southbridge/nvidia/mcp55
Author: ward
Date: Mon Nov 8 18:41:43 2010
New Revision: 6048
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6048
Log:
We can't print this early.
This patch fixes a hang on
supermicro/h8dme
supermicro/h8dmr
supermicro/h8dmr_fam10
and possibly on other mcp55-based boards.
Signed-off-by: Ward Vandewege w...@gnu.org
Acked-by: Peter Stuge pe...@stuge.se
Modified:
trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
Modified: trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c
==
--- trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c Mon Nov 8
16:16:30 2010(r6047)
+++ trunk/src/southbridge/nvidia/mcp55/mcp55_early_smbus.c Mon Nov 8
18:41:43 2010(r6048)
@@ -32,11 +32,8 @@
device_t dev;
dev = pci_locate_device(PCI_ID(0x10de, 0x0368), 0);
- if (dev == PCI_DEV_INVALID) {
- printk(BIOS_WARNING, SMBUS controller not found\n);
- } else {
- printk(BIOS_DEBUG, SMBus controller enabled\n);
- }
+ if (dev == PCI_DEV_INVALID)
+ die(SMBus controller not found\n);
/* set smbus iobase */
pci_write_config32(dev, 0x20, SMBUS0_IO_BASE | 1);
--
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Re: [coreboot] [PATCH] don't print too early on mcp55-based boards
On Mon, Nov 01, 2010 at 11:01:41PM +0100, Peter Stuge wrote: Ward Vandewege wrote: See attached. Perhaps we should also print a post code if the SMBus controller can't be found - suggestions for a value? 0x5B ? Let's do that as part of the die modification. We can't print this early. This patch fixes a hang on supermicro/h8dme supermicro/h8dmr supermicro/h8dmr_fam10 and possibly on other mcp55-based boards. Signed-off-by: Ward Vandewege w...@gnu.org Acked-by: Peter Stuge pe...@stuge.se r6048. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r6049 - in trunk/src/superio: fintek/f71805f fintek/f71859 fintek/f71863fg fintek/f71889 intel/i3100 ite/it8661f ite/it8671f ite/it8673f ite/it8705f ite/it8712f ite/it8716f ite/it8
Author: uwe
Date: Mon Nov 8 21:55:24 2010
New Revision: 6049
URL: https://tracker.coreboot.org/trac/coreboot/changeset/6049
Log:
Add #include guards to all Super I/O header files (trivial).
Signed-off-by: Uwe Hermann u...@hermann-uwe.de
Acked-by: Uwe Hermann u...@hermann-uwe.de
Modified:
trunk/src/superio/fintek/f71805f/chip.h
trunk/src/superio/fintek/f71805f/f71805f.h
trunk/src/superio/fintek/f71859/chip.h
trunk/src/superio/fintek/f71859/f71859.h
trunk/src/superio/fintek/f71863fg/chip.h
trunk/src/superio/fintek/f71863fg/f71863fg.h
trunk/src/superio/fintek/f71889/chip.h
trunk/src/superio/fintek/f71889/f71889.h
trunk/src/superio/intel/i3100/i3100.h
trunk/src/superio/ite/it8661f/it8661f.h
trunk/src/superio/ite/it8671f/it8671f.h
trunk/src/superio/ite/it8673f/it8673f.h
trunk/src/superio/ite/it8705f/it8705f.h
trunk/src/superio/ite/it8712f/it8712f.h
trunk/src/superio/ite/it8716f/it8716f.h
trunk/src/superio/ite/it8718f/it8718f.h
trunk/src/superio/nsc/pc8374/chip.h
trunk/src/superio/nsc/pc8374/pc8374.h
trunk/src/superio/nsc/pc87309/chip.h
trunk/src/superio/nsc/pc87309/pc87309.h
trunk/src/superio/nsc/pc87351/chip.h
trunk/src/superio/nsc/pc87351/pc87351.h
trunk/src/superio/nsc/pc87360/chip.h
trunk/src/superio/nsc/pc87360/pc87360.h
trunk/src/superio/nsc/pc87366/chip.h
trunk/src/superio/nsc/pc87366/pc87366.h
trunk/src/superio/nsc/pc87417/chip.h
trunk/src/superio/nsc/pc87417/pc87417.h
trunk/src/superio/nsc/pc87427/chip.h
trunk/src/superio/nsc/pc87427/pc87427.h
trunk/src/superio/nsc/pc97307/chip.h
trunk/src/superio/nsc/pc97307/pc97307.h
trunk/src/superio/nsc/pc97317/chip.h
trunk/src/superio/nsc/pc97317/pc97317.h
trunk/src/superio/renesas/m3885x/chip.h
trunk/src/superio/serverengines/pilot/pilot.h
trunk/src/superio/smsc/fdc37m60x/chip.h
trunk/src/superio/smsc/fdc37m60x/fdc37m60x.h
trunk/src/superio/smsc/fdc37n972/chip.h
trunk/src/superio/smsc/fdc37n972/fdc37n972.h
trunk/src/superio/smsc/lpc47b272/chip.h
trunk/src/superio/smsc/lpc47b272/lpc47b272.h
trunk/src/superio/smsc/lpc47b397/chip.h
trunk/src/superio/smsc/lpc47b397/lpc47b397.h
trunk/src/superio/smsc/lpc47m10x/chip.h
trunk/src/superio/smsc/lpc47m10x/lpc47m10x.h
trunk/src/superio/smsc/lpc47m15x/chip.h
trunk/src/superio/smsc/lpc47m15x/lpc47m15x.h
trunk/src/superio/smsc/lpc47n217/chip.h
trunk/src/superio/smsc/lpc47n217/lpc47n217.h
trunk/src/superio/smsc/lpc47n227/chip.h
trunk/src/superio/smsc/lpc47n227/lpc47n227.h
trunk/src/superio/smsc/sio10n268/chip.h
trunk/src/superio/smsc/sio10n268/sio10n268.h
trunk/src/superio/smsc/smscsuperio/Makefile.inc
trunk/src/superio/smsc/smscsuperio/chip.h
trunk/src/superio/via/vt1211/vt1211.h
trunk/src/superio/winbond/w83627dhg/chip.h
trunk/src/superio/winbond/w83627dhg/w83627dhg.h
trunk/src/superio/winbond/w83627ehg/chip.h
trunk/src/superio/winbond/w83627ehg/w83627ehg.h
trunk/src/superio/winbond/w83627hf/chip.h
trunk/src/superio/winbond/w83627hf/w83627hf.h
trunk/src/superio/winbond/w83627thf/chip.h
trunk/src/superio/winbond/w83627thf/w83627thf.h
trunk/src/superio/winbond/w83627thg/chip.h
trunk/src/superio/winbond/w83627thg/w83627thg.h
trunk/src/superio/winbond/w83627uhg/chip.h
trunk/src/superio/winbond/w83627uhg/w83627uhg.h
trunk/src/superio/winbond/w83697hf/chip.h
trunk/src/superio/winbond/w83697hf/w83697hf.h
trunk/src/superio/winbond/w83977f/chip.h
trunk/src/superio/winbond/w83977f/w83977f.h
trunk/src/superio/winbond/w83977tf/chip.h
trunk/src/superio/winbond/w83977tf/w83977tf.h
Modified: trunk/src/superio/fintek/f71805f/chip.h
==
--- trunk/src/superio/fintek/f71805f/chip.h Mon Nov 8 18:41:43 2010
(r6048)
+++ trunk/src/superio/fintek/f71805f/chip.h Mon Nov 8 21:55:24 2010
(r6049)
@@ -18,6 +18,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef SUPERIO_FINTEK_F71805F_CHIP_H
+#define SUPERIO_FINTEK_F71805F_CHIP_H
+
#include device/device.h
#include uart8250.h
@@ -28,3 +31,5 @@
struct superio_fintek_f71805f_config {
struct uart8250 com1, com2;
};
+
+#endif
Modified: trunk/src/superio/fintek/f71805f/f71805f.h
==
--- trunk/src/superio/fintek/f71805f/f71805f.h Mon Nov 8 18:41:43 2010
(r6048)
+++ trunk/src/superio/fintek/f71805f/f71805f.h Mon Nov 8 21:55:24 2010
(r6049)
@@ -18,6 +18,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef SUPERIO_FINTEK_F71805F_F71805F_H
+#define SUPERIO_FINTEK_F71805F_F71805F_H
+
/*
* Datasheet:
* - Name: F71805F/FG Super H/W Monitor + LPC IO
@@ -34,3 +37,5 @@
#defineF71805F_HWM 0x04/* Hardware monitor */
#defineF71805F_GPIO0x06/* General Purpose
Re: [coreboot] MCP55 Mac Address copying/change
On Monday 08 November 2010 15:30:44 Peter Stuge wrote:
Harald Gutmann wrote:
Just for my personal interest, could someone explain me what
actually is called romstrap?
It's a horrible name for permanent settings that are stored in the
boot flash.
I thought that these things are permanently stored. But is it just a name for
fixed values in the flash, or do those values need to be stored at a special
address in the flash?
Is there any fast method to read the onboards NIC mac address faster?
ip l sh eth0|grep link/ether|awk '{print $2}'
I know that this is possible via commands on the shell, but you can't be sure
that you select the onboard NIC with that method, because when a second NIC is
used in that board on PCI this one could also be eth0, and therefore you could
end up with the wrong one getting copied.
//Peter
Regards,
Harald
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Re: [coreboot] MCP55 Mac Address copying/change
Is there any fast method to read the onboards NIC mac address
faster?
ip l sh eth0|grep link/ether|awk '{print $2}'
I know that this is possible via commands on the shell, but you can't be
sure
that you select the onboard NIC with that method, because when a second
NIC is
used in that board on PCI this one could also be eth0, and therefore you
could
end up with the wrong one getting copied.
I thought you could tell the vendor by looking at the MAC Address.
Thanks,
Myles
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