Re: [coreboot] Initial bits to support Thinkpad X60
Hi Stefan, Stefan Reinauer ste...@coreboot.org writes: Not sure we want to use that socket as it is the container for all the old CPUs. Sure it isn't a mFCPGA478 'cause that's what Merom/Yonah usually use. Intel Spec Finder (http://ark.intel.com/Product.aspx?id=27228) says it's 'PBGA479' which is soldered directly to the Board, so mPGA479M looked like the best fit. But the mFCPGA478 works without modifications, so we may use that. I have no problem changing the code to 478, i'm just not sure what the right Socket is. Regards, Sven -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Unused files
These include files are unused, they are never included src/cpu/amd/model_10xxx/mc_patch_0120.h src/cpu/amd/model_10xxx/mc_patch_0183.h src/cpu/amd/model_10xxx/mc_patch_0184.h src/cpu/intel/model_f1x/multiplier.h src/cpu/intel/model_f0x/multiplier.h src/southbridge/amd/cs5536/smbus2.h I vote for dropping them. Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Unused files
On Wed, Jan 12, 2011 at 12:39 PM, Stefan Reinauer ste...@coreboot.org wrote: These include files are unused, they are never included src/cpu/amd/model_10xxx/mc_patch_0120.h src/cpu/amd/model_10xxx/mc_patch_0183.h src/cpu/amd/model_10xxx/mc_patch_0184.h src/cpu/intel/model_f1x/multiplier.h src/cpu/intel/model_f0x/multiplier.h src/southbridge/amd/cs5536/smbus2.h I vote for dropping them. Stefan I agree, the patch files have been replaced by newer version. Marc -- http://se-eng.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [commit] r6249 - in trunk/src: cpu/amd/model_10xxx cpu/intel/model_f0x cpu/intel/model_f1x southbridge/amd/cs5536
Author: stepan Date: Wed Jan 12 22:09:25 2011 New Revision: 6249 URL: https://tracker.coreboot.org/trac/coreboot/changeset/6249 Log: drop unused files Signed-off-by: Stefan Reinauer ste...@coreboot.org Acked-by: Stefan Reinauer ste...@coreboot.org Deleted: trunk/src/cpu/amd/model_10xxx/mc_patch_0120.h trunk/src/cpu/amd/model_10xxx/mc_patch_0183.h trunk/src/cpu/amd/model_10xxx/mc_patch_0184.h trunk/src/cpu/intel/model_f0x/multiplier.h trunk/src/cpu/intel/model_f1x/multiplier.h trunk/src/southbridge/amd/cs5536/smbus2.h -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] enabling expert mode - build fails (warnings treated as errors) on fam10 boards
Hi all, If one enables expert mode in Kconfig and builds a fam10 board, this is what happens: $ make clean make ROMCC mainboard/supermicro/h8qme_fam10/bootblock.inc GENbootblock/bootblock.S CC mainboard/supermicro/h8qme_fam10/bootblock.s CC mainboard/supermicro/h8qme_fam10/bootblock.o GENbootblock/ldscript.ld LINK bootblock.elf OBJCOPYcoreboot.bootblock OPTION option_table.h GENbuild.h CC romstage.inc cc1: warnings being treated as errors In file included from src/northbridge/amd/amdht/ht_wrapper.c:52:0, from src/cpu/amd/quadcore/quadcore.c:22, from src/mainboard/supermicro/h8qme_fam10/romstage.c:72: src/northbridge/amd/amdht/h3finit.c: In function 'selectOptimalWidthAndFrequency': src/northbridge/amd/amdht/h3finit.c:1332:24: error: CONFIG_LIMIT_HT_SPEED_300 is not defined src/northbridge/amd/amdht/h3finit.c:1336:24: error: CONFIG_LIMIT_HT_SPEED_500 is not defined make: *** [build/mainboard/supermicro/h8qme_fam10/romstage.pre.inc] Error 1 I looked around a bit; those config variables do not appear to be used anywhere but in the checks in h3finit.c. What's the best way to fix this? Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Unused files
-Original Message- From: coreboot-boun...@coreboot.org [mailto:coreboot-boun...@coreboot.org] On Behalf Of Marc Jones Sent: Wednesday, January 12, 2011 02:08 PM To: Stefan Reinauer Cc: coreboot@coreboot.org Subject: Re: [coreboot] Unused files On Wed, Jan 12, 2011 at 12:39 PM, Stefan Reinauer ste...@coreboot.org wrote: These include files are unused, they are never included src/cpu/amd/model_10xxx/mc_patch_0120.h src/cpu/amd/model_10xxx/mc_patch_0183.h src/cpu/amd/model_10xxx/mc_patch_0184.h src/cpu/intel/model_f1x/multiplier.h src/cpu/intel/model_f0x/multiplier.h src/southbridge/amd/cs5536/smbus2.h I vote for dropping them. Stefan ]I agree, the patch files have been replaced by newer version. ] ]Marc ]-- ]http://se-eng.com All the AMD family 10h patches are quite old. The first 4 bytes show dates of: mc_patch_01B6 07/31/2009 mc_patch_019F 12/17/2008 mc_patch_0186 05/01/2008 mc_patch_0195 11/04/2008 mc_patch_0196 11/05/2008 The AMI BIOS in my Asustek m3A78 family 10h motherboard has 2010 patches. Thanks, Scott -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Unused files
Stefan Reinauer wrote: These include files are unused, they are never included src/cpu/amd/model_10xxx/mc_patch_0120.h src/cpu/amd/model_10xxx/mc_patch_0183.h src/cpu/amd/model_10xxx/mc_patch_0184.h src/cpu/intel/model_f1x/multiplier.h src/cpu/intel/model_f0x/multiplier.h src/southbridge/amd/cs5536/smbus2.h I vote for dropping them. Acked-by: Peter Stuge pe...@stuge.se -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Unused files
* Scott Duplichan sc...@notabs.org [110112 23:35]: On Wed, Jan 12, 2011 at 12:39 PM, Stefan Reinauer ste...@coreboot.org wrote: These include files are unused, they are never included src/cpu/amd/model_10xxx/mc_patch_0120.h src/cpu/amd/model_10xxx/mc_patch_0183.h src/cpu/amd/model_10xxx/mc_patch_0184.h src/cpu/intel/model_f1x/multiplier.h src/cpu/intel/model_f0x/multiplier.h src/southbridge/amd/cs5536/smbus2.h I vote for dropping them. Stefan ]I agree, the patch files have been replaced by newer version. ] ]Marc ]-- ]http://se-eng.com All the AMD family 10h patches are quite old. The first 4 bytes show dates of: mc_patch_01B6 07/31/2009 mc_patch_019F 12/17/2008 mc_patch_0186 05/01/2008 mc_patch_0195 11/04/2008 mc_patch_0196 11/05/2008 The AMI BIOS in my Asustek m3A78 family 10h motherboard has 2010 patches. Where can we get newer microcode patches from? AMD anyone? Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] enabling expert mode - build fails (warnings treated as errors) on fam10 boards
* Ward Vandewege w...@gnu.org [110112 23:12]: Hi all, If one enables expert mode in Kconfig and builds a fam10 board, this is what happens: $ make clean make ROMCC mainboard/supermicro/h8qme_fam10/bootblock.inc GENbootblock/bootblock.S CC mainboard/supermicro/h8qme_fam10/bootblock.s CC mainboard/supermicro/h8qme_fam10/bootblock.o GENbootblock/ldscript.ld LINK bootblock.elf OBJCOPYcoreboot.bootblock OPTION option_table.h GENbuild.h CC romstage.inc cc1: warnings being treated as errors In file included from src/northbridge/amd/amdht/ht_wrapper.c:52:0, from src/cpu/amd/quadcore/quadcore.c:22, from src/mainboard/supermicro/h8qme_fam10/romstage.c:72: src/northbridge/amd/amdht/h3finit.c: In function 'selectOptimalWidthAndFrequency': src/northbridge/amd/amdht/h3finit.c:1332:24: error: CONFIG_LIMIT_HT_SPEED_300 is not defined src/northbridge/amd/amdht/h3finit.c:1336:24: error: CONFIG_LIMIT_HT_SPEED_500 is not defined make: *** [build/mainboard/supermicro/h8qme_fam10/romstage.pre.inc] Error 1 I looked around a bit; those config variables do not appear to be used anywhere but in the checks in h3finit.c. What's the best way to fix this? Thanks, Ward. Looks like a piece of Kconfig patch went missing? -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this
Hi i have a question about this L2 cache, can it also be used for the P3 socket PGA370. My nokia Ip530 has that type of CPU and as far as i know L2 cache is disabled Regards, Marc -Original Message- From: Keith Hui buu...@gmail.com To: coreboot@coreboot.org Cc: Jouni Mettälä jtmett...@gmail.com, Idwer Vollering vid...@gmail.com, Roger rogerx@gmail.com Subject: Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this Date: Tue, 11 Jan 2011 23:17:17 -0500 Hi all, Here is the new L2 cache patch. Sign-off in the patch itself. Still very juicy and tasty at 25k. :D Also done is including cpu/intel/model_68x again in slot_1. Otherwise it will die with a Coppermine P3 installed. My boot log on P2B-LS and a Katmai 600MHz attached. I have optimized it some more, and added more information and meaningful constants as I cross checked the code with Intel's documentation. Some debugging messages are different too. Give this a good workout. Cheers Keith ps. Copying people who have sent me reports. :) On Fri, Jan 7, 2011 at 3:45 PM, Jouni Mettälä jtmett...@gmail.com wrote: Hi Parts of original patch are already in coreboot. This version made cache work in my board now. It might need work so it doesn't break others. Here is part of serial capture. Rest is attached Initializing CPU #0 CPU: vendor Intel device 673 CPU: family 06, model 07, stepping 03 microcode_info: sig = 0x0673 pf=0x0001 rev = 0x microcode updated to revision: 000e from revision Configuring L2 cache... rdmsr(IA32_PLATFORM_ID) = 0, 1102 L2 Cache latency is 8 Sending 0 to set_l2_register4 L2 ECC Checking is enabled L2 Physical Address Range is 4096M Maximum cache mask is 2 L2 Cache Mask is 4000 read_l2(2) = 8 write_l2(2) = 8 L2 Cache size is 512K L2 Cache lines initialized Signed-off-by: Jouni Mettälä jtmett...@gmail.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Restarting at Jumping to image
Hello, I am working on a new mainboard/northbridge and have got it all the way to Jumping to image and then it immediately restarts and loops at that point over and over. I even did a ram_check() on the whole memory (accept vga range) and it passes just fine. Has anyone seen this before? Is there a simple way to verify/read the raw data after coreboot is copied to memory? Help? Here is my bootlog: http://coreboot.pastebin.com/KNyMM9xZ -- Thanks, Joseph Smith Set-Top-Linux www.settoplinux.org -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Restarting at Jumping to image
* Joseph Smith j...@settoplinux.org [110113 01:00]: Hello, I am working on a new mainboard/northbridge and have got it all the way to Jumping to image and then it immediately restarts and loops at that point over and over. I even did a ram_check() on the whole memory (accept vga range) and it passes just fine. Has anyone seen this before? Is there a simple way to verify/read the raw data after coreboot is copied to memory? Help? Here is my bootlog: http://coreboot.pastebin.com/KNyMM9xZ ram_check() is not a good test to see if ram is working. It merely catches some cases where RAM is _not_ working. Sorry to say but with a 99% chance this means your RAM init is faulty. You can switch compression of stage 2 explicitly off and then dump the memory at 0x10 to serial and compare it with your coreboot.rom file. Stefan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this
The L2 cache on a Coppermine doesn't need any special enabling sequence. I just put a 1GHz Coppermine into my board and it boots fine showing the full 256k cache. This patch doesn't even apply to them anyway. Cheers Keith On Wed, Jan 12, 2011 at 6:04 PM, Marc Bertens mbert...@xs4all.nl wrote: Hi i have a question about this L2 cache, can it also be used for the P3 socket PGA370. My nokia Ip530 has that type of CPU and as far as i know L2 cache is disabled Regards, Marc -Original Message- From: Keith Hui buu...@gmail.com To: coreboot@coreboot.org Cc: Jouni Mettälä jtmett...@gmail.com, Idwer Vollering vid...@gmail.com, Roger rogerx@gmail.com Subject: Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this Date: Tue, 11 Jan 2011 23:17:17 -0500 Hi all, Here is the new L2 cache patch. Sign-off in the patch itself. Still very juicy and tasty at 25k. :D Also done is including cpu/intel/model_68x again in slot_1. Otherwise it will die with a Coppermine P3 installed. My boot log on P2B-LS and a Katmai 600MHz attached. I have optimized it some more, and added more information and meaningful constants as I cross checked the code with Intel's documentation. Some debugging messages are different too. Give this a good workout. Cheers Keith ps. Copying people who have sent me reports. :) On Fri, Jan 7, 2011 at 3:45 PM, Jouni Mettälä jtmett...@gmail.com wrote: Hi Parts of original patch are already in coreboot. This version made cache work in my board now. It might need work so it doesn't break others. Here is part of serial capture. Rest is attached Initializing CPU #0 CPU: vendor Intel device 673 CPU: family 06, model 07, stepping 03 microcode_info: sig = 0x0673 pf=0x0001 rev = 0x microcode updated to revision: 000e from revision Configuring L2 cache... rdmsr(IA32_PLATFORM_ID) = 0, 1102 L2 Cache latency is 8 Sending 0 to set_l2_register4 L2 ECC Checking is enabled L2 Physical Address Range is 4096M Maximum cache mask is 2 L2 Cache Mask is 4000 read_l2(2) = 8 write_l2(2) = 8 L2 Cache size is 512K L2 Cache lines initialized Signed-off-by: Jouni Mettälä jtmett...@gmail.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] SECC Pentium 2/3 users are gonna love this
On Wed, Jan 12, 2011 at 10:55:37PM -0500, Keith Hui wrote: The L2 cache on a Coppermine doesn't need any special enabling sequence. I just put a 1GHz Coppermine into my board and it boots fine showing the full 256k cache. This patch doesn't even apply to them anyway. FYI: Have 450P3 and 2x750P3's here and none of my coreboot logs state anything about L2 being activated. From what you're saying, the L2 cache is entirely automatically activated on Coppermines. Cheers. -- Roger http://rogerx.freeshell.org/ -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
