Re: [coreboot] Fam10 FIDVID in SVI : disabling microcode update
Xavi Drudis Ferran writes: Hello. Hello. Should I send a patch making a Kconfig option to not upgrade microcode for fam10? Is there any interest in that ? I have interest in that. I am working on ECS A740GM-M port and have asked that question in my mail, but for different reasons. [1] My patches are not in the repository yet. Still haven't split them. :( Right now I use a workaround to prevent loading of microcode. I've made a zero-filled microcode patch file that is kept in the board directory. The Kconfig option for the microcode file points to that file. The effect of this is same revision (0) in patch and CPU and the microcode is not loaded. This worked on Sempron 140 and r6725. Haven't tested it with recent changes and revisions. [1] http://www.coreboot.org/pipermail/coreboot/2011-January/063067.html -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] add SPD address mapping to i945
The current code works only with dual channel if Channel 0 uses SPD address
0x50/0x51, while the second channel has to use 0x52/0x53.
For hardware that uses other addresses (like the ThinkPad X60) this means we
get only one module running instead of both.
This patch adds a second parameter to sdram_initialize, which is an array with
2 * DIMM_SOCKETS members. It should contain the SPD addresses for every single
DIMM socket. If NULL is given as the second parameter, the code uses the old
addressing scheme.
---
src/mainboard/getac/p470/romstage.c |2 +-
src/mainboard/ibase/mb899/romstage.c |2 +-
src/mainboard/intel/d945gclf/romstage.c |2 +-
src/mainboard/kontron/986lcd-m/romstage.c |2 +-
src/mainboard/lenovo/x60/romstage.c |3 +-
src/mainboard/roda/rk886ex/romstage.c |2 +-
src/northbridge/intel/i945/raminit.c | 75 +++--
src/northbridge/intel/i945/raminit.h |3 +-
8 files changed, 47 insertions(+), 44 deletions(-)
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 270a7bd..83cd91e 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -332,7 +332,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode);
+ sdram_initialize(boot_mode, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index d3a0299..e248a27 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -283,7 +283,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode);
+ sdram_initialize(boot_mode, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index f705673..6dfc144 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -243,7 +243,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode);
+ sdram_initialize(boot_mode, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 925c93e..2cf73e6 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -382,7 +382,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode);
+ sdram_initialize(boot_mode, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 5578324..e2b4a40 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -294,6 +294,7 @@ void main(unsigned long bist)
{
u32 reg32;
int boot_mode = 0;
+ const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 };
if (bist == 0)
enable_lapic();
@@ -357,7 +358,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode);
+ sdram_initialize(boot_mode, spd_addrmap);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index fce53da..0797699 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -320,7 +320,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode);
+ sdram_initialize(boot_mode, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 1c93435..0970e87 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -54,9 +54,12 @@ struct cbmem_entry *get_cbmem_toc(void)
#define RAM_EMRS_2 (0x1 21)
#define RAM_EMRS_3 (0x2 21)
-static inline int spd_read_byte(unsigned device, unsigned address)
+static inline int spd_read_byte(struct sys_info *sys_info, unsigned device, unsigned address)
{
- return smbus_read_byte(device, address);
+ if (sys_info-spd_addresses)
+ return smbus_read_byte(sys_info-spd_addresses[device], address);
+ else
+ return smbus_read_byte(DIMM0 + device, address);
}
static __attribute__((noinline)) void do_ram_command(u32 command)
@@ -367,7 +370,7 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
*/
for (i=0; i(2 * DIMM_SOCKETS); i++) {
- u8 reg8, device = DIMM0 + i;
+ u8 reg8;
/* Initialize the socket information with a sane value */
sysinfo-dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
@@ -382,24 +385,24 @@
Re: [coreboot] [PATCH] Move cmos.default handling to bootblock
Georgi, Patrick wrote: Is there a Kconfig option for enabling the NVRAM write? I would like that very much. I'd also like it to be off by default. HAVE_CMOS_DEFAULT. Without this, cmos.default isn't put into CBFS (by default), and without that file, no write happens. But it's a mainboard knob, not a user knob, right? Maybe we should consider some coreboot profiles for Kconfig, that would autoselect options, which could be manually overridden by experts? profiles? We have those: mainboard defaults. Call them profiles or maybe personalities. Yes there is one set of options from the developer creating the original port, but I'm thinking more of bird's view variations; * Zero impact coreboot (never writes to NVRAM) * Normal mode (will fix NVRAM with defaults) * Strict mode (requires NVRAM to always be correct, or will fail to boot. maybe also other extra checks in the code) There could be other personalities. The point is that they are very high level (ie. easy for every user to decide on, because they fit or do not fit) and might control more than one Kconfig option. //Peter pgp2EkcPegtlU.pgp Description: PGP signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] add SPD address mapping to i945
Am Freitag, den 18.02.2011, 12:09 +0100 schrieb Sven Schnelle:
The current code works only with dual channel if Channel 0 uses SPD address
0x50/0x51, while the second channel has to use 0x52/0x53.
For hardware that uses other addresses (like the ThinkPad X60) this means we
get only one module running instead of both.
This patch adds a second parameter to sdram_initialize, which is an array with
2 * DIMM_SOCKETS members. It should contain the SPD addresses for every single
DIMM socket. If NULL is given as the second parameter, the code uses the old
addressing scheme.
Awww...
Please keep spd_read_byte alone, we have a somewhat unified API there
across the chipsets (and I hope to clean it up even more at some point,
see http://www.coreboot.org/Infrastructure_Projects#Refactor_SMBUS_code)
Maybe you could create a function like
int get_dimm_no(struct sys_info *sys_info, int device) {
if (sys_info-spd_addresses)
return sys_info-spd_addresses[device];
else
return DIMM0 + device;
}
and use that to determine the addresses where currently DIMM0+i is
used instead?
While this would be changed in a clean-up like referred to above, it
would be less of an effort than to essentially undo your changes.
That should give you the same result with not changing any internal
APIs.
Thanks,
Patrick
--
Patrick Georgi
SINA-Development - High Security
secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany
Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com
Sitz: Kronprinzenstraße 30, 45128 Essen / Amtsgericht Essen HRB 13615
Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines
Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg
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Re: [coreboot] [PATCH] Move cmos.default handling to bootblock
Am Freitag, den 18.02.2011, 12:15 +0100 schrieb Peter Stuge: HAVE_CMOS_DEFAULT. Without this, cmos.default isn't put into CBFS (by default), and without that file, no write happens. But it's a mainboard knob, not a user knob, right? We don't deliver cmos.default files, so this is a user setting at this time. This might change, and then we should reevaluate how we handle CMOS. But USE_OPTION_TABLE should disable it _all_ anyway. So you already have: - no CMOS at all - CMOS support, but no cmos.default - CMOS support with cmos.default Call them profiles or maybe personalities. Yes there is one set of options from the developer creating the original port, but I'm thinking more of bird's view variations; We already stretch Kconfig beyond its limits. Let's not do it any further or it will break apart. * Strict mode (requires NVRAM to always be correct, or will fail to boot. maybe also other extra checks in the code) Fail to boot? I wonder about its use. Patrick -- Patrick Georgi SINA-Development - High Security secunet Security Networks AG - Mergenthalerallee 77 - 65760 Eschborn, Germany Phone +49 201 54 54-3610 - Fax +49 201 54 54-1325 - www.secunet.com Sitz: Kronprinzenstraße 30, 45128 Essen / Amtsgericht Essen HRB 13615 Vorstand: Dr. Rainer Baumgart (Vors.), Thomas Koelzer, Thomas Pleines Aufsichtsratsvorsitzender: Dr. Karsten Ottenberg signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] [PATCH] add SPD address mapping to i945
[Missed coreboot List Cc]
Hi Patrick,
thanks for you reply. I've attached a new patch which addresses
those issues.
Thanks,
Sven.
--
For hardware that uses other addresses (like the ThinkPad X60) this means we
get only one module running instead of both.
This patch adds a second parameter to sdram_initialize, which is an array with
2 * DIMM_SOCKETS members. It should contain the SPD addresses for every single
DIMM socket. If NULL is given as the second parameter, the code uses the old
addressing scheme.
Signed-off-by: Sven Schnelle sv...@stackframe.org
---
src/mainboard/getac/p470/romstage.c |2 +-
src/mainboard/ibase/mb899/romstage.c |2 +-
src/mainboard/intel/d945gclf/romstage.c |2 +-
src/mainboard/kontron/986lcd-m/romstage.c |2 +-
src/mainboard/lenovo/x60/romstage.c |3 +-
src/mainboard/roda/rk886ex/romstage.c |2 +-
src/northbridge/intel/i945/raminit.c | 57 +++--
src/northbridge/intel/i945/raminit.h |3 +-
8 files changed, 46 insertions(+), 27 deletions(-)
diff --git a/src/mainboard/getac/p470/romstage.c b/src/mainboard/getac/p470/romstage.c
index 270a7bd..83cd91e 100644
--- a/src/mainboard/getac/p470/romstage.c
+++ b/src/mainboard/getac/p470/romstage.c
@@ -332,7 +332,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode);
+ sdram_initialize(boot_mode, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/mainboard/ibase/mb899/romstage.c b/src/mainboard/ibase/mb899/romstage.c
index d3a0299..e248a27 100644
--- a/src/mainboard/ibase/mb899/romstage.c
+++ b/src/mainboard/ibase/mb899/romstage.c
@@ -283,7 +283,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode);
+ sdram_initialize(boot_mode, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index f705673..6dfc144 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -243,7 +243,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode);
+ sdram_initialize(boot_mode, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/mainboard/kontron/986lcd-m/romstage.c b/src/mainboard/kontron/986lcd-m/romstage.c
index 925c93e..2cf73e6 100644
--- a/src/mainboard/kontron/986lcd-m/romstage.c
+++ b/src/mainboard/kontron/986lcd-m/romstage.c
@@ -382,7 +382,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode);
+ sdram_initialize(boot_mode, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/mainboard/lenovo/x60/romstage.c b/src/mainboard/lenovo/x60/romstage.c
index 5578324..e2b4a40 100644
--- a/src/mainboard/lenovo/x60/romstage.c
+++ b/src/mainboard/lenovo/x60/romstage.c
@@ -294,6 +294,7 @@ void main(unsigned long bist)
{
u32 reg32;
int boot_mode = 0;
+ const u8 spd_addrmap[2 * DIMM_SOCKETS] = { 0x50, 0x52, 0x51, 0x53 };
if (bist == 0)
enable_lapic();
@@ -357,7 +358,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode);
+ sdram_initialize(boot_mode, spd_addrmap);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/mainboard/roda/rk886ex/romstage.c b/src/mainboard/roda/rk886ex/romstage.c
index fce53da..0797699 100644
--- a/src/mainboard/roda/rk886ex/romstage.c
+++ b/src/mainboard/roda/rk886ex/romstage.c
@@ -320,7 +320,7 @@ void main(unsigned long bist)
dump_spd_registers();
#endif
- sdram_initialize(boot_mode);
+ sdram_initialize(boot_mode, NULL);
/* Perform some initialization that must run before stage2 */
early_ich7_init();
diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c
index 1c93435..8b7ffa1 100644
--- a/src/northbridge/intel/i945/raminit.c
+++ b/src/northbridge/intel/i945/raminit.c
@@ -54,6 +54,15 @@ struct cbmem_entry *get_cbmem_toc(void)
#define RAM_EMRS_2 (0x1 21)
#define RAM_EMRS_3 (0x2 21)
+static int get_dimm_spd_address(struct sys_info *sysinfo, int device)
+{
+ if (sysinfo-spd_addresses)
+ return sysinfo-spd_addresses[device];
+ else
+ return DIMM0 + device;
+
+}
+
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
@@ -367,7 +376,8 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo)
*/
for (i=0; i(2 * DIMM_SOCKETS); i++) {
- u8 reg8, device = DIMM0 + i;
+ int device = get_dimm_spd_address(sysinfo, i);
+ u8 reg8;
/* Initialize the socket information with a sane value */
sysinfo-dimm[i] = SYSINFO_DIMM_NOT_POPULATED;
@@ -458,7 +468,7 @@ static void sdram_verify_package_type(struct sys_info *
Re: [coreboot] support request - SOYO 7VBA133
On Thu, Feb 17, 2011 at 11:02 PM, Peter Stuge pe...@stuge.se wrote: José Neto wrote: Can you support my motherboard??? No. You will have to do the development yourself, if you want it. [Apollo PRO133x] [1106:0691] +-01.0-[:01]00.0 Silicon Integrated Systems [SiS] 300/305 PCI/AGP VGA Display Adapter [1039:0300] SiS is out of the chipset business since years, and v4 has no code for this chipset. Maybe you can do surgery from v1. That's just the VGA card, the Apollo Pro 133 is Via 693+686a. -Corey //Peter -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Fam10 FIDVID in SVI : disabling microcode update
Hi Xavi, On Wed, Feb 16, 2011 at 02:45:02PM +0100, Xavi Drudis Ferran wrote: Should I send a patch making a Kconfig option to not upgrade microcode for fam10? Is there any interest in that ? Yes, please. I would test and ack that. Thanks, Ward. -- Ward Vandewege w...@fsf.org Free Software Foundation - Senior Systems Administrator -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New CMOS option sata_mode
Attached patch implements a new CMOS option 'sata_mode'.
A new Kconfig option 'SATA_MODE' with default 'ide' is added to
amd/sb600/Kconfig.
The handling of the CMOS option is placed in amd/sb600/sata.c and
overrides the hardcoded 'ide' mode
in the following way:
if get_option(., sata_mode) returns 0 use CMOS option
in case of -2 grab the Kconfig option CONFIG_SATA_MODE if exist
otherwise use the hardcoded mode.
Signed-off-by: Josef Kellermann se...@arcor.de mailto://se...@arcor.de
From c349a79ea1ac9bcd52376b80f32cfa0552259219 Mon Sep 17 00:00:00 2001
From: Josef Kellermann se...@arcor.de
Date: Fri, 18 Feb 2011 11:44:31 +0100
Subject: [PATCH 1/2] added new cmos option 'sata_mode' and Kconfig option
'SATA_MODE'
This options override the default chipset mode 'IDE'
in the following way: if cmos option exist use cmos option, if Kconfig option
exist use Kconfig option else use default 'IDE'.
---
src/southbridge/amd/sb600/Kconfig |5 -
src/southbridge/amd/sb600/sata.c | 30 ++
2 files changed, 26 insertions(+), 9 deletions(-)
diff --git a/src/southbridge/amd/sb600/Kconfig
b/src/southbridge/amd/sb600/Kconfig
index 4e86999..7831aa3 100644
--- a/src/southbridge/amd/sb600/Kconfig
+++ b/src/southbridge/amd/sb600/Kconfig
@@ -35,4 +35,7 @@ config EHCI_BAR
config EHCI_DEBUG_OFFSET
hex
default 0xe0 if SOUTHBRIDGE_AMD_SB600
-
+
+config SATA_MODE
+ string
+ default ide
diff --git a/src/southbridge/amd/sb600/sata.c b/src/southbridge/amd/sb600/sata.c
index 055e7da..143135e 100644
--- a/src/southbridge/amd/sb600/sata.c
+++ b/src/southbridge/amd/sb600/sata.c
@@ -17,7 +17,6 @@
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-
#include console/console.h
#include device/device.h
#include delay.h
@@ -26,6 +25,10 @@
#include device/pci_ops.h
#include arch/io.h
#include sb600.h
+#include pc80/mc146818rtc.h
+
+#define SATA_MODE_IDE 1
+#define SATA_MODE_AHCI !(SATA_MODE_IDE)
static int sata_drive_detect(int portnum, u16 iobar)
{
@@ -98,10 +101,6 @@ static void sata_init(struct device *dev)
printk(BIOS_SPEW, sata_bar4=%x\n, sata_bar4); /* 3000 */
printk(BIOS_SPEW, sata_bar5=%x\n, sata_bar5); /* e0309000 */
- /* Program the 2C to 0x43801002 */
- dword = 0x43801002;
- pci_write_config32(dev, 0x2c, dword);
-
/* SERR-Enable */
word = pci_read_config16(dev, 0x04);
word |= (1 8);
@@ -112,13 +111,28 @@ static void sata_init(struct device *dev)
byte |= (1 2);
pci_write_config8(dev, 0x40, byte);
- /* Set SATA Operation Mode, Set to IDE mode */
+ /* Set SATA Operation Mode */
byte = pci_read_config8(dev, 0x40);
byte |= (1 0);
byte |= (1 4);
pci_write_config8(dev, 0x40, byte);
- dword = 0x01018f00;
+ // 1 means IDE, 0 means AHCI
+ if( get_option(i, sata_mode) 0 ) {
+ // no cmos option
+ i = SATA_MODE_IDE; // default
+#if defined(CONFIG_SATA_MODE)
+ i = ((CONFIG_SATA_MODE[0] ~0x20) == 'A') ? SATA_MODE_AHCI :
SATA_MODE_IDE;
+#endif
+ }
+ printk(BIOS_INFO, %s: setting sata mode = %s\n,__func__, (i ==
SATA_MODE_IDE) ? ide : ahci );
+
+ dword = pci_read_config32(dev, 0x8);
+ dword = 0xffff;
+ if( i == SATA_MODE_IDE )
+ dword |= 0x00018f00; // IDE mode
+ else
+ dword |= 0x00060100; // AHCI mode
pci_write_config32(dev, 0x8, dword);
byte = pci_read_config8(dev, 0x40);
@@ -245,7 +259,7 @@ static void sata_init(struct device *dev)
}
static struct pci_operations lops_pci = {
- /* .set_subsystem = pci_dev_set_subsystem, */
+ .set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations sata_ops = {
--
1.7.1
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Re: [coreboot] support request - SOYO 7VBA133
Oh sorry... But i have no idea for where start. Unfortunately, wanting is not being able to. Thanks anyway! On Thu, Feb 17, 2011 at 11:02 PM, Peter Stuge pe...@stuge.se wrote: José Neto wrote: Can you support my motherboard??? No. You will have to do the development yourself, if you want it. -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] add Kconfig options in addition/in place of CMOS option
Attached patch adds sane compile-time defaults via Kconfig options for
CMOS options
'iommu, ECC_memory, max_mem_clock, hw_scrubber, interleave_chip_selects'.
Avoid build error if any of these CMOS options are not defined.
Checks the return value of 'get_option(..)', if not done yet, and
if CMOS option not exist grab a Kconfig option otherwise a hardcoded
value is used.
Signed-off-by: Josef Kellermann se...@arcor.de mailto://se...@arcor.de
From 7442dfd6d12bf596fdb64bff370631eb2e75c542 Mon Sep 17 00:00:00 2001
From: Josef Kellermann se...@arcor.de
Date: Fri, 18 Feb 2011 14:25:33 +0100
Subject: [PATCH 2/2] This patch
adds sane compile-time defaults via Kconfig options for CMOS options
'iommu, ECC_memory, max_mem_clock, hw_scrubber, interleave_chip_selcts'.
avoid build error if any of these CMOS options are not defined.
checks the return value of 'get_option(..)', if not done yet, and
if CMOS option not exist grab a Kconfig option otherwise a hardcoded
value is used.
---
src/cpu/amd/model_fxx/model_fxx_init.c | 12 +++--
src/northbridge/amd/amdk8/misc_control.c |9 +-
src/northbridge/amd/amdk8/raminit_f.c| 37 +++--
3 files changed, 45 insertions(+), 13 deletions(-)
diff --git a/src/cpu/amd/model_fxx/model_fxx_init.c
b/src/cpu/amd/model_fxx/model_fxx_init.c
index a5112b3..bfdefa2 100644
--- a/src/cpu/amd/model_fxx/model_fxx_init.c
+++ b/src/cpu/amd/model_fxx/model_fxx_init.c
@@ -263,8 +263,15 @@ static void init_ecc_memory(unsigned node_id)
}
/* See if we scrubbing should be enabled */
- enable_scrubbing = 1;
- get_option(enable_scrubbing, hw_scrubber);
+ /* fixme: does it make any sense enabling scrubbing if not ECC_memory ?
*/
+ dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
+ enable_scrubbing = (dcl DCL_DimmEccEn) ? 1 : 0; /* default: enable
scrubbing if ECC_memory */
+ if( get_option(enable_scrubbing, hw_scrubber) 0 )
+ {
+#if defined(CONFIG_HW_SCRUBBER)
+ enable_scrubbing = CONFIG_HW_SCRUBBER;
+#endif
+ }
/* Enable cache scrubbing at the lowest possible rate */
if (enable_scrubbing) {
@@ -279,7 +286,6 @@ static void init_ecc_memory(unsigned node_id)
}
/* If ecc support is not enabled don't touch memory */
- dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
if (!(dcl DCL_DimmEccEn)) {
printk(BIOS_DEBUG, ECC Disabled\n);
return;
diff --git a/src/northbridge/amd/amdk8/misc_control.c
b/src/northbridge/amd/amdk8/misc_control.c
index fa90a55..e65b2a9 100644
--- a/src/northbridge/amd/amdk8/misc_control.c
+++ b/src/northbridge/amd/amdk8/misc_control.c
@@ -46,9 +46,14 @@ static void mcf3_read_resources(device_t dev)
if (dev-path.pci.devfn != PCI_DEVFN(0x18, 3)) {
return;
}
-
+
iommu = 1;
- get_option(iommu, iommu);
+ if( get_option(iommu, iommu) 0 )
+ {
+#if defined(CONFIG_IOMMU)
+ iommu = CONFIG_IOMMU;
+#endif
+ }
if (iommu) {
/* Add a GART aperture resource */
diff --git a/src/northbridge/amd/amdk8/raminit_f.c
b/src/northbridge/amd/amdk8/raminit_f.c
index 3135bce..d7d6157 100644
--- a/src/northbridge/amd/amdk8/raminit_f.c
+++ b/src/northbridge/amd/amdk8/raminit_f.c
@@ -1107,6 +1107,15 @@ static unsigned long interleave_chip_selects(const
struct mem_controller *ctrl,
/* See if all of the memory chip selects are the same size
* and if so count them.
*/
+#if defined(CMOS_VSTART_interleave_chip_selects)
+ if (read_option(CMOS_VSTART_interleave_chip_selects,
CMOS_VLEN_interleave_chip_selects, 1) == 0)
+ return 0;
+#else
+#if !defined(CONFIG_INTERLEAVE_CHIP_SELECTS) ||
(CONFIG_INTERLEAVE_CHIP_SELECTS == 0)
+ return 0;
+#endif
+#endif
+
chip_selects = 0;
common_size = 0;
common_cs_mode = 0xff;
@@ -1279,15 +1288,10 @@ static void order_dimms(const struct mem_controller
*ctrl,
{
unsigned long tom_k, base_k;
- if (read_option(CMOS_VSTART_interleave_chip_selects,
- CMOS_VLEN_interleave_chip_selects, 1) != 0) {
- tom_k = interleave_chip_selects(ctrl, meminfo-is_Width128);
- } else {
- printk(BIOS_DEBUG, Interleaving disabled\n);
- tom_k = 0;
- }
+ tom_k = interleave_chip_selects(ctrl, meminfo-is_Width128);
if (!tom_k) {
+ printk(BIOS_DEBUG, Interleaving disabled\n);
tom_k = order_chip_selects(ctrl);
}
@@ -1801,7 +1805,17 @@ static struct spd_set_memclk_result spd_set_memclk(const
struct mem_controller *
value = pci_read_config32(ctrl-f3, NORTHBRIDGE_CAP);
min_cycle_time = min_cycle_times[(value NBCAP_MEMCLK_SHIFT)
NBCAP_MEMCLK_MASK];
bios_cycle_time = min_cycle_times[
- read_option(CMOS_VSTART_max_mem_clock,
Re: [coreboot] support request - SOYO 7VBA133
Thanks! 2011/2/18 Alex G. mr.nuke...@gmail.com On 02/18/2011 08:51 PM, José Neto wrote: Oh sorry... But i have no idea for where start. Unfortunately, wanting is not being able to. Thanks anyway! Start with Peter Stuge's Bringing coreboot to a system near you video. Alex -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Question: Can I change DQS settings from a user program
Hi all, I have a K8 board. I tried to change the DQS settings from a user program, but I failed. I printed out the DQS settings before my pci_write_long() function. I also printed out the DQS settings after the pci writing. The results are same. My question is: can I change DQS settings from a user program? or I need to enable some registers before changing? Thanks, Fengwei -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Support for the new siemens sitemp_g1p1 mainboard
On Fri, Feb 18, 2011 at 12:41 PM, Josef Kellermann se...@arcor.de wrote: Attached patch provides support for the siemens sitemp_g1p1 mainboard. This board is similar to the amd dbm690t. I adapt the code from dbm690t according to customer requirement specification. I have been testing Linux as well as Windows XP booting on this board. Signed-off-by: Josef Kellermann se...@arcor.de Hi Josef, Thanks for the patches. I have not looked at the patch in detail yet, but it is easier to review your changes with a diff based on the reference. The best way is to do an svn copy of the reference directory, then apply your changes. Marc -- http://se-eng.com -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] [PATCH] Correct wrong PCI ID vor VIA K8M890 Chrome
before anyone bricks a board Alex. With the K8T800/M800 patch, the PCI IDs for the VIA chrome were moved to pci_ids.h. The PCI ID for K8M890 chrome was copied incorrectly. (3220 instead of 3230). This patch defines the corect PCI ID for this device. Signed-off-by: Alexandru Gagniuc mr.nuke...@gmail.com Acked-by: Alexandru Gagniuc mr.nuke...@gmail.com Trivial Index: src/include/device/pci_ids.h === --- src/include/device/pci_ids.h (revision 6369) +++ src/include/device/pci_ids.h (working copy) @@ -1260,7 +1260,7 @@ #define PCI_DEVICE_ID_VIA_K8M890CE_4 0x4336 #define PCI_DEVICE_ID_VIA_K8M890CE_5 0x5336 #define PCI_DEVICE_ID_VIA_K8M890CE_7 0x7336 -#define PCI_DEVICE_ID_VIA_K8M890_CHROME 0x3220 +#define PCI_DEVICE_ID_VIA_K8M890_CHROME 0x3230 #define PCI_DEVICE_ID_VIA_K8T890CE_PEG 0xa238 #define PCI_DEVICE_ID_VIA_K8T890CE_PEX0 0xc238 #define PCI_DEVICE_ID_VIA_K8T890CE_PEX1 0xd238 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] P2B-LS help: Onboard SCSI BIOS failed to boot
I am trying (again) to get the Adaptec SCSI on my P2B-LS to initialize properly with coreboot. But it won't boot. Attached is a serial log of what happened. After compiling coreboot I checked out SeaBIOS through git and added the SCSI option rom extracted from my factory bios. A port and a few other resources is assigned, but no IRQ. The SCSI option rom would initialize, I can press the hotkey to enter the utility, but that's it. That option rom hangs before getting any responses from the SCSI hardware. I am trying to set up SerialICE to see what is going on. Just looking for some insights before I reach that point. I have to jumper off the SCSI to get it to boot. I don't know if this has anything to do but the Ultra2 port on my other P2B-LS is fubared and nothing plugged there would register. Afraid the same may befall this board too. Thanks Keith p2bls.scsi.log Description: Binary data -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
