[coreboot] (help me to get better) flashrom support for thinkpads with locked down opcodes

2012-08-26 Thread Stefan Tauner
Hi there!

As you probably all know the procedure to relieve the coreboot-
supported thinkpads from their proprietary firmware is not completely
trivial[1]. The main problem is that the vendor has locked down the
available SPI opcodes that we are allowed to use and this hinders
current flashrom to identify the flash chip.

Carl-Daniel has started to work on a patch that allows flashrom to use
a lower-quality identifying opcode (RES) on such locked down computers
without spoiling flashrom use on other devices. I have continued that
and we now have a patch that allows probing and reading on the
thinkpads. Erase (and hence write in practice) does not work yet,
because the available erase opcodes are also limited, but that will be
dealt with shortly(-ish :).

The current version of the patch can be found here:
http://patchwork.coreboot.org/patch/3726/

I would like to request the help of at least one volunteer who is able
to recover from failed flash attempts and is willing to revert to the
vendor firmware temporarily and spend some time testing patches we sent
him.

This will of course not make the coreboot conversion foolproof and is
quite late... but i am pretty sure it will still be welcomed by
newbies :)

Also, i would like to see a flashrom -V log of any affected machine
that is not a T60 (2007-GCG)[2] and is running the vendor firmware.

[1]: http://www.coreboot.org/Lenovo_x60x
[2]: http://paste.flashrom.org/view.php?id=635
-- 
Kind regards/Mit freundlichen Grüßen, Stefan Tauner

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Re: [coreboot] Moving gerrit to an separate mailing list

2012-08-26 Thread Ward Vandewege
On Wed, Aug 08, 2012 at 04:28:45PM -0500, Alex G. wrote:
 All I've said and refuted above are arguments and rants we like to use
 to tease each other. I strongly believe that it makes sense, now more
 than ever, to separate development and discussion traffic into two
 separate lists. I hope you all agree.

I very much agree.

Thanks,
Ward.

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Re: [coreboot] (help me to get better) flashrom support for thinkpads with locked down opcodes

2012-08-26 Thread Stefan Reinauer
* Stefan Tauner stefan.tau...@student.tuwien.ac.at [120826 21:31]:
 As you probably all know the procedure to relieve the coreboot-
 supported thinkpads from their proprietary firmware is not completely
 trivial[1]. The main problem is that the vendor has locked down the
 available SPI opcodes that we are allowed to use and this hinders
 current flashrom to identify the flash chip.

Have you guys considered SMI cache poisoning attacks to work around
those restrictions?

It would pretty much be a per bios version or per machine based
workaround, but if we can provide known good coreboot images, that might
be attractive for people out there...

Stefan


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[coreboot] Patch set updated for coreboot: b4a6409 Every chip must have chip_operations

2012-08-26 Thread kyosti.mal...@gmail.com
Kyösti Mälkki (kyosti.mal...@gmail.com) just uploaded a new patch set to 
gerrit, which you can find at http://review.coreboot.org/1472

-gerrit

commit b4a6409a8db16e92922f207612f009ce5d1f13f8
Author: Kyösti Mälkki kyosti.mal...@gmail.com
Date:   Tue Aug 21 17:54:26 2012 +0300

Every chip must have chip_operations

Forcing this rule, chip_ops can be added in the static devicetree
regardless of the existence of the chip.h files.

Take care of NULL .name  case in dummy chip_operations.
Fix typo in mPGA603 socket.

Change-Id: Iec1c23484e85cab3f80a34f2b082088f38ac4de9
Signed-off-by: Kyösti Mälkki kyosti.mal...@gmail.com
---
 src/arch/x86/boot/smbios.c |  3 ++-
 .../intel/socket_mPGA603/socket_mPGA603_400Mhz.c   |  2 +-
 src/devices/Makefile.inc   |  3 +++
 src/devices/dummy_chip_ops.c   | 27 ++
 util/sconfig/main.c| 13 ---
 5 files changed, 37 insertions(+), 11 deletions(-)

diff --git a/src/arch/x86/boot/smbios.c b/src/arch/x86/boot/smbios.c
index 8877f60..a171707 100644
--- a/src/arch/x86/boot/smbios.c
+++ b/src/arch/x86/boot/smbios.c
@@ -278,7 +278,8 @@ static int smbios_walk_device_tree(device_t tree, int 
*handle, unsigned long *cu
int len = 0;
 
for(dev = tree; dev; dev = dev-next) {
-   printk(BIOS_INFO, %s (%s)\n, dev_path(dev), dev-chip_ops ? 
dev-chip_ops-name : );
+   printk(BIOS_INFO, %s (%s)\n, dev_path(dev),
+   (dev-chip_ops  dev-chip_ops-name) ? 
dev-chip_ops-name : );
 
if (dev-ops  dev-ops-get_smbios_data)
len += dev-ops-get_smbios_data(dev, handle, current);
diff --git a/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c 
b/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c
index 9154608..2436f96 100644
--- a/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c
+++ b/src/cpu/intel/socket_mPGA603/socket_mPGA603_400Mhz.c
@@ -2,6 +2,6 @@
 #include chip.h
 
 
-struct chip_opertations cpu_intel_socket_mPGA603_ops = {
+struct chip_operations cpu_intel_socket_mPGA603_ops = {
CHIP_NAME(Socket mPGA603 400Mhz CPU)
 };
diff --git a/src/devices/Makefile.inc b/src/devices/Makefile.inc
index 9a2f71e..cde8b3f 100644
--- a/src/devices/Makefile.inc
+++ b/src/devices/Makefile.inc
@@ -11,6 +11,9 @@ ramstage-y += pnp_device.c
 ramstage-y += pci_ops.c
 ramstage-y += smbus_ops.c
 
+# Work-around for chip.h removal
+ramstage-y += dummy_chip_ops.c
+
 romstage-y+= device_romstage.c
 
 subdirs-y += oprom
diff --git a/src/devices/dummy_chip_ops.c b/src/devices/dummy_chip_ops.c
new file mode 100644
index 000..b29a566
--- /dev/null
+++ b/src/devices/dummy_chip_ops.c
@@ -0,0 +1,27 @@
+#include device/device.h
+
+/* Dummy chip_operations, so every chip has one for sure.
+ * Temporary work-around before total chip.h removal.
+ */
+
+struct chip_operations cpu_via_c3_ops = {};
+struct chip_operations cpu_via_c7_ops = {};
+struct chip_operations drivers_ati_ragexl_ops = {};
+struct chip_operations drivers_dec_21143_ops = {};
+struct chip_operations drivers_generic_generic_ops = {};
+struct chip_operations drivers_oxford_oxpcie_ops = {};
+struct chip_operations drivers_realtek_ops = {};
+struct chip_operations drivers_sil_3114_ops = {};
+struct chip_operations drivers_trident_blade3d_ops = {};
+struct chip_operations southbridge_amd_amd8131_ops = {};
+struct chip_operations southbridge_amd_amd8132_ops = {};
+struct chip_operations southbridge_amd_amd8151_ops = {};
+struct chip_operations southbridge_broadcom_bcm21000_ops = {};
+struct chip_operations southbridge_broadcom_bcm5780_ops = {};
+struct chip_operations southbridge_intel_i82870_ops = {};
+struct chip_operations southbridge_rdc_r8610_ops = {};
+struct chip_operations southbridge_via_k8t890_ops = {};
+struct chip_operations superio_serverengines_pilot_ops = {};
+struct chip_operations superio_smsc_lpc47n207_ops = {};
+struct chip_operations superio_smsc_sio1007_ops = {};
+
diff --git a/util/sconfig/main.c b/util/sconfig/main.c
index fe4c3b8..3aa57f9 100644
--- a/util/sconfig/main.c
+++ b/util/sconfig/main.c
@@ -418,16 +418,11 @@ static void pass1(FILE *fil, struct device *ptr)
fprintf(fil, \t.link_list = NULL,\n);
if (ptr-sibling)
fprintf(fil, \t.sibling = %s,\n, ptr-sibling-name);
-   if (ptr-chip-chiph_exists) {
-   fprintf(fil, #ifndef __PRE_RAM__\n);
-   fprintf(fil, \t.chip_ops = %s_ops,\n, 
ptr-chip-name_underscore);
-   fprintf(fil, #endif\n);
+   fprintf(fil, #ifndef __PRE_RAM__\n);
+   fprintf(fil, \t.chip_ops = %s_ops,\n, 
ptr-chip-name_underscore);
+   fprintf(fil, #endif\n);
+   if (ptr-chip-chiph_exists)
fprintf(fil, \t.chip_info = %s_info_%d,\n,