[coreboot] Patch set updated for coreboot: 0c99cf5 libpayload: New CBFS to support multiple firmware media source.
Hung-Te Lin (hun...@chromium.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2191
-gerrit
commit 0c99cf50e9b9882cc57d3af70067b54ff854c02f
Author: Hung-Te Lin hun...@chromium.org
Date: Fri Jan 25 12:42:40 2013 +0800
libpayload: New CBFS to support multiple firmware media source.
Upgrade CBFS in libpayload to use new media-based implementation from
coreboot
( http://review.coreboot.org/#/c/2182/ ).
Old CBFS functions (cbfs_find, cbfs_find_file, get_cbfs_header) are still
supported, although the recommended way is to use new CBFS API.
To migrate your existing x86 payload source:
- Change cbfs_find to cbfs_get_file
- Change cbfs_find_file to cbfs_get_file_content
- Prefix every CBFS call with a CBFS_DEFAULT_MEDIA argument.
Ex, char *jpeg_data = cbfs_find_file(splash.jpg, CBFS_TYPE_BOOTSPLASH);
= char *jpeg_data = cbfs_get_file_content(
CBFS_DEFAULT_MEDIA, splash.jpg, CBFS_TYPE_BOOTSPLASH);
The legacy setup_cbfs_from_{ram,flash} is also supported, although the
better
equivalent is to make a new media instance:
struct cbfs_media ram_media;
init_cbfs_ram_media(ram_media, start, size);
char *data = cbfs_get_file_content(ram_media, myfile, my_type);
Verified by being successfully linked with filo.
Change-Id: If797bc7e3ba975d7e3be905c59424f7a93b8ce11
Signed-off-by: Hung-Te Lin hun...@chromium.org
---
payloads/libpayload/arch/x86/Makefile.inc | 2 +
payloads/libpayload/arch/x86/rom_media.c | 111 ++
payloads/libpayload/include/cbfs.h| 102 +++--
payloads/libpayload/include/cbfs_core.h | 74 +++---
payloads/libpayload/include/stdint.h | 1 +
payloads/libpayload/libcbfs/Makefile.inc | 1 +
payloads/libpayload/libcbfs/cbfs.c| 232 --
payloads/libpayload/libcbfs/cbfs_core.c | 198 ++---
payloads/libpayload/libcbfs/ram_media.c | 114 +++
9 files changed, 676 insertions(+), 159 deletions(-)
diff --git a/payloads/libpayload/arch/x86/Makefile.inc
b/payloads/libpayload/arch/x86/Makefile.inc
index 8f68b07..0977eb1 100644
--- a/payloads/libpayload/arch/x86/Makefile.inc
+++ b/payloads/libpayload/arch/x86/Makefile.inc
@@ -33,5 +33,7 @@ libc-y += timer.c coreboot.c util.S
libc-y += exec.S virtual.c
libc-y += string.c
+libcbfs-$(CONFIG_CBFS) += rom_media.c
+
# Multiboot support is configurable
libc-$(CONFIG_MULTIBOOT) += multiboot.c
diff --git a/payloads/libpayload/arch/x86/rom_media.c
b/payloads/libpayload/arch/x86/rom_media.c
new file mode 100644
index 000..e9fa94c
--- /dev/null
+++ b/payloads/libpayload/arch/x86/rom_media.c
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#define LIBPAYLOAD
+
+#include cbfs.h
+#include string.h
+
+#ifdef LIBPAYLOAD
+# define printk(x...)
+# define init_default_cbfs_media libpayload_init_default_cbfs_media
+ extern int libpayload_init_default_cbfs_media(struct cbfs_media *media);
+#else
+# include console/console.h
+#endif
+
+// Implementation of memory-mapped ROM media source on X86.
+
+static int x86_rom_open(struct cbfs_media *media) {
+ return 0;
+}
+
+static void *x86_rom_map(struct cbfs_media *media, size_t offset, size_t
count) {
+ void *ptr;
+ // Some address (ex, pointer to master header) may be
[coreboot] Gerrit problem: Not able to sign in
Dear coreboot admins, currently I am not able to sign into Gerrit using my Google Mail account. Not found The page you requested was not found, or you do not have permission to view this page. Do you have similar problems? Thanks, Paul signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Gerrit problem: Not able to sign in
Me too. On Thu, Jan 31, 2013 at 4:52 PM, Paul Menzel paulepan...@users.sourceforge.net wrote: Dear coreboot admins, currently I am not able to sign into Gerrit using my Google Mail account. Not found The page you requested was not found, or you do not have permission to view this page. Do you have similar problems? Thanks, Paul -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- Yours sincerely, WANG Siyuan -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Gerrit problem: Not able to sign in
Hello! Have same issue today. Best regards, Anton Kochkov. On Thu, Jan 31, 2013 at 12:52 PM, Paul Menzel paulepan...@users.sourceforge.net wrote: Dear coreboot admins, currently I am not able to sign into Gerrit using my Google Mail account. Not found The page you requested was not found, or you do not have permission to view this page. Do you have similar problems? Thanks, Paul -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Gerrit problem: Not able to sign in
On 31.01.2013 09:52, Paul Menzel wrote: Dear coreboot admins, currently I am not able to sign into Gerrit using my Google Mail account. Not found The page you requested was not found, or you do not have permission to view this page. Do you have similar problems? Thanks, Paul I have the same problem -- Regards Vladimir 'φ-coder/phcoder' Serbinenko signature.asc Description: OpenPGP digital signature -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Gerrit problem: Not able to sign in
On Thu, Jan 31, 2013 at 09:58:47AM +0100, Vladimir 'φ-coder/phcoder' Serbinenko wrote: The page you requested was not found, or you do not have permission to view this page. Do you have similar problems? Thanks, Paul I have the same problem This is now fixed. Thanks, Ward. -- Ward Vandewege | CTO, Free Software Foundation GPG Key: 25F774AB | http://identi.ca/cure | http://fsf.org/blogs/RSS Do you use free software? Donate to join the FSF and support freedom at http://www.fsf.org/register_form?referrer=859 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: 2e85cbc Add MMCONF resource to AMD fam15 PCI_DOMAIN
Steven Sherk (steven.sh...@se-eng.com) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2248
-gerrit
commit 2e85cbc1e844b627840466f916db30cdb32532a3
Author: Steven Sherk steven.sh...@se-eng.com
Date: Wed Jan 30 16:02:14 2013 -0700
Add MMCONF resource to AMD fam15 PCI_DOMAIN
This is a port of the following:
commit d5c998be99709c92f200b3b08aed2ca3fee2d519
The coreboot resource allocator doesn't respect resources
claimed in the APIC_CLUSTER. Move the MMCONF resource to the
PCI_DOMAIN to prevent overlap with PCI devices.
original-Change-Id: I8541795f69bbdd9041b390103fb901d37e07eeb9
Signed-off-by: Marc Jones marc.jo...@se-eng.com
Change-Id: I6e585d5cf0d46bd58337a6801fb0690ab2dd000c
Signed-off-by: Steven Sherk steven.sh...@se-eng.com
---
src/northbridge/amd/agesa/family15/northbridge.c | 32 +++-
1 file changed, 20 insertions(+), 12 deletions(-)
diff --git a/src/northbridge/amd/agesa/family15/northbridge.c
b/src/northbridge/amd/agesa/family15/northbridge.c
index 2ab0e3e..6fb3105 100644
--- a/src/northbridge/amd/agesa/family15/northbridge.c
+++ b/src/northbridge/amd/agesa/family15/northbridge.c
@@ -341,6 +341,20 @@ static void nb_read_resources(device_t dev)
amdfam15_link_read_bases(dev, nodeid, link-link_num);
}
}
+
+ /*
+* This MMCONF resource must be reserved in the PCI_DOMAIN.
+* It is not honored by the coreboot resource allocator if it is in
+* the APIC_CLUSTER.
+*/
+#if CONFIG_MMCONF_SUPPORT
+ struct resource *resource = new_resource(dev, 0xc0010058);
+ resource-base = CONFIG_MMCONF_BASE_ADDRESS;
+ resource-size = CONFIG_MMCONF_BUS_NUMBER * 4096 * 256;
+ resource-flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+#endif
+
}
@@ -448,6 +462,12 @@ static void nb_set_resources(device_t dev)
assign_resources(bus);
}
}
+
+ /* Print the MMCONF region if it has been reserved. */
+ res = find_resource(dev, 0xc0010058);
+ if (res) {
+ report_resource_stored(dev, res, mmconfig);
+ }
}
static void northbridge_init(struct device *dev)
@@ -1095,22 +1115,10 @@ static void cpu_bus_noop(device_t dev)
static void cpu_bus_read_resources(device_t dev)
{
-#if CONFIG_MMCONF_SUPPORT
- struct resource *resource = new_resource(dev, 0xc0010058);
- resource-base = CONFIG_MMCONF_BASE_ADDRESS;
- resource-size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
- resource-flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-#endif
}
static void cpu_bus_set_resources(device_t dev)
{
- struct resource *resource = find_resource(dev, 0xc0010058);
- if (resource) {
- report_resource_stored(dev, resource, mmconfig);
- }
- pci_dev_set_resources(dev);
}
static struct device_operations cpu_bus_ops = {
--
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Re: [coreboot] New patch to review for coreboot: c3f4e05 Google/snow: romstage that turns on memory and loads a ram stage with cbfs
yeah, these are terrible names. Those pointers are going away soon anyway. ron On Wed, Jan 30, 2013 at 5:11 PM, Bernhard Urban lew...@gmail.com wrote: I can't log into gerrit at the moment, so I reply here. On Thu, Jan 31, 2013 at 1:08 AM, Ronald G. Minnich ger...@coreboot.org wrote: + /* wow, did it work? */ + int i; + u32 *c = (void *)0x4000; what is at 0x4000? what is c? Please use a define or a more descriptive name for the pointer. Thanks, Bernhard -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: ef4cbd5 Family 10: Update for string portability
Mike Loptien (mike.lopt...@se-eng.com) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2249
-gerrit
commit ef4cbd50d51306153aeeea9d067c8e929828d94e
Author: Mike Loptien mike.lopt...@se-eng.com
Date: Thu Jan 31 10:19:31 2013 -0700
Family 10: Update for string portability
Update function messages to be more portable by using
the __func__ compiler command instead of hard coded
function names.
Change-Id: Idf479980e427bbf0399bdbc15045d80f402f6dbe
Signed-off-by: Mike Loptien mike.lopt...@se-eng.com
---
src/northbridge/amd/agesa/family10/northbridge.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/amd/agesa/family10/northbridge.c
b/src/northbridge/amd/agesa/family10/northbridge.c
index 4bdc7b4..c5d570a 100644
--- a/src/northbridge/amd/agesa/family10/northbridge.c
+++ b/src/northbridge/amd/agesa/family10/northbridge.c
@@ -833,12 +833,12 @@ static void amdfam10_domain_enable_resources(device_t dev)
{
u32 val;
/* Must be called after PCI enumeration and resource allocation */
- printk(BIOS_DEBUG, \nFam10 - domain_enable_resources: AmdInitMid.\n);
+ printk(BIOS_DEBUG, \nFam10 - %s: AmdInitMid.\n, __func__);
val = agesawrapper_amdinitmid();
if (val) {
printk(BIOS_DEBUG, agesawrapper_amdinitmid failed: %x \n,
val);
}
- printk(BIOS_DEBUG, ader - leaving domain_enable_resources.\n);
+ printk(BIOS_DEBUG, ader - leaving %s.\n, __func__);
}
--
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[coreboot] New patch to review for coreboot: 228fe81 Family 12: Update for string portability
Mike Loptien (mike.lopt...@se-eng.com) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2250
-gerrit
commit 228fe811dfd8f5bc8c8ffe822392b44b6540e474
Author: Mike Loptien mike.lopt...@se-eng.com
Date: Thu Jan 31 10:17:02 2013 -0700
Family 12: Update for string portability
Update function messages to be more portable by using
the __func__ compiler command instead of hard coded
function names.
Change-Id: I3368a831770df1b8449eb0c97ae4bb24f6678efd
Signed-off-by: Mike Loptien mike.lopt...@se-eng.com
---
src/northbridge/amd/agesa/family12/northbridge.c | 74
1 file changed, 37 insertions(+), 37 deletions(-)
diff --git a/src/northbridge/amd/agesa/family12/northbridge.c
b/src/northbridge/amd/agesa/family12/northbridge.c
index c4b43c5..9c598e8 100644
--- a/src/northbridge/amd/agesa/family12/northbridge.c
+++ b/src/northbridge/amd/agesa/family12/northbridge.c
@@ -99,7 +99,7 @@ static void f1_write_config32(unsigned reg, u32 value)
static u32 amdfam12_nodeid(device_t dev)
{
-printk(BIOS_DEBUG, Fam12h - northbridge.c - amdfam12_nodeid\n);
+printk(BIOS_DEBUG, Fam12h - northbridge.c - %s\n,__func__);
return (dev-path.pci.devfn 3) - CONFIG_CDB;
}
@@ -117,13 +117,13 @@ static void set_vga_enable_reg(u32 nodeid, u32 linkn)
{
u32 val;
-printk(BIOS_DEBUG, \nFam12h - northbridge.c - set_vga_enable_reg -
Start.\n);
+printk(BIOS_DEBUG, \nFam12h - northbridge.c - %s - Start.\n,__func__);
val = 1 | (nodeid4) | (linkn12);
/* it will routing (1)mmio 0xa:0xb (2) io 0x3b0:0x3bb,
0x3c0:0x3df */
f1_write_config32(0xf4, val);
-printk(BIOS_DEBUG, Fam12h - northbridge.c - set_vga_enable_reg - End.\n);
+printk(BIOS_DEBUG, Fam12h - northbridge.c - %s - End.\n,__func__);
}
@@ -133,7 +133,7 @@ static int reg_useable(unsigned reg, device_t goal_dev,
unsigned goal_nodeid,
struct resource *res;
unsigned nodeid, link = 0;
int result;
-printk(BIOS_DEBUG, \nFam12h - northbridge.c - reg_useable - Start.\n);
+printk(BIOS_DEBUG, \nFam12h - northbridge.c - %s - Start.\n,__func__);
res = 0;
for(nodeid = 0; !res (nodeid fx_devs); nodeid++) {
device_t dev;
@@ -153,7 +153,7 @@ static int reg_useable(unsigned reg, device_t goal_dev,
unsigned goal_nodeid,
result = 1;
}
}
-printk(BIOS_DEBUG, Fam12h - northbridge.c - reg_useable - End.\n);
+printk(BIOS_DEBUG, Fam12h - northbridge.c - %s - End.\n,__func__);
return result;
}
@@ -221,7 +221,7 @@ static void amdfam12_link_read_bases(device_t dev, u32
nodeid, u32 link)
{
struct resource *resource;
-printk(BIOS_DEBUG, \nFam12h - northbridge.c - amdfam12_link_read_bases -
Start.\n);
+printk(BIOS_DEBUG, \nFam12h - northbridge.c - %s - Start.\n,__func__);
/* Initialize the io space constraints on the current bus */
resource = amdfam12_find_iopair(dev, nodeid, link);
if (resource) {
@@ -275,7 +275,7 @@ static void amdfam12_link_read_bases(device_t dev, u32
nodeid, u32 link)
}
#endif
}
-printk(BIOS_DEBUG, Fam12h - northbridge.c - amdfam12_link_read_bases -
End.\n);
+printk(BIOS_DEBUG, Fam12h - northbridge.c - %s - End.\n,__func__);
}
static u32 my_find_pci_tolm(struct bus *bus, u32 tolm)
@@ -347,7 +347,7 @@ static void read_resources(device_t dev)
u32 nodeid;
struct bus *link;
-printk(BIOS_DEBUG, \nFam12h - northbridge.c - read_resources - Start.\n);
+printk(BIOS_DEBUG, \nFam12h - northbridge.c - %s - Start.\n,__func__);
nodeid = amdfam12_nodeid(dev);
for(link = dev-link_list; link; link = link-next) {
@@ -355,7 +355,7 @@ static void read_resources(device_t dev)
amdfam12_link_read_bases(dev, nodeid, link-link_num);
}
}
-printk(BIOS_DEBUG, Fam12h - northbridge.c - read_resources - End.\n);
+printk(BIOS_DEBUG, Fam12h - northbridge.c - %s - End.\n,__func__);
}
@@ -366,7 +366,7 @@ static void set_resource(device_t dev, struct resource
*resource,
unsigned reg, link_num;
char buf[50];
-printk(BIOS_DEBUG, \nFam12h - northbridge.c - set_resource - Start.\n);
+printk(BIOS_DEBUG, \nFam12h - northbridge.c - %s - Start.\n,__func__);
/* Make certain the resource has actually been set */
if (!(resource-flags IORESOURCE_ASSIGNED)) {
@@ -406,7 +406,7 @@ static void set_resource(device_t dev, struct resource
*resource,
sprintf(buf, node %x link %x,
nodeid, link_num);
report_resource_stored(dev, resource, buf);
-printk(BIOS_DEBUG, Fam12h - northbridge.c - set_resource - End.\n);
+printk(BIOS_DEBUG, Fam12h - northbridge.c - %s - End.\n,__func__);
}
@@ -418,7 +418,7 @@ static void create_vga_resource(device_t dev, unsigned
nodeid)
{
struct bus *link;
-printk(BIOS_DEBUG, \nFam12h - northbridge.c - create_vga_resource -
Start.\n);
+printk(BIOS_DEBUG,
[coreboot] New patch to review for coreboot: 1fc7956 Family 15tn: Update for string protability
Mike Loptien (mike.lopt...@se-eng.com) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2251
-gerrit
commit 1fc795678160a048ce724a7b9eb6745c3d3d26c7
Author: Mike Loptien mike.lopt...@se-eng.com
Date: Wed Jan 30 16:00:43 2013 -0700
Family 15tn: Update for string protability
Update function messages to be more portable by using
the __func__ compiler command instead of hard coded
function names.
Change-Id: Ib8ab97666340a9481f3ab71f0f347382e964994f
Signed-off-by: Mike Loptien mike.lopt...@se-eng.com
---
src/northbridge/amd/agesa/family15tn/northbridge.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c
b/src/northbridge/amd/agesa/family15tn/northbridge.c
index eb63ead..b05a11c 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -544,7 +544,7 @@ static void domain_enable_resources(device_t dev)
#endif
/* Must be called after PCI enumeration and resource allocation */
- printk(BIOS_DEBUG, \nFam15 - domain_enable_resources: AmdInitMid.\n);
+ printk(BIOS_DEBUG, \nFam15 - %s: AmdInitMid.\n, __func__);
#if CONFIG_HAVE_ACPI_RESUME
if (acpi_slp_type != 3) {
printk(BIOS_DEBUG, agesawrapper_amdinitmid );
@@ -563,7 +563,7 @@ static void domain_enable_resources(device_t dev)
printk(BIOS_DEBUG, passed.\n);
#endif
- printk(BIOS_DEBUG, ader - leaving domain_enable_resources.\n);
+ printk(BIOS_DEBUG, ader - leaving %s.\n, __func__);
}
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
--
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[coreboot] Patch set updated for coreboot: d9fbf8c Family 15tn: Update for string portability
Mike Loptien (mike.lopt...@se-eng.com) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2251
-gerrit
commit d9fbf8c55e8f3688e44679da03027ca60cbb2293
Author: Mike Loptien mike.lopt...@se-eng.com
Date: Wed Jan 30 16:00:43 2013 -0700
Family 15tn: Update for string portability
Update function messages to be more portable by using
the __func__ compiler command instead of hard coded
function names.
Change-Id: Ib8ab97666340a9481f3ab71f0f347382e964994f
Signed-off-by: Mike Loptien mike.lopt...@se-eng.com
---
src/northbridge/amd/agesa/family15tn/northbridge.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c
b/src/northbridge/amd/agesa/family15tn/northbridge.c
index eb63ead..b05a11c 100644
--- a/src/northbridge/amd/agesa/family15tn/northbridge.c
+++ b/src/northbridge/amd/agesa/family15tn/northbridge.c
@@ -544,7 +544,7 @@ static void domain_enable_resources(device_t dev)
#endif
/* Must be called after PCI enumeration and resource allocation */
- printk(BIOS_DEBUG, \nFam15 - domain_enable_resources: AmdInitMid.\n);
+ printk(BIOS_DEBUG, \nFam15 - %s: AmdInitMid.\n, __func__);
#if CONFIG_HAVE_ACPI_RESUME
if (acpi_slp_type != 3) {
printk(BIOS_DEBUG, agesawrapper_amdinitmid );
@@ -563,7 +563,7 @@ static void domain_enable_resources(device_t dev)
printk(BIOS_DEBUG, passed.\n);
#endif
- printk(BIOS_DEBUG, ader - leaving domain_enable_resources.\n);
+ printk(BIOS_DEBUG, ader - leaving %s.\n, __func__);
}
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
--
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[coreboot] Patch set updated for coreboot: 278a96f Fam15tn: Move SPD read from mainboards into wrapper
Martin Roth (martin.r...@se-eng.com) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2190
-gerrit
commit 278a96f565b68ac96969a1c2ce43150f682de9dc
Author: Martin Roth martin.r...@se-eng.com
Date: Sun Jan 20 10:38:58 2013 -0700
Fam15tn: Move SPD read from mainboards into wrapper
Continuing with the mainboard cleanup for F15tn, move the functions
to read the SPD from the mainboards for Thatcher and Parmer into the
wrapper for the northbridge/amd/agesa/family15tn.
Move the SPD address customization for the mainboard into the
devicetree.cb file.
Unrelated side note - Porting.h has an un-closed #pragma pack(1)
that can cause confusing side-effects. AGESA's structures all
use this, but coreboot's don't. Be sure to include the coreboot
.h files BEFORE Porting.h is included, not after.
This fix has been tested.
Change-Id: I89cdd225be61f60c6b8e7020e6f8b879983bbd96
Signed-off-by: Martin Roth martin.r...@se-eng.com
---
src/mainboard/amd/parmer/BiosCallOuts.c| 15 +-
src/mainboard/amd/parmer/BiosCallOuts.h| 3 -
src/mainboard/amd/parmer/Makefile.inc | 2 -
src/mainboard/amd/parmer/devicetree.cb | 16 +-
src/mainboard/amd/parmer/dimmSpd.c | 164
src/mainboard/amd/parmer/dimmSpd.h | 59
src/mainboard/amd/thatcher/BiosCallOuts.c | 15 +-
src/mainboard/amd/thatcher/BiosCallOuts.h | 3 -
src/mainboard/amd/thatcher/Makefile.inc| 2 -
src/mainboard/amd/thatcher/devicetree.cb | 16 +-
src/mainboard/amd/thatcher/dimmSpd.c | 166 -
src/mainboard/amd/thatcher/dimmSpd.h | 59
src/northbridge/amd/agesa/family15tn/Makefile.inc | 3 +-
src/northbridge/amd/agesa/family15tn/chip.h| 28
src/northbridge/amd/agesa/family15tn/dimmSpd.c | 160
src/northbridge/amd/agesa/family15tn/dimmSpd.h | 56 +++
.../amd/agesa/family15tn/fam15tn_callouts.c| 8 +
.../amd/agesa/family15tn/fam15tn_callouts.h| 1 +
18 files changed, 277 insertions(+), 499 deletions(-)
diff --git a/src/mainboard/amd/parmer/BiosCallOuts.c
b/src/mainboard/amd/parmer/BiosCallOuts.c
index 8bfde14..c3e57c8 100644
--- a/src/mainboard/amd/parmer/BiosCallOuts.c
+++ b/src/mainboard/amd/parmer/BiosCallOuts.c
@@ -19,7 +19,6 @@
#include agesawrapper.h
#include amdlib.h
-#include dimmSpd.h
#include BiosCallOuts.h
#include Ids.h
#include OptionsIds.h
@@ -33,10 +32,10 @@ STATIC CONST BIOS_CALLOUT_STRUCT BiosCallouts[] =
{AGESA_DEALLOCATE_BUFFER,fam15tn_DeallocateBuffer },
{AGESA_DO_RESET, fam15tn_Reset },
{AGESA_LOCATE_BUFFER,fam15tn_LocateBuffer },
- {AGESA_READ_SPD, BiosReadSpd },
+ {AGESA_READ_SPD, fam15tn_ReadSpd },
{AGESA_READ_SPD_RECOVERY,fam15tn_DefaultRet },
- {AGESA_RUNFUNC_ONAP, fam15tn_RunFuncOnAp},
- {AGESA_GET_IDS_INIT_DATA,fam15tn_GetIdsInitData },
+ {AGESA_RUNFUNC_ONAP, fam15tn_RunFuncOnAp },
+ {AGESA_GET_IDS_INIT_DATA,fam15tn_GetIdsInitData },
{AGESA_HOOKBEFORE_DQS_TRAINING, fam15tn_HookBeforeDQSTraining },
{AGESA_HOOKBEFORE_EXIT_SELF_REF, fam15tn_HookBeforeExitSelfRefresh },
{AGESA_FCH_OEM_CALLOUT, Fch_Oem_config },
@@ -63,14 +62,6 @@ AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID
*ConfigPtr)
return CalloutStatus;
}
-AGESA_STATUS BiosReadSpd (UINT32 Func, UINT32 Data, VOID *ConfigPtr)
-{
- AGESA_STATUS Status;
- Status = AmdMemoryReadSPD (Func, Data, ConfigPtr);
-
- return Status;
-}
-
/**
* AMD Parmer Platform ALC272 Verb Table
*/
diff --git a/src/mainboard/amd/parmer/BiosCallOuts.h
b/src/mainboard/amd/parmer/BiosCallOuts.h
index 66db8cd..d42683e 100644
--- a/src/mainboard/amd/parmer/BiosCallOuts.h
+++ b/src/mainboard/amd/parmer/BiosCallOuts.h
@@ -25,9 +25,6 @@
/* CALLOUT Initialization */
AGESA_STATUS GetBiosCallout (UINT32 Func, UINT32 Data, VOID *ConfigPtr);
-/* AGESA ADVANCED CALLOUTS - MEMORY */
-AGESA_STATUS BiosReadSpd (UINT32 Func,UINT32 Data,VOID *ConfigPtr);
-
/* FCH OEM Config*/
AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr);
diff --git a/src/mainboard/amd/parmer/Makefile.inc
b/src/mainboard/amd/parmer/Makefile.inc
index de3163d..a83297a 100644
--- a/src/mainboard/amd/parmer/Makefile.inc
+++ b/src/mainboard/amd/parmer/Makefile.inc
@@ -19,12 +19,10 @@
romstage-y += buildOpts.c
romstage-y += agesawrapper.c
-romstage-y += dimmSpd.c
romstage-y += BiosCallOuts.c
romstage-y += PlatformGnbPcie.c
ramstage-y += buildOpts.c
ramstage-y += agesawrapper.c
-ramstage-y += dimmSpd.c
ramstage-y += BiosCallOuts.c
ramstage-y +=
[coreboot] Patch merged into coreboot/master: 79e36d9 Improve how our printk calls do_div by using constants.
the following patch was just integrated into master: commit 79e36d90608a929c33b655c6fb6376f33f332e6f Author: Ronald G. Minnich rminn...@gmail.com Date: Wed Jan 30 14:29:34 2013 -0800 Improve how our printk calls do_div by using constants. The do_div code has a nice optimization in it when it is called with constants. The current highly generalized use of it defeats those optimizations and causes trouble on ARM, resulting in a complex and buggy code path. Since we only need to print in bases 8, 10, and 16, do a minor restructuring of the code so that we call do_div with constants. If you need base 2, print in base 16 and do it in your head. :-) This fixes an ongoing problem with ARM, will not harm X86, and will help PPC should we ever want to support it again. Plus, I don't have to ever try to understand the div64 assembly and where it's going wrong :-) Change-Id: I6a480011916eb0834e05c5bb10909d83330fe797 Signed-off-by: Ronald G. Minnich rminn...@gmail.com Reviewed-on: http://review.coreboot.org/2235 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks dhend...@chromium.org Reviewed-by: Stefan Reinauer stefan.reina...@coreboot.org Build-Tested: build bot (Jenkins) at Wed Jan 30 23:38:01 2013, giving +1 Reviewed-By: Stefan Reinauer stefan.reina...@coreboot.org at Thu Jan 31 01:23:18 2013, giving +1 Reviewed-By: David Hendricks dhend...@chromium.org at Thu Jan 31 01:04:27 2013, giving +2 See http://review.coreboot.org/2235 for details. -gerrit -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Guide lines: Prepend commit summary with component
Am Mittwoch, den 30.01.2013, 21:47 +0100 schrieb Peter Stuge: David Hendricks wrote: If you wish to focus only on a particular part of the codebase It's more about getting an overview of what has changed. It is impossible to discern whether Fix MMU setup is at all relevant for my ThinkPad from the message alone. Maybe some setup was wrong - what do I know. armv7: Fix MMU setup however makes it clear what the change is. Thanks Peter. That example made my point clear. specify the directories/files you wish to look at when running git log. The Web interfaces make this stuff hard. It's the other way around, for creating an overview. At least I am also doing it this way. Or do Peter or I miss some trick for getting this overview. The commit message represents the commit. The commit contains a root tree. Commits only affecting subsets of the code isn't really an accurate representation of how the repository works. Actually, I think it would look kind of ugly to do git log src/arch/x86 and see every commit cluttered with some cookie-cutter prefix. Maybe - or maybe it is simply expected. Within x86 it's possible that there will be several different and distinct parts. One other point, supporting that prepending is the right thing to do, is that the Linux kernel is also prepending each commit summary with the subsystem it touches. Thanks, Paul signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Different Google copyright notices: »The Chromium OS Authors. ?«
Am Mittwoch, den 30.01.2013, 01:06 +0100 schrieb Peter Stuge: ron minnich wrote: In the community we can of course not know what is correct when, ah yes well I do kind of wonder if *I* know what I'm doing half the time :-) I guess the concern was that perhaps there was a single correct notice to be used, and that some of you guys made a mistake somewhere. I don't expect that you make such mistakes, but I guess that's what Paul meant. Well, thanks to Hung-Te’s clarifying answer, at least the inconsistent spelling of »The Chromium*OS Authors.« with or without space shows that a mistake indeed was made while copying. Also I assume, that the inconsistency in adding »All rights reserved.« or having the copyright sign spelled with a capitalized »(C)« or not »(c)« is a mistake (and not a policy decision). So to keep the differences between files small, it would be awesome if some Google/Chromium OS developer could unify that and set up some pre-commit hook checking that with each commit. Thanks, Paul signature.asc Description: This is a digitally signed message part -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: 62599e3 Google/snow: romstage that turns on memory and loads a ram stage with cbfs
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2245 -gerrit commit 62599e30a95bd768fe54d36ff061c81574512ffb Author: Ronald G. Minnich rminn...@gmail.com Date: Wed Jan 30 15:55:36 2013 -0800 Google/snow: romstage that turns on memory and loads a ram stage with cbfs This is a first cut at a romstage. It sets up memory, although that needs some work; and finds and loads a ramstage. Change-Id: I02a0eb48828500bf83c3c57d4bacb396e58bf9a5 Signed-off-by: Ronald G. Minnich rminn...@gmail.com Signed-off-by: David Hendricks dhend...@chromium.org --- src/arch/armv7/Makefile.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 78fa671..00c1de5 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -323,4 +323,3 @@ $(objgenerated)/crt0.romstage.o: $(objgenerated)/crt0.s $(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h $(obj)/build.h @printf CC $(subst $(obj)/,,$(@))\n $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $ -o $@ - -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: 23b9620 lib: Prevent unaligned memory access in LZMA decode library.
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/2246
-gerrit
commit 23b962036c01e42452157afcf07d3fd0c29ebc50
Author: Hung-Te Lin hun...@chromium.org
Date: Thu Jan 31 12:14:46 2013 +0800
lib: Prevent unaligned memory access in LZMA decode library.
LZMA decode library used to retrieve output size by:
outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
'src' is aligned but LZMA_PROPERTIES_SIZE may refer to an unaligned address
like
src+5, and using that as integer pointer may fail on platforms like ARM.
To fix this, use memcpy to copy into aligned variable outSize.
Change-Id: If678e735cb270c3e5e29f36f1fad318096bf7d59
Signed-off-by: Hung-Te Lin hun...@chromium.org
---
src/lib/lzma.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/lib/lzma.c b/src/lib/lzma.c
index f0b88c1..a2d91d1 100644
--- a/src/lib/lzma.c
+++ b/src/lib/lzma.c
@@ -31,7 +31,8 @@ unsigned long ulzma(unsigned char * src, unsigned char * dst)
unsigned char scratchpad[15980];
memcpy(properties, src, LZMA_PROPERTIES_SIZE);
- outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
+ /* Do memcpy to prevent unaligned memory access. */
+ memcpy(outSize, src + LZMA_PROPERTIES_SIZE, sizeof(outSize));
if (LzmaDecodeProperties(state.Properties, properties,
LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) {
printk(BIOS_WARNING, lzma: Incorrect stream properties.\n);
return 0;
--
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[coreboot] New patch to review for coreboot: c2ba5f8 armv7: unify stage hand-off routines
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2254 -gerrit commit c2ba5f86d00ad43ed2d7828c3b840f79751938a7 Author: David Hendricks dhend...@chromium.org Date: Thu Jan 31 17:05:50 2013 -0800 armv7: unify stage hand-off routines This replaces the current stage-specific exit/entry functions with generic versions. Now all stages compile with stage_entry(), which is placed at .text.stage_entry.armv7, and stage_exit(). Snow is also updated to avoid breakage. Change-Id: I953a2c4b8121bd4b66c3362557997a9ca3aa53b0 Signed-off-by: David Hendricks dhend...@chromium.org --- src/arch/armv7/Makefile.inc| 40 - src/arch/armv7/bootblock_simple.c | 8 ++-- src/arch/armv7/coreboot_ram.ld | 1 + src/arch/armv7/include/arch/stages.h | 28 src/arch/armv7/lib/Makefile.inc| 2 - src/arch/armv7/lib/c_start.S | 9 src/arch/armv7/romstage.ld | 2 +- src/arch/armv7/romstage_main.c | 29 - src/arch/armv7/stages.c| 45 src/mainboard/google/snow/Makefile.inc | 1 + src/mainboard/google/snow/mainboard.c | 2 +- src/mainboard/google/snow/ramstage.c | 32 ++ src/mainboard/google/snow/romstage.c | 78 +++--- 13 files changed, 203 insertions(+), 74 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index ba734a6..78fa671 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -104,6 +104,14 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(OBJCOPY) --add-gnu-debuglink=$ $@.tmp mv $@.tmp $@ +stages_c = $(src)/arch/armv7/stages.c +stages_o = $(obj)/arch/armv7/stages.o + +$(stages_o): $(stages_c) + @printf CC $(subst $(obj)/,,$(@))\n + $(CC) -Wa,-acdlns -I. $(INCLUDES) -c -o $@ $ -marm + + # Build the coreboot_ram (stage 2) @@ -115,12 +123,12 @@ else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/coreboot_ram.ld $ endif -$(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) +$(objgenerated)/coreboot_ram.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME) @printf CC $(subst $(obj)/,,$(@))\n ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --wrap __do_div64 --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group else - $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif @@ -239,18 +247,11 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) @printf GEN$(subst $(obj)/,,$(@))\n printf '$(foreach crt0,$(bootblock_inc),#include $(crt0)\n)' $@ -bootblock_exit_c = $(src)/arch/armv7/bootblock_exit.c -bootblock_exit_o = $(obj)/arch/armv7/bootblock_exit.o - -$(bootblock_exit_o): $(bootblock_exit_c) - @printf CC $(subst $(obj)/,,$(@))\n - $(CC) -Wa,-acdlns -I. $(INCLUDES) -c -o $@ $ -marm - $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf CC $(subst $(obj)/,,$(@))\n $(CC) -Wa,-acdlns -c -o $@ $ $(basename $@).disasm -BOOTBLOCK_OBJS = $(objgenerated)/bootblock.o $(bootblock_exit_o) +#BOOTBLOCK_OBJS = $(objgenerated)/bootblock.o $(bootblock_exit_o) $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf CC $(subst $(obj)/,,$(@))\n @@ -262,39 +263,32 @@ $(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ,,$(CONFIG_BOOTBLOCK_S $ $(objgenerated)/bootblock.inc.d $(CC) -c -S $(CFLAGS) -I. $(INCLUDES) $ -o $@ -$(objcbfs)/bootblock.debug: $(BOOTBLOCK_OBJS) $(objgenerated)/bootblock.ld +$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld @printf LINK $(subst $(obj)/,,$(@))\n ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m armelf_linux_eabi -static -o $@.tmp -L$(obj) $ -T $(objgenerated)/bootblock.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $(BOOTBLOCK_OBJS) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $(objgenerated)/bootblock.o $(stages) $(LIBGCC_FILE_NAME) -Wl,--end-group endif
[coreboot] Patch set updated for coreboot: 9462558 Google/snow: romstage that turns on memory and loads a ram stage with cbfs
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2245 -gerrit commit 94625583bda9028498ce29d957cf2b7b38ea665a Author: Ronald G. Minnich rminn...@gmail.com Date: Wed Jan 30 15:55:36 2013 -0800 Google/snow: romstage that turns on memory and loads a ram stage with cbfs This is a first cut at a romstage. It sets up memory, although that needs some work; and finds and loads a ramstage. Change-Id: I02a0eb48828500bf83c3c57d4bacb396e58bf9a5 Signed-off-by: Ronald G. Minnich rminn...@gmail.com Signed-off-by: David Hendricks dhend...@chromium.org --- src/arch/armv7/Makefile.inc | 1 - 1 file changed, 1 deletion(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 78fa671..00c1de5 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -323,4 +323,3 @@ $(objgenerated)/crt0.romstage.o: $(objgenerated)/crt0.s $(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h $(obj)/build.h @printf CC $(subst $(obj)/,,$(@))\n $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/config.h -include $(obj)/build.h -I. -I$(src) $ -o $@ - -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: fc12483 exynos5250: #define the dram controller interleaving size
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/2255
-gerrit
commit fc1248392c682d28e76aa092841f5957b4b31493
Author: David Hendricks dhend...@chromium.org
Date: Thu Jan 31 17:22:50 2013 -0800
exynos5250: #define the dram controller interleaving size
Change-Id: Iab184aa85be68b6ca5107d278d2fe821e5b2e611
Signed-off-by: David Hendricks dhend...@chromium.org
---
src/cpu/samsung/exynos5250/dmc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/cpu/samsung/exynos5250/dmc.h b/src/cpu/samsung/exynos5250/dmc.h
index b778e09..9b1f293 100644
--- a/src/cpu/samsung/exynos5250/dmc.h
+++ b/src/cpu/samsung/exynos5250/dmc.h
@@ -175,6 +175,8 @@ enum mem_manuf {
MEM_MANUF_COUNT = 2, // fancy that.
};
+#define DMC_INTERLEAVE_SIZE0x1f
+
/* CONCONTROL register fields */
#define CONCONTROL_DFI_INIT_START_SHIFT28
#define CONCONTROL_RD_FETCH_SHIFT 12
--
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[coreboot] New patch to review for coreboot: 9d041ec exynos5250: hard-code array index for memory timings
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/2256
-gerrit
commit 9d041ece89e064f5f4c5d510042a0b0348596c6c
Author: David Hendricks dhend...@chromium.org
Date: Thu Jan 31 17:25:16 2013 -0800
exynos5250: hard-code array index for memory timings
Discovering memory timings is a bit complicated due to the need
to obtain and decode board config. To make things worse, the imported
code makes a mess of dependencies. Hard-code the memory timings
for now to get us further along (the instability won't really matter
until we're loading depthcharge anyway).
Change-Id: I1f341ad597db0c31ed4ae6bc703fc22b6596a803
Signed-off-by: David Hendricks dhend...@chromium.org
---
src/cpu/samsung/exynos5250/clock_init.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/cpu/samsung/exynos5250/clock_init.c
b/src/cpu/samsung/exynos5250/clock_init.c
index 565abe1..421d880 100644
--- a/src/cpu/samsung/exynos5250/clock_init.c
+++ b/src/cpu/samsung/exynos5250/clock_init.c
@@ -725,6 +725,9 @@ struct arm_clk_ratios *get_arm_ratios(void)
struct mem_timings *clock_get_mem_timings(void)
{
+ /* FIXME: hard-coded for now */
+ return mem_timings[0];
+#if 0
struct mem_timings *mem;
enum ddr_mode mem_type;
enum mem_manuf mem_manuf;
@@ -742,6 +745,7 @@ struct mem_timings *clock_get_mem_timings(void)
}
}
return NULL;
+#endif
}
void system_clock_init(void)
--
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[coreboot] Patch set updated for coreboot: 8a8ec00 exynos5250: #define the dram controller interleaving size
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/2255
-gerrit
commit 8a8ec0014698cde516d4fdb2a268792e25467d9d
Author: David Hendricks dhend...@chromium.org
Date: Thu Jan 31 17:22:50 2013 -0800
exynos5250: #define the dram controller interleaving size
Change-Id: Iab184aa85be68b6ca5107d278d2fe821e5b2e611
Signed-off-by: David Hendricks dhend...@chromium.org
---
src/cpu/samsung/exynos5250/dmc.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/cpu/samsung/exynos5250/dmc.h b/src/cpu/samsung/exynos5250/dmc.h
index b778e09..9b1f293 100644
--- a/src/cpu/samsung/exynos5250/dmc.h
+++ b/src/cpu/samsung/exynos5250/dmc.h
@@ -175,6 +175,8 @@ enum mem_manuf {
MEM_MANUF_COUNT = 2, // fancy that.
};
+#define DMC_INTERLEAVE_SIZE0x1f
+
/* CONCONTROL register fields */
#define CONCONTROL_DFI_INIT_START_SHIFT28
#define CONCONTROL_RD_FETCH_SHIFT 12
--
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[coreboot] Patch set updated for coreboot: adaff84 armv7: unify stage hand-off routines
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2254 -gerrit commit adaff84abec4a4236f85689dda387f0a9efee2fa Author: David Hendricks dhend...@chromium.org Date: Thu Jan 31 17:05:50 2013 -0800 armv7: unify stage hand-off routines This replaces the current stage-specific exit/entry functions with generic versions. Now all stages compile with stage_entry(), which is placed at .text.stage_entry.armv7, and stage_exit(). Snow's ramstage files are also updated to avoid build breakage. Change-Id: I953a2c4b8121bd4b66c3362557997a9ca3aa53b0 Signed-off-by: David Hendricks dhend...@chromium.org --- src/arch/armv7/Makefile.inc| 40 +- src/arch/armv7/bootblock_simple.c | 8 +++--- src/arch/armv7/coreboot_ram.ld | 1 + src/arch/armv7/include/arch/stages.h | 28 + src/arch/armv7/lib/Makefile.inc| 2 -- src/arch/armv7/lib/c_start.S | 9 --- src/arch/armv7/romstage.ld | 2 +- src/arch/armv7/romstage_main.c | 29 -- src/arch/armv7/stages.c| 45 ++ src/mainboard/google/snow/Makefile.inc | 1 + src/mainboard/google/snow/mainboard.c | 2 +- src/mainboard/google/snow/ramstage.c | 32 12 files changed, 131 insertions(+), 68 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index ba734a6..78fa671 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -104,6 +104,14 @@ $(objcbfs)/%.elf: $(objcbfs)/%.debug $(OBJCOPY) --add-gnu-debuglink=$ $@.tmp mv $@.tmp $@ +stages_c = $(src)/arch/armv7/stages.c +stages_o = $(obj)/arch/armv7/stages.o + +$(stages_o): $(stages_c) + @printf CC $(subst $(obj)/,,$(@))\n + $(CC) -Wa,-acdlns -I. $(INCLUDES) -c -o $@ $ -marm + + # Build the coreboot_ram (stage 2) @@ -115,12 +123,12 @@ else $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/coreboot_ram.ld $ endif -$(objgenerated)/coreboot_ram.o: $$(ramstage-objs) $(LIBGCC_FILE_NAME) +$(objgenerated)/coreboot_ram.o: $(stages_o) $$(ramstage-objs) $(LIBGCC_FILE_NAME) @printf CC $(subst $(obj)/,,$(@))\n ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m -m armelf_linux_eabi -r -o $@ --wrap __divdi3 --wrap __udivdi3 --wrap __moddi3 --wrap __umoddi3 --wrap __uidiv --wrap __do_div64 --start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) --end-group else - $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--start-group $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif @@ -239,18 +247,11 @@ $(objgenerated)/bootblock_inc.S: $$(bootblock_inc) @printf GEN$(subst $(obj)/,,$(@))\n printf '$(foreach crt0,$(bootblock_inc),#include $(crt0)\n)' $@ -bootblock_exit_c = $(src)/arch/armv7/bootblock_exit.c -bootblock_exit_o = $(obj)/arch/armv7/bootblock_exit.o - -$(bootblock_exit_o): $(bootblock_exit_c) - @printf CC $(subst $(obj)/,,$(@))\n - $(CC) -Wa,-acdlns -I. $(INCLUDES) -c -o $@ $ -marm - $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf CC $(subst $(obj)/,,$(@))\n $(CC) -Wa,-acdlns -c -o $@ $ $(basename $@).disasm -BOOTBLOCK_OBJS = $(objgenerated)/bootblock.o $(bootblock_exit_o) +#BOOTBLOCK_OBJS = $(objgenerated)/bootblock.o $(bootblock_exit_o) $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf CC $(subst $(obj)/,,$(@))\n @@ -262,39 +263,32 @@ $(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ,,$(CONFIG_BOOTBLOCK_S $ $(objgenerated)/bootblock.inc.d $(CC) -c -S $(CFLAGS) -I. $(INCLUDES) $ -o $@ -$(objcbfs)/bootblock.debug: $(BOOTBLOCK_OBJS) $(objgenerated)/bootblock.ld +$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld @printf LINK $(subst $(obj)/,,$(@))\n ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m armelf_linux_eabi -static -o $@.tmp -L$(obj) $ -T $(objgenerated)/bootblock.ld else - $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $(BOOTBLOCK_OBJS) $(LIBGCC_FILE_NAME) -Wl,--end-group + $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(objgenerated)/bootblock.ld -Wl,--start-group $(objgenerated)/bootblock.o $(stages) $(LIBGCC_FILE_NAME) -Wl,--end-group endif
[coreboot] Patch set updated for coreboot: 39fbb46 Google/snow: romstage that turns on memory and loads a ram stage with cbfs
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/2245
-gerrit
commit 39fbb46989c17575de205e159fe27bed87cc8c3a
Author: Ronald G. Minnich rminn...@gmail.com
Date: Wed Jan 30 15:55:36 2013 -0800
Google/snow: romstage that turns on memory and loads a ram stage with cbfs
This is a first cut at a romstage. It sets up memory, although that
needs some work; and finds and loads a ramstage.
Change-Id: I02a0eb48828500bf83c3c57d4bacb396e58bf9a5
Signed-off-by: Ronald G. Minnich rminn...@gmail.com
Signed-off-by: David Hendricks dhend...@chromium.org
---
src/arch/armv7/Makefile.inc | 1 -
src/mainboard/google/snow/romstage.c | 89 +---
2 files changed, 72 insertions(+), 18 deletions(-)
diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc
index 78fa671..00c1de5 100644
--- a/src/arch/armv7/Makefile.inc
+++ b/src/arch/armv7/Makefile.inc
@@ -323,4 +323,3 @@ $(objgenerated)/crt0.romstage.o: $(objgenerated)/crt0.s
$(objgenerated)/crt0.s: $(objgenerated)/crt0.romstage.S $(obj)/config.h
$(obj)/build.h
@printf CC $(subst $(obj)/,,$(@))\n
$(CC) -MMD -x assembler-with-cpp -E -I$(src)/include
-I$(src)/arch/armv7/include -I$(obj) -include $(obj)/config.h -include
$(obj)/build.h -I. -I$(src) $ -o $@
-
diff --git a/src/mainboard/google/snow/romstage.c
b/src/mainboard/google/snow/romstage.c
index 3f3f3ec..fae371a 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -19,35 +19,90 @@
#include types.h
#include system.h
-#include cache.h
-
-#if 0
-#include arch/io.h
-/* FIXME: make i2c.h use standard types */
-#define uchar unsigned char
-#define uint unsigned int
-#include device/i2c.h
+#include cache.h
+#include cbfs.h
+#include common.h
-#include cpu/samsung/s5p-common/s3c24x0_i2c.h
-#include cpu/samsung/exynos5250/dmc.h
-#include cpu/samsung/exynos5250/power.h
+#include cpu/samsung/exynos5250/setup.h
+#include cpu/samsung/exynos5250/dmc.h
#include cpu/samsung/exynos5250/clock_init.h
-#include cpu/samsung/exynos5-common/uart.h
-#endif
#include console/console.h
+#include arch/bootblock_exit.h
+#include arch/stages.h
-void main(void);
void main(void)
{
-// volatile unsigned long *pshold = (unsigned long *)0x1004330c;
+ struct cbfs_media cbfs;
// i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
// power_init();
// clock_init();
// exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
console_init();
printk(BIOS_INFO, hello from romstage\n);
+ struct mem_timings *mem;
+ int ret;
+
+ mem = clock_get_mem_timings();
+ printk(BIOS_SPEW, clock_get_mem_timings returns 0x%p\n, mem);
+ printk(BIOS_SPEW, man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n,
+ mem-mem_manuf,
+ mem-mem_type,
+ mem-mpll_mdiv,
+ mem-frequency_mhz);
+
+ ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE);
+ if (ret) {
+ printk(BIOS_ERR, Memory controller init failed, err: %x\n,
+ ret);
+ while(1);
+ }
+
+ printk(BIOS_INFO, ddr3_init done\n);
+ /* wow, did it work? */
+ int i;
+ u32 *c = (void *)CONFIG_RAMBASE;
+
+// mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024);
+// printk(BIOS_INFO, mmu_setup done\n);
+ for(i = 0; i 16384; i++)
+ c[i] = i+32768;
+ for(i = 0; i 16384; i++)
+ if (c[i] != i+32768)
+ printk(BIOS_SPEW, BADc[%02x]: %02x,, i, c[i]);
+ for(i = 0; i 1048576; i++)
+ c[i] = 0;
+ ret = init_default_cbfs_media(cbfs);
+ if (ret){
+ printk(BIOS_ERR, init_default_cbfs_media returned %d: HALT\n,
+ ret);
+ while (1);
+ }
+
+ struct cbfs_stage *stage = (struct cbfs_stage *)
+ cbfs_get_file_content(cbfs, fallback/coreboot_ram,
+ CBFS_TYPE_STAGE);
+ printk(BIOS_ERR, Stage: %p\n, stage);
+ printk(BIOS_ERR, loading stage %s @ 0x%x (0x%x bytes),entry @ 0x%p\n,
+ ram stage,
+ (uint32_t) stage-load, stage-memlen,
+ (void *)(u32)stage-entry);
+
+#if 0
+ /* for reference and testing ... we should be able to remove soon */
+// c = (void *)(u32)(stage-load + stage-len);
+ c = (void *)(u32)(stage-load);
+ printk(BIOS_ERR, memzero 0x%x words starting at %p\n,
+ (stage-memlen /*- stage-len*/)/4, c);
+ for(i = 0; i (stage-memlen /*- stage-len*/)/4; i++){
+ printk(BIOS_INFO, %p, , c[i]);
+ c[i] = 0;
+ }
+#endif
+
+ void *entry = cbfs_load_stage(cbfs, fallback/coreboot_ram);
+ printk(BIOS_INFO, entry is %p\n, entry);
-// *pshold =
[coreboot] Patch set updated for coreboot: 9daa5a8 lib: Prevent unaligned memory access in LZMA decode library.
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/2246
-gerrit
commit 9daa5a800c9827569dc356834f4b80106ae184b9
Author: Hung-Te Lin hun...@chromium.org
Date: Thu Jan 31 12:14:46 2013 +0800
lib: Prevent unaligned memory access in LZMA decode library.
LZMA decode library used to retrieve output size by:
outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
'src' is aligned but LZMA_PROPERTIES_SIZE may refer to an unaligned address
like
src+5, and using that as integer pointer may fail on platforms like ARM.
To fix this, use memcpy to copy into aligned variable outSize.
Change-Id: If678e735cb270c3e5e29f36f1fad318096bf7d59
Signed-off-by: Hung-Te Lin hun...@chromium.org
---
src/lib/lzma.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/lib/lzma.c b/src/lib/lzma.c
index f0b88c1..a2d91d1 100644
--- a/src/lib/lzma.c
+++ b/src/lib/lzma.c
@@ -31,7 +31,8 @@ unsigned long ulzma(unsigned char * src, unsigned char * dst)
unsigned char scratchpad[15980];
memcpy(properties, src, LZMA_PROPERTIES_SIZE);
- outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
+ /* Do memcpy to prevent unaligned memory access. */
+ memcpy(outSize, src + LZMA_PROPERTIES_SIZE, sizeof(outSize));
if (LzmaDecodeProperties(state.Properties, properties,
LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) {
printk(BIOS_WARNING, lzma: Incorrect stream properties.\n);
return 0;
--
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[coreboot] Patch set updated for coreboot: 92ef230 exynos5250: hard-code array index for memory timings
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/2256
-gerrit
commit 92ef2301ee0fe8c5e92aceccbaa6cc17e30c8427
Author: David Hendricks dhend...@chromium.org
Date: Thu Jan 31 17:25:16 2013 -0800
exynos5250: hard-code array index for memory timings
Discovering memory timings is a bit complicated due to the need
to obtain and decode board config. To make things worse, the imported
code makes a mess of dependencies. Hard-code the memory timings
for now to get us further along (the instability won't really matter
until we're loading depthcharge anyway).
Change-Id: I1f341ad597db0c31ed4ae6bc703fc22b6596a803
Signed-off-by: David Hendricks dhend...@chromium.org
---
src/cpu/samsung/exynos5250/clock_init.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/cpu/samsung/exynos5250/clock_init.c
b/src/cpu/samsung/exynos5250/clock_init.c
index 565abe1..421d880 100644
--- a/src/cpu/samsung/exynos5250/clock_init.c
+++ b/src/cpu/samsung/exynos5250/clock_init.c
@@ -725,6 +725,9 @@ struct arm_clk_ratios *get_arm_ratios(void)
struct mem_timings *clock_get_mem_timings(void)
{
+ /* FIXME: hard-coded for now */
+ return mem_timings[0];
+#if 0
struct mem_timings *mem;
enum ddr_mode mem_type;
enum mem_manuf mem_manuf;
@@ -742,6 +745,7 @@ struct mem_timings *clock_get_mem_timings(void)
}
}
return NULL;
+#endif
}
void system_clock_init(void)
--
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[coreboot] Patch set updated for coreboot: 21f5a2e snow: make romstage init DRAM controller and call ramstage
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/2245
-gerrit
commit 21f5a2ee7aa069ca8a53040c5962cca77e734098
Author: Ronald G. Minnich rminn...@gmail.com
Date: Wed Jan 30 15:55:36 2013 -0800
snow: make romstage init DRAM controller and call ramstage
This is a first cut at a romstage. It sets up memory, although that
needs some work; and finds and loads a ramstage.
Change-Id: I02a0eb48828500bf83c3c57d4bacb396e58bf9a5
Signed-off-by: Ronald G. Minnich rminn...@gmail.com
Signed-off-by: David Hendricks dhend...@chromium.org
---
src/mainboard/google/snow/romstage.c | 89 +---
1 file changed, 72 insertions(+), 17 deletions(-)
diff --git a/src/mainboard/google/snow/romstage.c
b/src/mainboard/google/snow/romstage.c
index 3f3f3ec..fae371a 100644
--- a/src/mainboard/google/snow/romstage.c
+++ b/src/mainboard/google/snow/romstage.c
@@ -19,35 +19,90 @@
#include types.h
#include system.h
-#include cache.h
-
-#if 0
-#include arch/io.h
-/* FIXME: make i2c.h use standard types */
-#define uchar unsigned char
-#define uint unsigned int
-#include device/i2c.h
+#include cache.h
+#include cbfs.h
+#include common.h
-#include cpu/samsung/s5p-common/s3c24x0_i2c.h
-#include cpu/samsung/exynos5250/dmc.h
-#include cpu/samsung/exynos5250/power.h
+#include cpu/samsung/exynos5250/setup.h
+#include cpu/samsung/exynos5250/dmc.h
#include cpu/samsung/exynos5250/clock_init.h
-#include cpu/samsung/exynos5-common/uart.h
-#endif
#include console/console.h
+#include arch/bootblock_exit.h
+#include arch/stages.h
-void main(void);
void main(void)
{
-// volatile unsigned long *pshold = (unsigned long *)0x1004330c;
+ struct cbfs_media cbfs;
// i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
// power_init();
// clock_init();
// exynos_pinmux_config(PERIPH_ID_UART3, PINMUX_FLAG_NONE);
console_init();
printk(BIOS_INFO, hello from romstage\n);
+ struct mem_timings *mem;
+ int ret;
+
+ mem = clock_get_mem_timings();
+ printk(BIOS_SPEW, clock_get_mem_timings returns 0x%p\n, mem);
+ printk(BIOS_SPEW, man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n,
+ mem-mem_manuf,
+ mem-mem_type,
+ mem-mpll_mdiv,
+ mem-frequency_mhz);
+
+ ret = ddr3_mem_ctrl_init(mem, DMC_INTERLEAVE_SIZE);
+ if (ret) {
+ printk(BIOS_ERR, Memory controller init failed, err: %x\n,
+ ret);
+ while(1);
+ }
+
+ printk(BIOS_INFO, ddr3_init done\n);
+ /* wow, did it work? */
+ int i;
+ u32 *c = (void *)CONFIG_RAMBASE;
+
+// mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024);
+// printk(BIOS_INFO, mmu_setup done\n);
+ for(i = 0; i 16384; i++)
+ c[i] = i+32768;
+ for(i = 0; i 16384; i++)
+ if (c[i] != i+32768)
+ printk(BIOS_SPEW, BADc[%02x]: %02x,, i, c[i]);
+ for(i = 0; i 1048576; i++)
+ c[i] = 0;
+ ret = init_default_cbfs_media(cbfs);
+ if (ret){
+ printk(BIOS_ERR, init_default_cbfs_media returned %d: HALT\n,
+ ret);
+ while (1);
+ }
+
+ struct cbfs_stage *stage = (struct cbfs_stage *)
+ cbfs_get_file_content(cbfs, fallback/coreboot_ram,
+ CBFS_TYPE_STAGE);
+ printk(BIOS_ERR, Stage: %p\n, stage);
+ printk(BIOS_ERR, loading stage %s @ 0x%x (0x%x bytes),entry @ 0x%p\n,
+ ram stage,
+ (uint32_t) stage-load, stage-memlen,
+ (void *)(u32)stage-entry);
+
+#if 0
+ /* for reference and testing ... we should be able to remove soon */
+// c = (void *)(u32)(stage-load + stage-len);
+ c = (void *)(u32)(stage-load);
+ printk(BIOS_ERR, memzero 0x%x words starting at %p\n,
+ (stage-memlen /*- stage-len*/)/4, c);
+ for(i = 0; i (stage-memlen /*- stage-len*/)/4; i++){
+ printk(BIOS_INFO, %p, , c[i]);
+ c[i] = 0;
+ }
+#endif
+
+ void *entry = cbfs_load_stage(cbfs, fallback/coreboot_ram);
+ printk(BIOS_INFO, entry is %p\n, entry);
-// *pshold = ~0x100; /* shut down */
- mmu_setup(CONFIG_SYS_SDRAM_BASE, CONFIG_DRAM_SIZE_MB * 1024);
+ printk(BIOS_INFO, sayonara, romstage!\n);
+ stage_exit((unsigned long)entry);
}
--
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[coreboot] Patch merged into coreboot/master: 50c0a50 armv7: unify stage hand-off routines
the following patch was just integrated into master: commit 50c0a50ac6a3fa54ed1286e8b76f933701b6d053 Author: David Hendricks dhend...@chromium.org Date: Thu Jan 31 17:05:50 2013 -0800 armv7: unify stage hand-off routines This replaces the current stage-specific exit/entry functions with generic versions. Now all stages compile with stage_entry(), which is placed at .text.stage_entry.armv7, and stage_exit(). Snow's ramstage files are also updated to avoid build breakage. Change-Id: I953a2c4b8121bd4b66c3362557997a9ca3aa53b0 Signed-off-by: David Hendricks dhend...@chromium.org Reviewed-on: http://review.coreboot.org/2254 Reviewed-by: Ronald G. Minnich rminn...@gmail.com Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Feb 1 03:17:48 2013, giving +1 Reviewed-By: Ronald G. Minnich rminn...@gmail.com at Fri Feb 1 03:01:42 2013, giving +2 See http://review.coreboot.org/2254 for details. -gerrit -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: 1ead10d lib: Prevent unaligned memory access in LZMA decode library.
Ronald G. Minnich (rminn...@gmail.com) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2246
-gerrit
commit 1ead10d4f4718bede6279db834eb3d34960749e2
Author: Hung-Te Lin hun...@chromium.org
Date: Thu Jan 31 12:14:46 2013 +0800
lib: Prevent unaligned memory access in LZMA decode library.
LZMA decode library used to retrieve output size by:
outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
'src' is aligned but LZMA_PROPERTIES_SIZE may refer to an unaligned address
like
src+5, and using that as integer pointer may fail on platforms like ARM.
To fix this, use memcpy to copy into aligned variable outSize.
Change-Id: If678e735cb270c3e5e29f36f1fad318096bf7d59
Signed-off-by: Hung-Te Lin hun...@chromium.org
---
src/lib/lzma.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/lib/lzma.c b/src/lib/lzma.c
index f0b88c1..a2d91d1 100644
--- a/src/lib/lzma.c
+++ b/src/lib/lzma.c
@@ -31,7 +31,8 @@ unsigned long ulzma(unsigned char * src, unsigned char * dst)
unsigned char scratchpad[15980];
memcpy(properties, src, LZMA_PROPERTIES_SIZE);
- outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
+ /* Do memcpy to prevent unaligned memory access. */
+ memcpy(outSize, src + LZMA_PROPERTIES_SIZE, sizeof(outSize));
if (LzmaDecodeProperties(state.Properties, properties,
LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) {
printk(BIOS_WARNING, lzma: Incorrect stream properties.\n);
return 0;
--
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Re: [coreboot] Different Google copyright notices: »The Chromium OS Authors. ?«
On Fri, Feb 1, 2013 at 6:36 AM, Paul Menzel paulepan...@users.sourceforge.net wrote: Am Mittwoch, den 30.01.2013, 01:06 +0100 schrieb Peter Stuge: ron minnich wrote: In the community we can of course not know what is correct when, ah yes well I do kind of wonder if *I* know what I'm doing half the time :-) I guess the concern was that perhaps there was a single correct notice to be used, and that some of you guys made a mistake somewhere. I don't expect that you make such mistakes, but I guess that's what Paul meant. Well, thanks to Hung-Te’s clarifying answer, at least the inconsistent spelling of »The Chromium*OS Authors.« with or without space shows that a mistake indeed was made while copying. Oops, I won't call that a mistake by copy. Just like Ron said, copyright and policy changes. I only verified latest one is 'Chromium OS Authors' for chromium.org. Maybe it was without space, lower case c, ... etc for some time (or maybe there was not a standard long time ago). That's why I only changed my new changes on gerrit (i.e., those not merged yet) instead of changing all files related to chromium.org, because I can only make sure those were made by taking copyright string from old files. Also I assume, that the inconsistency in adding »All rights reserved.« or having the copyright sign spelled with a capitalized »(C)« or not »(c)« is a mistake (and not a policy decision). So to keep the differences between files small, it would be awesome if some Google/Chromium OS developer could unify that and set up some pre-commit hook checking that with each commit. For same reason, for new commits we can be more careful to use latest correct copyright string, but it seems no harm to keep old files as-is. What do you think? Regards, Hung-Te -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch merged into coreboot/master: 7fb692b Fam15tn: Move SPD read from mainboards into wrapper
the following patch was just integrated into master: commit 7fb692bd867b271834be797029a6b4f72e4601bd Author: Martin Roth martin.r...@se-eng.com Date: Sun Jan 20 10:38:58 2013 -0700 Fam15tn: Move SPD read from mainboards into wrapper Continuing with the mainboard cleanup for F15tn, move the functions to read the SPD from the mainboards for Thatcher and Parmer into the wrapper for the northbridge/amd/agesa/family15tn. Move the SPD address customization for the mainboard into the devicetree.cb file. Unrelated side note - Porting.h has an un-closed #pragma pack(1) that can cause confusing side-effects. AGESA's structures all use this, but coreboot's don't. Be sure to include the coreboot .h files BEFORE Porting.h is included, not after. This fix has been tested. Change-Id: I89cdd225be61f60c6b8e7020e6f8b879983bbd96 Signed-off-by: Martin Roth martin.r...@se-eng.com Reviewed-on: http://review.coreboot.org/2190 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones marcj...@gmail.com Reviewed-by: Paul Menzel paulepan...@users.sourceforge.net Reviewed-by: Siyuan Wang wangsiyuanb...@gmail.com Build-Tested: build bot (Jenkins) at Thu Jan 31 19:59:42 2013, giving +1 Reviewed-By: Marc Jones marcj...@gmail.com at Thu Jan 31 23:02:10 2013, giving +2 See http://review.coreboot.org/2190 for details. -gerrit -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] New patch to review for coreboot: 32e20ad clean-up for arch/armv7/Makefile.inc
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2257 -gerrit commit 32e20ad580f6f9cc744380910a0dc49cd68cae9a Author: David Hendricks dhend...@chromium.org Date: Thu Jan 31 17:49:22 2013 -0800 clean-up for arch/armv7/Makefile.inc This removes a few lines which are obsolete or unneeded. We may want to do something with SMP eventually (can we use it for decompression?) but for now we'll assume non-bootstrap cores are idle until the OS does something with them. Change-Id: Iff6b196e008e803bcfd00e5de07cf471bd2357ea Signed-off-by: David Hendricks dhend...@chromium.org --- src/arch/armv7/Makefile.inc | 35 --- 1 file changed, 35 deletions(-) diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index 78fa671..e55f477 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -25,7 +25,6 @@ # Take care of subdirectories subdirs-y += boot/ subdirs-y += lib/ -# subdirs-y += smp/ # Build the final rom image @@ -60,10 +59,6 @@ endif $(obj)/coreboot.rom: $(obj)/coreboot.pre $(objcbfs)/coreboot_ram.elf $(CBFSTOOL) $(call strip_quotes,$(COREBOOT_ROM_DEPENDENCIES)) @printf CBFS $(subst $(obj)/,,$(@))\n cp $(obj)/coreboot.pre $@.tmp - if [ -f $(objcbfs)/coreboot_ap.elf ]; \ - then \ - $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ap.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ap -c $(CBFS_COMPRESS_FLAG) ; \ - fi $(CBFSTOOL) $@.tmp add-stage -f $(objcbfs)/coreboot_ram.elf -n $(CONFIG_CBFS_PREFIX)/coreboot_ram -c $(CBFS_COMPRESS_FLAG) ifeq ($(CONFIG_PAYLOAD_NONE),y) @printf PAYLOADnone (as specified by user)\n @@ -131,20 +126,6 @@ else $(CC) $(CFLAGS) -nostdlib -r -o $@ -Wl,--start-group $(stages_o) $(ramstage-objs) $(LIBGCC_FILE_NAME) -Wl,--end-group endif - -# Ramstage for AP CPU (AMD K8, obsolete?) - -#$(objcbfs)/coreboot_ap.debug: $(objgenerated)/coreboot_ap.o $(src)/arch/armv7/init/ldscript_apc.lb -# @printf CC $(subst $(obj)/,,$(@))\n -# $(CC) -nostdlib -nostartfiles -static -o $@ -L$(obj) -T $(src)/arch/armv7/init/ldscript_apc.lb $ - -#$(objgenerated)/coreboot_ap.o: $(src)/mainboard/$(MAINBOARDDIR)/ap_romstage.c $(OPTION_TABLE_H) -# @printf CC $(subst $(obj)/,,$(@))\n -# $(CC) -MMD $(CFLAGS) -I$(src) -D__PRE_RAM__ -I. -I$(obj) -c $ -o $@ - - -# done - CFLAGS += \ -ffixed-r8\ -march=armv7-a\ @@ -153,10 +134,6 @@ CFLAGS += \ -mthumb\ -mthumb-interwork -# For various headers imported from Linux -CFLAGS += -D__LINUX_ARM_ARCH__=7 - -#crt0s = $(src)/arch/armv7/bootblock.inc ldscripts = ldscripts += $(src)/arch/armv7/romstage.ld @@ -173,19 +150,10 @@ ifeq ($(CONFIG_LLSHELL),y) crt0s += $(src)/arch/armv7/llshell/llshell.inc endif -# FIXME: do we need romstage.inc? Maybe just get rid of this entirely. -#crt0s += $(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc - $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc: $(src)/mainboard/$(MAINBOARDDIR)/romstage.c $(OPTION_TABLE_H) $(obj)/build.h $(obj)/config.h @printf CC romstage.inc\n $(CC) -MMD $(CFLAGS) -D__PRE_RAM__ -I$(src) -I. -I$(obj) -c -S $ -o $@ -#$(obj)/mainboard/$(MAINBOARDDIR)/romstage.inc: $(obj)/mainboard/$(MAINBOARDDIR)/romstage.pre.inc -# @printf POST romstage.inc\n -# sed -e 's/\.rodata/.rom.data/g' -e 's/\^\.text/.section .rom.text/g' \ -# -e 's/\^\.section \.text/.section .rom.text/g' $^ $@.tmp -# mv $@.tmp $@ - # Things that appear in every board romstage-srcs += $(objgenerated)/crt0.s ramstage-srcs += src/mainboard/$(MAINBOARDDIR)/mainboard.c @@ -251,8 +219,6 @@ $(objgenerated)/bootblock.o: $(objgenerated)/bootblock.s @printf CC $(subst $(obj)/,,$(@))\n $(CC) -Wa,-acdlns -c -o $@ $ $(basename $@).disasm -#BOOTBLOCK_OBJS = $(objgenerated)/bootblock.o $(bootblock_exit_o) - $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(obj)/build.h @printf CC $(subst $(obj)/,,$(@))\n $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $ -o $@ @@ -274,7 +240,6 @@ endif # Build the romstage -# FIXME(dhendrix): added debug printfs $(objcbfs)/romstage_null.debug: $$(romstage-objs) $(stages_o) $(objgenerated)/romstage_null.ld @printf LINK $(subst $(obj)/,,$(@))\n ifeq
[coreboot] Patch set updated for coreboot: 120bd66 lib: Prevent unaligned memory access and fix endianess in LZMA decode library.
Hung-Te Lin (hun...@chromium.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2246
-gerrit
commit 120bd66b5ffbc7ca52a7255191d1c3025c6a2803
Author: Hung-Te Lin hun...@chromium.org
Date: Thu Jan 31 12:14:46 2013 +0800
lib: Prevent unaligned memory access and fix endianess in LZMA decode
library.
LZMA decode library used to retrieve output size by:
outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
'src' is aligned but LZMA_PROPERTIES_SIZE may refer to an unaligned address
like
src+5, and using that as integer pointer may fail on platforms like ARM.
Also
this will fail on systems using big-endian (outSize was encoded in
little-endian).
To fix this, reconstruct outSize in little-endian way.
Change-Id: If678e735cb270c3e5e29f36f1fad318096bf7d59
Signed-off-by: Hung-Te Lin hun...@chromium.org
---
src/lib/lzma.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/lib/lzma.c b/src/lib/lzma.c
index f0b88c1..7a62b84 100644
--- a/src/lib/lzma.c
+++ b/src/lib/lzma.c
@@ -29,9 +29,15 @@ unsigned long ulzma(unsigned char * src, unsigned char * dst)
#endif
/* in pre-ram, it must go on the stack */
unsigned char scratchpad[15980];
+ unsigned char *cp;
memcpy(properties, src, LZMA_PROPERTIES_SIZE);
- outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
+ /* The outSize in LZMA stream is a 64bit integer stored in little-endian
+* (ref: lzma.cc@LZMACompress: put_64). To prevent accessing by
+* unaligned memory access and to load endianess correctly, read each
+* byte and re-costruct. */
+ cp = src + LZMA_PROPERTIES_SIZE;
+ outSize = cp[3] 24 | cp[2] 16 | cp[1] 8 | cp[0];
if (LzmaDecodeProperties(state.Properties, properties,
LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) {
printk(BIOS_WARNING, lzma: Incorrect stream properties.\n);
return 0;
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: 3a950ab lib: Prevent unaligned memory access and fix endianess in LZMA decode library.
Hung-Te Lin (hun...@chromium.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2246
-gerrit
commit 3a950ab119a28d545ff4fd45805f9e67ebe8e3a8
Author: Hung-Te Lin hun...@chromium.org
Date: Thu Jan 31 12:14:46 2013 +0800
lib: Prevent unaligned memory access and fix endianess in LZMA decode
library.
LZMA decode library used to retrieve output size by:
outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
'src' is aligned but LZMA_PROPERTIES_SIZE may refer to an unaligned address
like
src+5, and using that as integer pointer may fail on platforms like ARM.
Also
this will fail on systems using big-endian (outSize was encoded in
little-endian).
To fix this, reconstruct outSize in little-endian way.
Change-Id: If678e735cb270c3e5e29f36f1fad318096bf7d59
Signed-off-by: Hung-Te Lin hun...@chromium.org
---
src/lib/lzma.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/lib/lzma.c b/src/lib/lzma.c
index f0b88c1..cd60b3f 100644
--- a/src/lib/lzma.c
+++ b/src/lib/lzma.c
@@ -29,9 +29,15 @@ unsigned long ulzma(unsigned char * src, unsigned char * dst)
#endif
/* in pre-ram, it must go on the stack */
unsigned char scratchpad[15980];
+ unsigned char *cp;
memcpy(properties, src, LZMA_PROPERTIES_SIZE);
- outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE);
+ /* The outSize in LZMA stream is a 64bit integer stored in little-endian
+* (ref: lzma.cc@LZMACompress: put_64). To prevent accessing by
+* unaligned memory address and to load in correct endianess, read each
+* byte and re-costruct. */
+ cp = src + LZMA_PROPERTIES_SIZE;
+ outSize = cp[3] 24 | cp[2] 16 | cp[1] 8 | cp[0];
if (LzmaDecodeProperties(state.Properties, properties,
LZMA_PROPERTIES_SIZE) != LZMA_RESULT_OK) {
printk(BIOS_WARNING, lzma: Incorrect stream properties.\n);
return 0;
--
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[coreboot] Patch merged into coreboot/master: 4d87d4e cbfstool: Add -v (verbose) output.
the following patch was just integrated into master: commit 4d87d4e09b38d152425f060f088f3a44b7dacfcb Author: Hung-Te Lin hun...@chromium.org Date: Mon Jan 28 14:39:43 2013 +0800 cbfstool: Add -v (verbose) output. Add -v (verbose) to every command, and allow printing debug messages. Revise logging and debugging functions (fprintf(stderr,...), dprintf...) and verbose message printing with following macros: ERROR(xxx): E: xxx WARN(xxx) W: xxx LOG(xxx)xxx INFO(...) INFO: xxx (only when runs with -v ) DEBUG(...) DEBUG: xxx (only when runs with more than one -v) Example: cbfstool coreboot.rom print -v cbfstool coreboot.rom add -f file -n file -t raw -v -v Normal output (especially for parsing) should use printf, not any of these macros (see usage() and cbfs_locate(), cbfs_print_directory() for example). Change-Id: I167617da1a6eea2b07075b0eb38e3c9d85ea75dc Signed-off-by: Hung-Te Lin hun...@chromium.org Reviewed-on: http://review.coreboot.org/2196 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks dhend...@chromium.org Build-Tested: build bot (Jenkins) at Wed Jan 30 03:50:11 2013, giving +1 Reviewed-By: David Hendricks dhend...@chromium.org at Fri Feb 1 05:50:32 2013, giving +2 See http://review.coreboot.org/2196 for details. -gerrit -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: 0d880b1 cbfstool: move flat-binary parsing to cbfs-mkpayload.
David Hendricks (dhend...@chromium.org) just uploaded a new patch set to
gerrit, which you can find at http://review.coreboot.org/2197
-gerrit
commit 0d880b12ba4b3f486986f9890d145d75a2afc2e6
Author: Hung-Te Lin hun...@chromium.org
Date: Mon Jan 28 15:04:30 2013 +0800
cbfstool: move flat-binary parsing to cbfs-mkpayload.
The ELF parsing and payload building in add-flat-binary command should be
isolated just like mkpayload and mkstage.
Since the add-flat-binary command creates a payload in the end , move
payload
processing to cbfs-mkpayload.c.
To test:
cbfstool coreboot.rom add-flat-binary -f u-boot.bin -n fallback/payload \
-l 0x10 -e 0x100020
To verify, get output from cbfstool coreboot.rom print -v:
fallback/payload 0x73ccc0 payload 124920
INFO: code (no compression, offset: 0x38, load: 0x111,
length:..)
Change-Id: Ia7bd2e6160507c0a1e8e20bc1d08397ce9826e0d
Signed-off-by: Hung-Te Lin hun...@chromium.org
---
util/cbfstool/cbfs-mkpayload.c | 53 +++
util/cbfstool/cbfstool.c | 57 ++
util/cbfstool/common.h | 5
3 files changed, 71 insertions(+), 44 deletions(-)
diff --git a/util/cbfstool/cbfs-mkpayload.c b/util/cbfstool/cbfs-mkpayload.c
index da04a75..060e9ee 100644
--- a/util/cbfstool/cbfs-mkpayload.c
+++ b/util/cbfstool/cbfs-mkpayload.c
@@ -202,3 +202,56 @@ int parse_elf_to_payload(unsigned char *input, unsigned
char **output,
err:
return -1;
}
+
+int parse_flat_binary_to_payload(unsigned char *input, unsigned char **output,
+int32_t input_size,
+uint32_t loadaddress,
+uint32_t entrypoint,
+comp_algo algo)
+{
+ comp_func_ptr compress;
+ unsigned char *payload;
+ struct cbfs_payload_segment *segs;
+ int doffset, len = 0;
+
+ compress = compression_function(algo);
+ if (!compress)
+ return -1;
+
+ DEBUG(start: parse_flat_binary_to_payload\n);
+
+ /* FIXME compressed file size might be bigger than original file and
+* causing buffer overflow. */
+ payload = calloc((2 * sizeof(struct cbfs_payload_segment)) +
input_size, 1);
+ if (payload == NULL) {
+ ERROR(Could not allocate memory.\n);
+ return -1;
+ }
+
+ segs = (struct cbfs_payload_segment *)payload;
+ doffset = (2 * sizeof(*segs));
+
+ /* Prepare code segment */
+ segs[0].type = PAYLOAD_SEGMENT_CODE;
+ segs[0].load_addr = htonll(loadaddress);
+ segs[0].mem_len = htonl(input_size);
+ segs[0].offset = htonl(doffset);
+
+ compress((char*)input, input_size, (char*)payload + doffset, len);
+ segs[0].compression = htonl(algo);
+ segs[0].len = htonl(len);
+
+ if ((unsigned int)len = input_size) {
+ WARN(Compressing data would make it bigger - disabled.\n);
+ segs[0].compression = 0;
+ segs[0].len = htonl(input_size);
+ memcpy(payload + doffset, input, input_size);
+ }
+
+ /* prepare entry point segment */
+ segs[1].type = PAYLOAD_SEGMENT_ENTRY;
+ segs[1].load_addr = htonll(entrypoint);
+ *output = payload;
+
+ return doffset + ntohl(segs[0].len);
+}
diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c
index 2857264..1ad270b 100644
--- a/util/cbfstool/cbfstool.c
+++ b/util/cbfstool/cbfstool.c
@@ -234,12 +234,8 @@ static int cbfs_add_stage(void)
static int cbfs_add_flat_binary(void)
{
uint32_t filesize = 0;
- uint32_t final_size;
void *rom, *filedata, *cbfsfile;
unsigned char *payload;
- comp_func_ptr compress;
- struct cbfs_payload_segment *segs;
- int doffset, len = 0;
if (!param.filename) {
ERROR(You need to specify -f/--filename.\n);
@@ -263,10 +259,6 @@ static int cbfs_add_flat_binary(void)
return 1;
}
- compress = compression_function(param.algo);
- if (!compress)
- return 1;
-
rom = loadrom(param.cbfs_name);
if (rom == NULL) {
ERROR(Could not load ROM image '%s'.\n,
@@ -282,47 +274,24 @@ static int cbfs_add_flat_binary(void)
return 1;
}
- /* FIXME compressed file size might be bigger than original file */
- payload = calloc((2 * sizeof(struct cbfs_payload_segment)) + filesize,
1);
- if (payload == NULL) {
- ERROR(Could not allocate memory.\n);
- free(filedata);
+ filesize = parse_flat_binary_to_payload(filedata, payload,
+ filesize,
+ param.loadaddress,
+
[coreboot] Patch merged into coreboot/master: 05dccae cbfstool: move flat-binary parsing to cbfs-mkpayload.
the following patch was just integrated into master: commit 05dccae75df4ed0c6a75867a89cf1a4055507e28 Author: Hung-Te Lin hun...@chromium.org Date: Mon Jan 28 15:04:30 2013 +0800 cbfstool: move flat-binary parsing to cbfs-mkpayload. The ELF parsing and payload building in add-flat-binary command should be isolated just like mkpayload and mkstage. Since the add-flat-binary command creates a payload in the end , move payload processing to cbfs-mkpayload.c. To test: cbfstool coreboot.rom add-flat-binary -f u-boot.bin -n fallback/payload \ -l 0x10 -e 0x100020 To verify, get output from cbfstool coreboot.rom print -v: fallback/payload 0x73ccc0 payload 124920 INFO: code (no compression, offset: 0x38, load: 0x111, length:..) Change-Id: Ia7bd2e6160507c0a1e8e20bc1d08397ce9826e0d Signed-off-by: Hung-Te Lin hun...@chromium.org Reviewed-on: http://review.coreboot.org/2197 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks dhend...@chromium.org Build-Tested: build bot (Jenkins) at Fri Feb 1 06:05:28 2013, giving +1 Reviewed-By: David Hendricks dhend...@chromium.org at Fri Feb 1 06:06:41 2013, giving +2 See http://review.coreboot.org/2197 for details. -gerrit -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch merged into coreboot/master: d51557a lib: Prevent unaligned memory access and fix endianess in LZMA decode library.
the following patch was just integrated into master: commit d51557ade2a9f29cbb4e0f38d5a4920b42486168 Author: Hung-Te Lin hun...@chromium.org Date: Thu Jan 31 12:14:46 2013 +0800 lib: Prevent unaligned memory access and fix endianess in LZMA decode library. LZMA decode library used to retrieve output size by: outSize = *(UInt32 *)(src + LZMA_PROPERTIES_SIZE); 'src' is aligned but LZMA_PROPERTIES_SIZE may refer to an unaligned address like src+5, and using that as integer pointer may fail on platforms like ARM. Also this will fail on systems using big-endian (outSize was encoded in little-endian). To fix this, reconstruct outSize in little-endian way. Change-Id: If678e735cb270c3e5e29f36f1fad318096bf7d59 Signed-off-by: Hung-Te Lin hun...@chromium.org Reviewed-on: http://review.coreboot.org/2246 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich rminn...@gmail.com Build-Tested: build bot (Jenkins) at Fri Feb 1 05:57:55 2013, giving +1 Reviewed-By: Ronald G. Minnich rminn...@gmail.com at Fri Feb 1 06:15:49 2013, giving +2 See http://review.coreboot.org/2246 for details. -gerrit -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch merged into coreboot/master: ea60473 exynos5250: #define the dram controller interleaving size
the following patch was just integrated into master: commit ea60473b9dea41571e1eac9afe93f712d66e557a Author: David Hendricks dhend...@chromium.org Date: Thu Jan 31 17:22:50 2013 -0800 exynos5250: #define the dram controller interleaving size Change-Id: Iab184aa85be68b6ca5107d278d2fe821e5b2e611 Signed-off-by: David Hendricks dhend...@chromium.org Reviewed-on: http://review.coreboot.org/2255 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich rminn...@gmail.com Build-Tested: build bot (Jenkins) at Fri Feb 1 03:10:28 2013, giving +1 Reviewed-By: Ronald G. Minnich rminn...@gmail.com at Fri Feb 1 06:16:23 2013, giving +2 See http://review.coreboot.org/2255 for details. -gerrit -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch merged into coreboot/master: c9f26a1 exynos5250: hard-code array index for memory timings
the following patch was just integrated into master: commit c9f26a169d854cf682f3d9d55124dce70b84620f Author: David Hendricks dhend...@chromium.org Date: Thu Jan 31 17:25:16 2013 -0800 exynos5250: hard-code array index for memory timings Discovering memory timings is a bit complicated due to the need to obtain and decode board config. To make things worse, the imported code makes a mess of dependencies. Hard-code the memory timings for now to get us further along (the instability won't really matter until we're loading depthcharge anyway). Change-Id: I1f341ad597db0c31ed4ae6bc703fc22b6596a803 Signed-off-by: David Hendricks dhend...@chromium.org Reviewed-on: http://review.coreboot.org/2256 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich rminn...@gmail.com Build-Tested: build bot (Jenkins) at Fri Feb 1 03:39:42 2013, giving +1 Reviewed-By: Ronald G. Minnich rminn...@gmail.com at Fri Feb 1 06:16:44 2013, giving +2 See http://review.coreboot.org/2256 for details. -gerrit -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] Different Google copyright notices: »The Chromium OS Authors. ?«
On Thu, Jan 31, 2013 at 6:09 PM, Hung-Te Lin hun...@chromium.org wrote: For same reason, for new commits we can be more careful to use latest correct copyright string, but it seems no harm to keep old files as-is. What do you think? don't change old strings. thanks ron -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch merged into coreboot/master: 0a5bc7f snow: make romstage init DRAM controller and call ramstage
the following patch was just integrated into master: commit 0a5bc7fb474a15b77747b2007340dd7589413d8d Author: Ronald G. Minnich rminn...@gmail.com Date: Wed Jan 30 15:55:36 2013 -0800 snow: make romstage init DRAM controller and call ramstage This is a first cut at a romstage. It sets up memory, although that needs some work; and finds and loads a ramstage. Change-Id: I02a0eb48828500bf83c3c57d4bacb396e58bf9a5 Signed-off-by: Ronald G. Minnich rminn...@gmail.com Signed-off-by: David Hendricks dhend...@chromium.org Reviewed-on: http://review.coreboot.org/2245 Tested-by: build bot (Jenkins) Build-Tested: build bot (Jenkins) at Fri Feb 1 03:47:25 2013, giving +1 Reviewed-By: Ronald G. Minnich rminn...@gmail.com at Fri Feb 1 06:17:40 2013, giving +2 See http://review.coreboot.org/2245 for details. -gerrit -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch merged into coreboot/master: d723c5b clean-up for arch/armv7/Makefile.inc
the following patch was just integrated into master: commit d723c5b554786794217a92acb4ce0096bf924da8 Author: David Hendricks dhend...@chromium.org Date: Thu Jan 31 17:49:22 2013 -0800 clean-up for arch/armv7/Makefile.inc This removes a few lines which are obsolete or unneeded. We may want to do something with SMP eventually (can we use it for decompression?) but for now we'll assume non-bootstrap cores are idle until the OS does something with them. Change-Id: Iff6b196e008e803bcfd00e5de07cf471bd2357ea Signed-off-by: David Hendricks dhend...@chromium.org Reviewed-on: http://review.coreboot.org/2257 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich rminn...@gmail.com Build-Tested: build bot (Jenkins) at Fri Feb 1 05:15:37 2013, giving +1 Reviewed-By: Ronald G. Minnich rminn...@gmail.com at Fri Feb 1 06:19:04 2013, giving +2 See http://review.coreboot.org/2257 for details. -gerrit -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch merged into coreboot/master: 332795c cbfstool: Make endian detection functions to work without prior setup.
the following patch was just integrated into master: commit 332795cc5951c6d65badd2bbf3c79f6b63dbdbc2 Author: Hung-Te Lin hun...@chromium.org Date: Mon Jan 28 15:53:34 2013 +0800 cbfstool: Make endian detection functions to work without prior setup. The 'host_bigendian' variable (and functions relying on it like ntohl/htonl) requires host detection by calling static which_endian() first -- which may be easily forgotten by developers. It's now a public function in common.c and doesn't need initialization anymore. Change-Id: I13dabd1ad15d2d6657137d29138e0878040cb205 Signed-off-by: Hung-Te Lin hun...@chromium.org Reviewed-on: http://review.coreboot.org/2199 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel paulepan...@users.sourceforge.net Build-Tested: build bot (Jenkins) at Wed Jan 30 04:04:05 2013, giving +1 Reviewed-By: Paul Menzel paulepan...@users.sourceforge.net at Wed Jan 30 11:07:22 2013, giving +2 See http://review.coreboot.org/2199 for details. -gerrit -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: fd30d9a libpayload: New CBFS to support multiple firmware media sources.
Hung-Te Lin (hun...@chromium.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2191
-gerrit
commit fd30d9a2c67f5a126580564d6b7e5714c8a8f2c8
Author: Hung-Te Lin hun...@chromium.org
Date: Fri Jan 25 12:42:40 2013 +0800
libpayload: New CBFS to support multiple firmware media sources.
Upgrade CBFS in libpayload to use new media-based implementation from
coreboot
( http://review.coreboot.org/#/c/2182/ ).
Old CBFS functions (cbfs_find, cbfs_find_file, get_cbfs_header) are still
supported, although the recommended way is to use new CBFS API.
To migrate your existing x86 payload source:
- Change cbfs_find to cbfs_get_file
- Change cbfs_find_file to cbfs_get_file_content
- Prefix every CBFS call with a CBFS_DEFAULT_MEDIA argument.
Ex, char *jpeg_data = cbfs_find_file(splash.jpg, CBFS_TYPE_BOOTSPLASH);
= char *jpeg_data = cbfs_get_file_content(
CBFS_DEFAULT_MEDIA, splash.jpg, CBFS_TYPE_BOOTSPLASH);
The legacy setup_cbfs_from_{ram,flash} is also supported, although the
better
equivalent is to make a new media instance:
struct cbfs_media ram_media;
init_cbfs_ram_media(ram_media, start, size);
char *data = cbfs_get_file_content(ram_media, myfile, my_type);
Verified by being successfully linked with filo.
Change-Id: If797bc7e3ba975d7e3be905c59424f7a93b8ce11
Signed-off-by: Hung-Te Lin hun...@chromium.org
---
payloads/libpayload/arch/x86/Makefile.inc | 2 +
payloads/libpayload/arch/x86/rom_media.c | 111 ++
payloads/libpayload/include/cbfs.h| 102 +++--
payloads/libpayload/include/cbfs_core.h | 74 +++---
payloads/libpayload/include/stdint.h | 1 +
payloads/libpayload/libcbfs/Makefile.inc | 1 +
payloads/libpayload/libcbfs/cbfs.c| 232 --
payloads/libpayload/libcbfs/cbfs_core.c | 198 ++---
payloads/libpayload/libcbfs/ram_media.c | 114 +++
9 files changed, 676 insertions(+), 159 deletions(-)
diff --git a/payloads/libpayload/arch/x86/Makefile.inc
b/payloads/libpayload/arch/x86/Makefile.inc
index 8f68b07..0977eb1 100644
--- a/payloads/libpayload/arch/x86/Makefile.inc
+++ b/payloads/libpayload/arch/x86/Makefile.inc
@@ -33,5 +33,7 @@ libc-y += timer.c coreboot.c util.S
libc-y += exec.S virtual.c
libc-y += string.c
+libcbfs-$(CONFIG_CBFS) += rom_media.c
+
# Multiboot support is configurable
libc-$(CONFIG_MULTIBOOT) += multiboot.c
diff --git a/payloads/libpayload/arch/x86/rom_media.c
b/payloads/libpayload/arch/x86/rom_media.c
new file mode 100644
index 000..e9fa94c
--- /dev/null
+++ b/payloads/libpayload/arch/x86/rom_media.c
@@ -0,0 +1,111 @@
+/*
+ * This file is part of the libpayload project.
+ *
+ * Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ *derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ */
+#define LIBPAYLOAD
+
+#include cbfs.h
+#include string.h
+
+#ifdef LIBPAYLOAD
+# define printk(x...)
+# define init_default_cbfs_media libpayload_init_default_cbfs_media
+ extern int libpayload_init_default_cbfs_media(struct cbfs_media *media);
+#else
+# include console/console.h
+#endif
+
+// Implementation of memory-mapped ROM media source on X86.
+
+static int x86_rom_open(struct cbfs_media *media) {
+ return 0;
+}
+
+static void *x86_rom_map(struct cbfs_media *media, size_t offset, size_t
count) {
+ void *ptr;
+ // Some address (ex, pointer to master header) may be
[coreboot] Patch set updated for coreboot: c407cfd armv7: Add 'bootblock' build class.
Hung-Te Lin (hun...@chromium.org) just uploaded a new patch set to gerrit, which you can find at http://review.coreboot.org/2252 -gerrit commit c407cfd7f41eb8467e85edc07609793762c7fd57 Author: Hung-Te Lin hun...@chromium.org Date: Fri Feb 1 01:09:24 2013 +0800 armv7: Add 'bootblock' build class. For ARM platform, the bootblock may need more C source files to initialize UART / SPI for loading romstage. To preventing making complex and implicit dependency by using #include inside bootblock.c, we should add a new build class bootblock. Also #ifdef __BOOT_BLOCK__ can be used to detect if the source is being compiled for boot block. For x86, the bootblock is limited to fewer assembly files so it's not using this class. (Some files shared by x86 and arm in top level or lib are also changed but nothing should be changed in x86 build process.) Change-Id: Ia81bccc366d2082397d133d9245f7ecb33b8bc8b Signed-off-by: Hung-Te Lin hun...@chromium.org --- Makefile.inc| 10 - src/arch/armv7/Makefile.inc | 9 +++-- src/arch/armv7/bootblock_simple.c | 2 +- src/arch/armv7/include/arch/cbfs.h | 60 - src/arch/armv7/lib/Makefile.inc | 1 + src/cpu/samsung/exynos5-common/Makefile.inc | 1 + src/lib/Makefile.inc| 10 + src/lib/cbfs.c | 2 + src/mainboard/google/snow/bootblock.c | 3 -- 9 files changed, 30 insertions(+), 68 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 3731797..0b473e4 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -58,7 +58,7 @@ subdirs-y += site-local ### # Add source classes and their build options -classes-y := ramstage romstage smm cpu_microcode +classes-y := ramstage romstage bootblock smm cpu_microcode ### # Helper functions for ramstage postprocess @@ -111,6 +111,9 @@ $(error Your current configuration requires binary-only components, but you did endif endif +bootblock-c-ccopts:=-D__BOOT_BLOCK__ +bootblock-S-ccopts:=-D__BOOT_BLOCK__ + smm-c-ccopts:=-D__SMM__ smm-S-ccopts:=-D__SMM__ @@ -121,6 +124,7 @@ endif ramstage-c-deps:=$$(OPTION_TABLE_H) romstage-c-deps:=$$(OPTION_TABLE_H) +bootblock-c-deps:=$$(OPTION_TABLE_H) ### # Add handler to compile ACPI's ASL @@ -286,6 +290,10 @@ $(obj)/%.romstage.o $(abspath $(obj))/%.romstage.o: $(obj)/%.c $(obj)/config.h $ @printf CC $(subst $(obj)/,,$(@))\n $(CC) -MMD -D__PRE_RAM__ $(CFLAGS) -c -o $@ $ +$(obj)/%.bootblock.o $(abspath $(obj))/%.bootblock.o: $(obj)/%.c $(obj)/config.h $(OPTION_TABLE_H) + @printf CC $(subst $(obj)/,,$(@))\n + $(CC) -MMD -D__BOOT_BLOCK__ $(CFLAGS) -c -o $@ $ + ### # Clean up rules clean-abuild: diff --git a/src/arch/armv7/Makefile.inc b/src/arch/armv7/Makefile.inc index e55f477..715ce1e 100644 --- a/src/arch/armv7/Makefile.inc +++ b/src/arch/armv7/Makefile.inc @@ -207,6 +207,9 @@ bootblock_inc += $(src)/arch/armv7/lib/id.inc bootblock_inc += $(chipset_bootblock_inc) bootblock_inc += $(objgenerated)/bootblock.inc +bootblock_custom = $(src)/$(call strip_quotes,$(CONFIG_BOOTBLOCK_CPU_INIT)) +bootblock_custom += $(src)/$(call strip_quotes,$(CONFIG_BOOTBLOCK_MAINBOARD_INIT)) + $(objgenerated)/bootblock.ld: $$(bootblock_lds) $(obj)/ldoptions @printf GEN$(subst $(obj)/,,$(@))\n printf '$(foreach ldscript,ldoptions $(bootblock_lds),INCLUDE $(ldscript)\n)' $@ @@ -223,18 +226,18 @@ $(objgenerated)/bootblock.s: $(objgenerated)/bootblock_inc.S $(obj)/config.h $(o @printf CC $(subst $(obj)/,,$(@))\n $(CC) -MMD -x assembler-with-cpp -E -I$(src)/include -I$(src)/arch/armv7/include -I$(obj) -include $(obj)/build.h -include $(obj)/config.h -I. -I$(src) $ -o $@ -$(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ,,$(CONFIG_BOOTBLOCK_SOURCE)) $(OPTION_TABLE_H) +$(objgenerated)/bootblock.inc: $(src)/arch/armv7/$(subst ,,$(CONFIG_BOOTBLOCK_SOURCE)) $(bootblock_custom) $(OPTION_TABLE_H) @printf CC $(subst $(obj)/,,$(@))\n $(CC) $(INCLUDES) -MM -MT$(objgenerated)/bootblock.inc \ $ $(objgenerated)/bootblock.inc.d $(CC) -c -S $(CFLAGS) -I. $(INCLUDES) $ -o $@ -$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld +$(objcbfs)/bootblock.debug: $(objgenerated)/bootblock.o $(objgenerated)/bootblock.ld $$(bootblock-objs) $(stages) @printf LINK $(subst $(obj)/,,$(@))\n ifeq ($(CONFIG_COMPILER_LLVM_CLANG),y) $(LD) -m armelf_linux_eabi -static -o $@.tmp -L$(obj) $ -T
[coreboot] New patch to review for coreboot: 04a409a armv7: Fix entry point in ram stage.
Hung-Te Lin (hun...@chromium.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2258
-gerrit
commit 04a409a7834d2a859676c7e70339e6cccf1ba9f7
Author: Hung-Te Lin hun...@chromium.org
Date: Fri Feb 1 15:27:39 2013 +0800
armv7: Fix entry point in ram stage.
Eliminated the warning message:
ld: warning: cannot find entry symbol _start; defaulting to 04000
The _start from c_start.S was deprecated so we need to define entry
point again in link description file.
Change-Id: I174428faa2e7f08cd91fe96a53e6efea9dc3634e
Signed-off-by: Hung-Te Lin hun...@chromium.org
---
src/arch/armv7/coreboot_ram.ld | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld
index 2f08d14..c69499c 100644
--- a/src/arch/armv7/coreboot_ram.ld
+++ b/src/arch/armv7/coreboot_ram.ld
@@ -32,6 +32,7 @@ SECTIONS
*/
.text : {
_text = .;
+ _start = .;
*(.text.stage_entry.armv7);
*(.text);
*(.text.*);
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
[coreboot] Patch set updated for coreboot: 8c30626 armv7: Fix entry point in ram stage.
Hung-Te Lin (hun...@chromium.org) just uploaded a new patch set to gerrit,
which you can find at http://review.coreboot.org/2258
-gerrit
commit 8c30626a4716e767408926690988d8d570312b8d
Author: Hung-Te Lin hun...@chromium.org
Date: Fri Feb 1 15:27:39 2013 +0800
armv7: Fix entry point in ram stage.
Eliminate the warning message:
ld: warning: cannot find entry symbol _start; defaulting to 04000
The _start from c_start.S is deprecated so we need to define entry
point again in link description file.
Change-Id: I174428faa2e7f08cd91fe96a53e6efea9dc3634e
Signed-off-by: Hung-Te Lin hun...@chromium.org
---
src/arch/armv7/coreboot_ram.ld | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld
index 2f08d14..c69499c 100644
--- a/src/arch/armv7/coreboot_ram.ld
+++ b/src/arch/armv7/coreboot_ram.ld
@@ -32,6 +32,7 @@ SECTIONS
*/
.text : {
_text = .;
+ _start = .;
*(.text.stage_entry.armv7);
*(.text);
*(.text.*);
--
coreboot mailing list: coreboot@coreboot.org
http://www.coreboot.org/mailman/listinfo/coreboot
