Re: [coreboot] DDR fails on F2A85-M
Hi Paul and David, We got an F2A85-M today. I haven't tried to boot coreboot yet but I can answer the question below: On Sat, May 11, 2013 at 10:20:31PM +0200, Paul Menzel wrote: Could you try to find out with `bios_extract` for example what AGESA version the vendor BIOS uses. bios_extract is not able to do anything with the image: $ ../bios_extract/bios_extract f2a85m-proprietary.rom Using file f2a85m-proprietary.rom (8192kB) Error: Unable to detect BIOS Image type. However, hd/strings suggest that the AGESA version is v1.1.0.7: 206209:007acd40 00 00 00 00 30 30 30 30 41 47 45 53 41 00 00 00 |AGESA...| 206210-007acd50 56 31 2e 31 2e 30 2e 37 20 20 20 20 00 00 00 00 |V1.1.0.7 | Thanks, Ward. -- Ward Vandewege | CTO, Free Software Foundation GPG Key: 25F774AB | http://status.fsf.org/ward http://fsf.org/blogs/RSS | http://identi.ca/cure Do you use free software? Donate to join the FSF and support freedom at http://www.fsf.org/register_form?referrer=859 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] DDR fails on F2A85-M
On Wed, May 22, 2013 at 11:18:46AM -0400, Ward Vandewege wrote: However, hd/strings suggest that the AGESA version is v1.1.0.7: 206209:007acd40 00 00 00 00 30 30 30 30 41 47 45 53 41 00 00 00 |AGESA...| 206210-007acd50 56 31 2e 31 2e 30 2e 37 20 20 20 20 00 00 00 00 |V1.1.0.7 | The above is for proprietary bios revision 5202. Bizarrely, the most recent proprietary bios revision for this board (6102) appears to use an older Agesa version, v1.1.0.1: 213221:0079e760 00 00 00 00 30 30 30 30 41 47 45 53 41 00 00 00 |AGESA...| 213222-0079e770 56 31 2e 31 2e 30 2e 31 20 20 20 20 00 00 00 00 |V1.1.0.1 | Thanks, Ward. -- Ward Vandewege | CTO, Free Software Foundation GPG Key: 25F774AB | http://status.fsf.org/ward http://fsf.org/blogs/RSS | http://identi.ca/cure Do you use free software? Donate to join the FSF and support freedom at http://www.fsf.org/register_form?referrer=859 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] DDR fails on F2A85-M
On Wed, May 22, 2013 at 9:49 AM, Ward Vandewege w...@gnu.org wrote: On Wed, May 22, 2013 at 11:18:46AM -0400, Ward Vandewege wrote: However, hd/strings suggest that the AGESA version is v1.1.0.7: 206209:007acd40 00 00 00 00 30 30 30 30 41 47 45 53 41 00 00 00 |AGESA...| 206210-007acd50 56 31 2e 31 2e 30 2e 37 20 20 20 20 00 00 00 00 |V1.1.0.7 | The above is for proprietary bios revision 5202. Bizarrely, the most recent proprietary bios revision for this board (6102) appears to use an older Agesa version, v1.1.0.1: 213221:0079e760 00 00 00 00 30 30 30 30 41 47 45 53 41 00 00 00 |AGESA...| 213222-0079e770 56 31 2e 31 2e 30 2e 31 20 20 20 20 00 00 00 00 |V1.1.0.1 | Thanks, Ward. Thanks for that. For the bios version I have (5103) it's: 007ac760 41 47 45 53 41 00 00 00 56 31 2e 31 2e 30 2e 37 |AGESA...V1.1.0.7| David -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] DDR fails on F2A85-M
If DDR3-667 works but AGESA fails at DDR3-1600, is it possible to go back to DDR3-667 or try an intermediate speed, say DDR3-1333 ? Maybe there is an option in AGESA where you can limit the maximum frequency. $ more src/mainboard/asus/f2a85-m/buildOpts.c […] #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY […] #define BLDCFG_MEMORY_CLOCK_SELECTDDR1600_FREQUENCY […] This is a great suggestion. I have spent a few days studying the AGESA code to find out what frequencies it tries. I concluded that the built-in AGESA autodetection is very limited. It may be there is a bug in the AGESA autodetection because this is not the same code path generally used in vendor BIOSes. The error messages about missing tables are suspicious. I believe it means AMD has the motherboard OEM (i.e. Asus) provide parameter tables measured with a scope that help the timings match the production board. Specifically I added IDS_HDT_CONSOLE (MEM_FLOW, MemPPSCFlow enter __FILE__ :%d\n, __LINE__); and IDS_HDT_CONSOLE (MEM_FLOW, MemPPSCFlow exit __FILE__ :%d\n, __LINE__); to the function MemPPSCFlow() in src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c I attempted setting BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT and BLDCFG_MEMORY_CLOCK_SELECT: diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 7f893f9..b9346b7 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -102,7 +102,7 @@ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED @@ -116,8 +116,8 @@ #define BLDCFG_POWER_DOWN_MODEPOWER_DOWN_BY_CHIP_SELECT #define BLDCFG_ONLINE_SPARE FALSE #define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECTDDR1600_FREQUENCY +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_LIMITED +#define BLDCFG_MEMORY_CLOCK_SELECTDDR1333_FREQUENCY #define BLDCFG_DQS_TRAINING_CONTROL TRUE #define BLDCFG_IGNORE_SPD_CHECKSUMFALSE #define BLDCFG_USE_BURST_MODE FALSE I then ran make clean; make and tried booting coreboot, but hit the same error (ASSERTION FAILED mmExcludeDimm.c line 26). I'm going to keep trying lower speeds. I also attemped configuring coreboot with 1.65V though my memory is only rated to 1.60V. I checked with the vendor BIOS that the memory is at least bootable at 1.65V. Then I tried booting coreboot at 1.65V (without the previous memory bus limit), but it stopped at the same assertion. Could you try to find out with `bios_extract` for example what AGESA version the vendor BIOS uses. I have not had time to run bios_extract but I did identify that the BIOS file supplied on Asus' website for the F2A85-M/CSM is identical to the data on the chip after stripping the first 2048 bytes. For example: dd if=f2a85-m-asus-5103-2012.09.10.v2.10.1208.cap of=f2a85-flashrom.bin bs=2048 skip=1 PS: David, Google Mail changed the compose interface and they send HTML message in addition to text by default. Could you change that to just plain text please [3][4]? I think this is now plain-text only, please let me know if gmail sends it as HTML. Sorry! -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] DDR fails on F2A85-M
The board does boot, but only at DDR667. (I tried each option up to DDR1600) On Tue, May 21, 2013 at 7:19 PM, David Hubbard david.c.hubbard+coreb...@gmail.com wrote: If DDR3-667 works but AGESA fails at DDR3-1600, is it possible to go back to DDR3-667 or try an intermediate speed, say DDR3-1333 ? Maybe there is an option in AGESA where you can limit the maximum frequency. $ more src/mainboard/asus/f2a85-m/buildOpts.c […] #define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY […] #define BLDCFG_MEMORY_CLOCK_SELECTDDR1600_FREQUENCY […] This is a great suggestion. I have spent a few days studying the AGESA code to find out what frequencies it tries. I concluded that the built-in AGESA autodetection is very limited. It may be there is a bug in the AGESA autodetection because this is not the same code path generally used in vendor BIOSes. The error messages about missing tables are suspicious. I believe it means AMD has the motherboard OEM (i.e. Asus) provide parameter tables measured with a scope that help the timings match the production board. Specifically I added IDS_HDT_CONSOLE (MEM_FLOW, MemPPSCFlow enter __FILE__ :%d\n, __LINE__); and IDS_HDT_CONSOLE (MEM_FLOW, MemPPSCFlow exit __FILE__ :%d\n, __LINE__); to the function MemPPSCFlow() in src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c I attempted setting BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT and BLDCFG_MEMORY_CLOCK_SELECT: diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index 7f893f9..b9346b7 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -102,7 +102,7 @@ #define BLDCFG_AMD_PLATFORM_TYPE AMD_PLATFORM_MOBILE -#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1866_FREQUENCY +#define BLDCFG_MEMORY_BUS_FREQUENCY_LIMIT DDR1333_FREQUENCY #define BLDCFG_MEMORY_MODE_UNGANGED TRUE #define BLDCFG_MEMORY_QUAD_RANK_CAPABLE TRUE #define BLDCFG_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED @@ -116,8 +116,8 @@ #define BLDCFG_POWER_DOWN_MODE POWER_DOWN_BY_CHIP_SELECT #define BLDCFG_ONLINE_SPARE FALSE #define BLDCFG_BANK_SWIZZLE TRUE -#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_AUTO -#define BLDCFG_MEMORY_CLOCK_SELECTDDR1600_FREQUENCY +#define BLDCFG_TIMING_MODE_SELECT TIMING_MODE_LIMITED +#define BLDCFG_MEMORY_CLOCK_SELECTDDR1333_FREQUENCY #define BLDCFG_DQS_TRAINING_CONTROL TRUE #define BLDCFG_IGNORE_SPD_CHECKSUMFALSE #define BLDCFG_USE_BURST_MODE FALSE I then ran make clean; make and tried booting coreboot, but hit the same error (ASSERTION FAILED mmExcludeDimm.c line 26). I'm going to keep trying lower speeds. I also attemped configuring coreboot with 1.65V though my memory is only rated to 1.60V. I checked with the vendor BIOS that the memory is at least bootable at 1.65V. Then I tried booting coreboot at 1.65V (without the previous memory bus limit), but it stopped at the same assertion. Could you try to find out with `bios_extract` for example what AGESA version the vendor BIOS uses. I have not had time to run bios_extract but I did identify that the BIOS file supplied on Asus' website for the F2A85-M/CSM is identical to the data on the chip after stripping the first 2048 bytes. For example: dd if=f2a85-m-asus-5103-2012.09.10.v2.10.1208.cap of=f2a85-flashrom.bin bs=2048 skip=1 PS: David, Google Mail changed the compose interface and they send HTML message in addition to text by default. Could you change that to just plain text please [3][4]? I think this is now plain-text only, please let me know if gmail sends it as HTML. Sorry! -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] DDR fails on F2A85-M
Hi Rudolf, Paul, I pulled the version from http://review.coreboot.org/#/c/3200/ but my F2A85-M still halts in the same place: ASSERTION FAILED: file 'src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmExcludeDimm.c', line 263 I am using CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_150 I uncommented the #define IDSOPT_IDS_ENABLED in src/mainboard/asus/f2a85-m/OptionsIds.h and captured the serial output. What do you think I should pursue first, option A or B: Option A is where AGESA says: MemClkFreq changed: 333 MHz - 800 MHzMemFInitTableDrive [0001] Start MemFInitTableDrive End No Rtt entries * ERROR Event: 04063500 Data: 0, 0, 0, 0 Disable DCT0 due to unsupported DIMM configuration Memclk Freq: 800 RdPtr: 6 It sounds like AGESA needs a table with Rtt entries? Option B is where AGESA says: Going into training stage 2. Complete training at DDR667 is done. If DDR3-667 works but AGESA fails at DDR3-1600, is it possible to go back to DDR3-667 or try an intermediate speed, say DDR3-1333 ? I put a sample log at https://gist.github.com/davidhubbard/5552910 Here are some things I did: 1. cold boot after removing AC power for ~30 s 2. try the other DIMM in slot A1 (still just a single DIMM in the machine) 3. hit the reset switch a couple of times The manufacturer page for the memory says: [1] Non-ECC Tested Speed DDR3-2133 MHz Tested Latency 11-11-11-30 2N Tested Voltage 1.5 -1.6V SPD Speed 1600 MHz SPD Voltage 1.5V Some useful snippets from the log: MemoryClockSelect : 800 AmdMemAuto: Start MEM PARAMS: BottomIo : 00E0 MemHoleRemap : 1 LimitBelow1TB : 1 UserTimingMode : 0 MemClockValue : 800 BankIntlv : 1 NodeIntlv : 0 ChannelIntlv : 1 EccFeature : 0 PowerDown : 1 OnLineSpare : 0 Parity : 0 BankSwizzle : 1 MemClr : 1 UmaMode : 1 UmaSize : 8192 MemRestoreCtl : 0 SaveMemContextCtl : 0 ExternalVrefCtl : 0 ForceTrainMode : 2 Node0: 1.5V - 800MHz MemClkFreq: 333 MHz MemClkFreq changed: 333 MHz - 800 MHz [1] http://www.gskill.com/products.php?index=397 [2] this is the same product: http://www.newegg.com/Product/Product.aspx?Item=N82E16820231468 -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
Re: [coreboot] DDR fails on F2A85-M
Hi all, I am using CONFIG_BOARD_ASUS_F2A85_M_DDR3_VOLT_150 There seems to be a problem in the code logic, Paul should know more. Maybe playing with the SMBus write and set voltage to 165 might help? I uncommented the #define IDSOPT_IDS_ENABLED in src/mainboard/asus/f2a85-m/OptionsIds.h and captured the serial output. What do you think I should pursue first, option A or B: Unfortunately I don't know. Hope some AGESA expert will step in. I'm AFK for the weekend so I can't help more. Have a look to the mainboard manual, i think dimm labeled A1 is in fact the second channel and not the first one. Please give a try in other slots too. Sorry for the short answer, I travel soonish AFK. Thanks Rudolf -- coreboot mailing list: coreboot@coreboot.org http://www.coreboot.org/mailman/listinfo/coreboot
