[coreboot] Re: Yangling/ FW6C board with different SUPERIO CHIP, I found the problem
> Even the "support" Team from the seller things it shold come with an ITE8772, very mysterious.. > Did you ever seen one of those devices coming in from the OEM with variation in onboard ICs ? I haven't seen/heard about such a case so I am also surprised. On 14.05.2021 21:42, Angel Pons wrote: Hi, On Fri, May 14, 2021 at 7:38 PM lain via coreboot wrote: Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x8613, rev=0x8 superiotool doesn't know about the IT8613E, but looks like there's one. Too old coreboot revision probably to get superiotool detect it, because we have been adding IT8613E support: https://review.coreboot.org/c/coreboot/+/31620 Best regards, Angel ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org Best regards, -- Michał Żygowski Firmware Engineer https://3mdeb.com | @3mdeb_com ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Yangling/ FW6C board with different SUPERIO CHIP, I found the problem
Hi, On Fri, May 14, 2021 at 7:38 PM lain via coreboot wrote: > > Probing for ITE Super I/O (init=standard) at 0x2e... > Failed. Returned data: id=0x8613, rev=0x8 superiotool doesn't know about the IT8613E, but looks like there's one. Best regards, Angel ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Yangling/ FW6C board with different SUPERIO CHIP, I found the problem
Strangely superiotool does not find anything atm. Maybe it was a 1 in 1 mistake of an false IC soldered, i am still happy as it works for me now, and dont have to touch it anymore. Even the "support" Team from the seller things it shold come with an ITE8772, very mysterious.. Did you ever seen one of those devices coming in from the OEM with variation in onboard ICs ? Err log was empty Sorry for copy it plain in: superiotool r6637 Probing for ALi Super I/O at 0x3f0... Failed. Returned data: id=0x, rev=0xff Probing for ALi Super I/O at 0x370... Failed. Returned data: id=0x, rev=0xff Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x2e... Failed. Returned data: vid=0x, id=0x Probing for Fintek Super I/O at 0x4e... Failed. Returned data: vid=0x, id=0x Probing for ITE Super I/O (init=standard) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x25e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=standard) at 0x2e... Failed. Returned data: id=0x8613, rev=0x8 Probing for ITE Super I/O (init=it8502e) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x2e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=standard) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8502e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8761e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=it8228e) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=0x87,0x87) at 0x4e... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=legacy/it8661f) at 0x370... Failed. Returned data: id=0x, rev=0xf Probing for ITE Super I/O (init=legacy/it8671f) at 0x370... Failed. Returned data: id=0x, rev=0xf Probing for NSC Super I/O at 0x2e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x4e... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x15c... Failed. Returned data: port=0xff, port+1=0xff Probing for NSC Super I/O at 0x164e... Failed. Returned data: port=0xff, port+1=0xff Probing for Nuvoton Super I/O at 0x164e... Failed. Returned data: chip_id=0x Probing for Nuvoton Super I/O (sid=0xfc) at 0x164e... Failed. Returned data: sid=0xff, id=0x, rev=0x00 Probing for Nuvoton Super I/O at 0x2e... Failed. Returned data: chip_id=0x Probing for Nuvoton Super I/O (sid=0xfc) at 0x2e... Failed. Returned data: sid=0xff, id=0x, rev=0x00 Probing for Nuvoton Super I/O at 0x4e... Failed. Returned data: chip_id=0x Probing for Nuvoton Super I/O (sid=0xfc) at 0x4e... Failed. Returned data: sid=0xff, id=0x, rev=0x00 Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x2e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x4e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x162e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x164e... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x3f0... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x20/0x21) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for SMSC Super I/O (idregs=0x0d/0x0e) at 0x370... Failed. Returned data: id=0xff, rev=0xff Probing for Winbond Super I/O (init=0x88) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O (init=0x89) at 0x2e... Failed. Returned data: id/oldid=0xff/0x0f, rev=0xff Probing for Winbond Super I/O
[coreboot] Re: Yangling/ FW6C board with different SUPERIO CHIP, I found the problem
Hi, Glad to hear that you get that working. Interestingly it is the older FW6 variant based on Kaby Lake so it should have ITE8772. Do you have the log from supertiotool.log? Additionally superiotool.err.log may be helpful. IT8613E should be supported. Best regards, -- Michał Żygowski Firmware Engineer https://3mdeb.com | @3mdeb_com On 5/14/21 3:03 PM, lain wrote: > Hello Michail > setting the register values for PCICLOCK to 25MHz as on the Braswell > protectli devices did the trick for me, i have serial working now > flawlessly. > Did you see the git diff i send ? > > I have trouble get superiotool to detect the SUPERIO chip it seems the > current version is not even probing for the 8613E. > > here is the cpuinfo ( i disabled SMT and SGX in coreboot) > > Architecture: x86_64 > CPU op-mode(s): 32-bit, 64-bit > Byte Order: Little Endian > Address sizes: 39 bits physical, 48 bits virtual > CPU(s): 2 > On-line CPU(s) list: 0,1 > Thread(s) per core: 1 > Core(s) per socket: 2 > Socket(s): 1 > NUMA node(s): 1 > Vendor ID: GenuineIntel > CPU family: 6 > Model: 142 > Model name: Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz > Stepping: 9 > CPU MHz: 1100.126 > CPU max MHz: 3100. > CPU min MHz: 400. > BogoMIPS: 5424.00 > Virtualization: VT-x > L1d cache: 32K > L1i cache: 32K > L2 cache: 256K > L3 cache: 3072K > NUMA node0 CPU(s): 0,1 > Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr > pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe > syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts > rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq > pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg fma cx16 > xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer > aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb > invpcid_single pti ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority > ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid > mpx rdseed adx smap clflushopt intel_pt xsaveopt xsavec xgetbv1 xsaves > dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp md_clear > flush_l1d > > > On Friday, May 14, 2021 11:30 CEST, Michał Żygowski > wrote: > >> Iain, >> >> Also please check what is the CPU on your platform. Please run `cat >> /proc/cpuinfo` and paste me the CPU brand string, because FW6 has >> refreshed variants based on Kaby Lake Refresh CPUs and different Super >> I/O ITE8613, which we will upload the source code to upstream >> coreboot soon. >> >> On 5/13/21 8:15 PM, lain wrote: >> > Hello Michal, >> > i found the regarding problem. >> > The board i got from aliexpress has an SUPERIO 8613 insteat of a >> > SUPERIO 8772F, this other superio seem to be support by coreboot but >> > dumbly changing this in the .config seems to fail, do you think you >> > could help me compiling it for this SUPERIO chip ? >> > >> > best regards >> > lain >> >> >> Best regards, >> >> -- >> Michał Żygowski >> Firmware Engineer >> https://3mdeb.com | @3mdeb_com >> > > > > ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Yangling/ FW6C board with different SUPERIO CHIP, I found the problem
Hello Michail setting the register values for PCICLOCK to 25MHz as on the Braswell protectli devices did the trick for me, i have serial working now flawlessly. Did you see the git diff i send ? I have trouble get superiotool to detect the SUPERIO chip it seems the current version is not even probing for the 8613E. here is the cpuinfo ( i disabled SMT and SGX in coreboot) Architecture: x86_64 CPU op-mode(s): 32-bit, 64-bit Byte Order: Little Endian Address sizes: 39 bits physical, 48 bits virtual CPU(s): 2 On-line CPU(s) list: 0,1 Thread(s) per core: 1 Core(s) per socket: 2 Socket(s): 1 NUMA node(s): 1 Vendor ID: GenuineIntel CPU family: 6 Model: 142 Model name: Intel(R) Core(TM) i5-7200U CPU @ 2.50GHz Stepping: 9 CPU MHz: 1100.126 CPU max MHz: 3100. CPU min MHz: 400. BogoMIPS: 5424.00 Virtualization: VT-x L1d cache: 32K L1i cache: 32K L2 cache: 256K L3 cache: 3072K NUMA node0 CPU(s): 0,1 Flags: fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 clflush dts acpi mmx fxsr sse sse2 ss ht tm pbe syscall nx pdpe1gb rdtscp lm constant_tsc art arch_perfmon pebs bts rep_good nopl xtopology nonstop_tsc cpuid aperfmperf tsc_known_freq pni pclmulqdq dtes64 monitor ds_cpl vmx est tm2 ssse3 sdbg fma cx16 xtpr pdcm pcid sse4_1 sse4_2 x2apic movbe popcnt tsc_deadline_timer aes xsave avx f16c rdrand lahf_lm abm 3dnowprefetch cpuid_fault epb invpcid_single pti ssbd ibrs ibpb stibp tpr_shadow vnmi flexpriority ept vpid ept_ad fsgsbase tsc_adjust bmi1 avx2 smep bmi2 erms invpcid mpx rdseed adx smap clflushopt intel_pt xsaveopt xsavec xgetbv1 xsaves dtherm ida arat pln pts hwp hwp_notify hwp_act_window hwp_epp md_clear flush_l1d On Friday, May 14, 2021 11:30 CEST, Michał Żygowski wrote: Iain, Also please check what is the CPU on your platform. Please run `cat /proc/cpuinfo` and paste me the CPU brand string, because FW6 has refreshed variants based on Kaby Lake Refresh CPUs and different Super I/O ITE8613, which we will upload the source code to upstream coreboot soon. On 5/13/21 8:15 PM, lain wrote: > Hello Michal, > i found the regarding problem. > The board i got from aliexpress has an SUPERIO 8613 insteat of a > SUPERIO 8772F, this other superio seem to be support by coreboot but > dumbly changing this in the .config seems to fail, do you think you > could help me compiling it for this SUPERIO chip ? > > best regards > lain Best regards, -- Michał Żygowski Firmware Engineer https://3mdeb.com | @3mdeb_com ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Yangling/ FW6C board with different SUPERIO CHIP, I found the problem
Iain, Also please check what is the CPU on your platform. Please run `cat /proc/cpuinfo` and paste me the CPU brand string, because FW6 has refreshed variants based on Kaby Lake Refresh CPUs and different Super I/O ITE8613, which we will upload the source code to upstream coreboot soon. On 5/13/21 8:15 PM, lain wrote: > Hello Michal, > i found the regarding problem. > The board i got from aliexpress has an SUPERIO 8613 insteat of a > SUPERIO 8772F, this other superio seem to be support by coreboot but > dumbly changing this in the .config seems to fail, do you think you > could help me compiling it for this SUPERIO chip ? > > best regards > lain Best regards, -- Michał Żygowski Firmware Engineer https://3mdeb.com | @3mdeb_com ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
[coreboot] Re: Yangling/ FW6C board with different SUPERIO CHIP, I found the problem
Hi Iain, On 5/13/21 8:15 PM, lain wrote: > Hello Michal, > i found the regarding problem. > The board i got from aliexpress has an SUPERIO 8613 insteat of a > SUPERIO 8772F, this other superio seem to be support by coreboot but > dumbly changing this in the .config seems to fail, do you think you > could help me compiling it for this SUPERIO chip ? Okay that would explain everything. Is this the Protectli branded board or the chinese Yanling? I can upload some blind patch that will support ITE 8613, but could you please run coreboot's superiotool on the ORIGINAL firmware? ITE8613 clock settings are a bit tricky, so I need a dump of the settings. Because of the tricky clock settings, you get the garbage on serial port now so copyign from FW2B/FW4B is not the best way to go. Please attach the dump in your response. For convenience you may use our fwdump-docker if you want to avoid compiling this tool from source: https://github.com/3mdeb/fwdump-docker Command to use: |docker run --rm --privileged -it -v $PWD:/home/fwdump 3mdeb/fwdump-docker:1.1.0 getlogs| Simply superiotool.log from the archive will suffice. > > best regards > lain Best regards, -- Michał Żygowski Firmware Engineer https://3mdeb.com | @3mdeb_com ___ coreboot mailing list -- coreboot@coreboot.org To unsubscribe send an email to coreboot-le...@coreboot.org
