Re: [coreboot] tyan s2882-d not booting

[Ward Vandewege]

On Mon, Dec 03, 2012 at 05:12:03PM -0800, Kui Zhang wrote:
 I got some old boxes:  tyan s2882-d, dual opteron processors, 16G RAM. 512K
 bios flash.
 
 So far, I am not able to get it to boot. It appears to reboot during CPU
 init.
 
 If anyone got coreboot working on this board, which revision did it worked
 last ?

That would have been me, I think. I'm not 100% sure we still have an s2882;
we only had one if I recall correctly. I can check later this week. Some
revision(s) it worked with are listed on http://www.coreboot.org/Tyan_S2882.
Those are revisions from the old SVN tree; you can grep the git log for the
svn revision number (it is listed); you'll see these are revisions from 2006.

I do have an s2881 that I booted succesfully about 5 or 6 weeks ago, with
coreboot head. It's a very similar board.

Have you tried with less ram?

Thanks,
Ward.

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[coreboot] tyan s2882-d not booting

[Kui Zhang]

I got some old boxes:  tyan s2882-d, dual opteron processors, 16G RAM. 512K
bios flash.

So far, I am not able to get it to boot. It appears to reboot during CPU
init.

If anyone got coreboot working on this board, which revision did it worked
last ?


Serial console:

coreboot-4.0-3129-gefb7940 Fri Nov 30 22:50:45 PST 2012 starting...
Enabling routing table for node 00 done.
Enabling SMP settings
(0,1) link=01
(1,0) link=01
setup_remote_node: done
Renaming current temporary node to 01 done.
Enabling routing table for node 01 done.
02 nodes initialized.
coherent_ht_finalize
done
SBLink=00
NC node|link=00
entering ht_optimize_link
pos=0x8a, unfiltered freq_cap=0x8075
pos=0x8a, filtered freq_cap=0x75
pos=0xce, unfiltered freq_cap=0x35
freq_cap1=0x75, freq_cap2=0x15
dev1 old_freq=0x4, freq=0x4, needs_reset=0x0
dev2 old_freq=0x4, freq=0x4, needs_reset=0x0
width_cap1=0x11, width_cap2=0x11
dev1 input ln_width1=0x4, ln_width2=0x4
dev1 input width=0x1
dev1 output ln_width1=0x4, ln_width2=0x4
dev1 input|output width=0x11
old dev1 input|output width=0x11
dev2 input|output width=0x11
old dev2 input|output width=0x11
entering ht_optimize_link
pos=0xd2, unfiltered freq_cap=0x35
pos=0xce, unfiltered freq_cap=0x1
pos=0xce, filtered freq_cap=0x1
freq_cap1=0x15, freq_cap2=0x1
dev1 old_freq=0x0, freq=0x0, needs_reset=0x0
dev2 old_freq=0x0, freq=0x0, needs_reset=0x0
width_cap1=0x0, width_cap2=0x0
dev1 input ln_width1=0x3, ln_width2=0x3
dev1 input width=0x0
dev1 output ln_width1=0x3, ln_width2=0x3
dev1 input|output width=0x0
old dev1 input|output width=0x0
dev2 input|output width=0x0
old dev2 input|output width=0x0
SMBus controller enabled
Ram1.00
setting up CPU00 northbridge registers
done.
Ram1.01
setting up CPU01 northbridge registers
done.
Ram2.00
Enabling dual channel memory
Registered
200MHz
Interleaved
RAM end at 0x0080 kB
Handling memory mapped above 4 GB
Upper RAM end at 0x0080 kB
Correcting memory amount mapped below 4 GB
Adjusting lower RAM end
Lower RAM end at 0x003f kB
Ram2.01
Enabling dual channel memory
Registered
200MHz
Interleaved
RAM end at 0x0100 kB
Handling memory mapped above 4 GB
Upper RAM end at 0x0100 kB
Correcting memory amount mapped below 4 GB
Adjusting lower RAM end
Lower RAM end at 0x003f kB
Ram3
ECC enabled
ECC enabled
Initializing memory:  done
Initializing memory:  done
Handling memory hole at 0x0030 (default)
RAM end at 0x0110 kB
Handling memory mapped above 4 GB
Upper RAM end at 0x0110 kB
Correcting memory amount mapped below 4 GB
Adjusting lower RAM end
Lower RAM end at 0x0030 kB
Ram4
v_esp=000cff48
testx = 5a5a5a5a
Copying data from cache to RAM -- switching to use RAM as stack... Done
testx = 5a5a5a5a
Disabling cache as ram now
Clearing initial memory region: Done
Loading image.
CBFS: Looking for 'fallback/coreboot_ram'
CBFS: found.



INIT detected from  --- { APICID = 00 NODEID = 00 COREID = 00} ---

Issuing SOFT_RESET...



No error during make. I tried building on x86_64 and x86.


thanks
Kui.Z
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Re: [coreboot] tyan s2882-d not booting

[Peter Stuge]

Kui Zhang wrote:
 I got some old boxes:  tyan s2882-d, dual opteron processors, 16G RAM.
 512K bios flash.
 
 So far, I am not able to get it to boot. It appears to reboot during
 CPU init.
 
 If anyone got coreboot working on this board, which revision did it
 worked last ?

I don't have it working, but I would suggest to try either the last
commit which touches the mainboard files, or the last commit which
touches the platform component files (northbridge and southbridge).

git log with appropriate parameters makes it easy to find these
commits from the history.


 Ram4
 v_esp=000cff48
 testx = 5a5a5a5a
 Copying data from cache to RAM -- switching to use RAM as stack... Done
 testx = 5a5a5a5a
 Disabling cache as ram now
 Clearing initial memory region: Done
 Loading image.
 CBFS: Looking for 'fallback/coreboot_ram'
 CBFS: found.
..

It looks like raminit worked, but the fact that executing from RAM
does *not* work speaks against that.


 No error during make. I tried building on x86_64 and x86.

Which toolchain did you use when building? Please run

make crossgcc

in the top-level coreboot directory to build a known-good toolchain
if you haven't already. After running that command, you can verify
that the toolchain will be used the next time you compile coreboot:

cat .xcompile

should show various paths into a subdirectory with an xgcc/ path
component.


//Peter

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