[gcc(refs/users/meissner/heads/work168-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:aca81acacb06caf3031674541bd83bd6a70776ac commit aca81acacb06caf3031674541bd83bd6a70776ac Author: Michael Meissner Date: Tue Jun 11 18:24:20 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 12 1 file changed, 12 insertions(+) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index ec645be708f2..e1609221b2c7 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,3 +1,15 @@ + Branch work168-tar, patch #203 + +Add -mlrspr. + +2024-06-11 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add + support for -mlrspr. + * config/rs6000/rs6000.opt (-mlrspr): New debug option. + Branch work168-tar, patch #202 Add options for modes in SPR registers.
[gcc(refs/users/meissner/heads/work168-tar)] Add -mlrspr.
https://gcc.gnu.org/g:1232a584429302448e9ff8dee30e92901b37870a commit 1232a584429302448e9ff8dee30e92901b37870a Author: Michael Meissner Date: Tue Jun 11 18:23:32 2024 -0400 Add -mlrspr. 2024-06-11 Michael Meissner gcc/ * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add support for -mlrspr. * config/rs6000/rs6000.opt (-mlrspr): New debug option. Diff: --- gcc/config/rs6000/rs6000.cc | 4 +++- gcc/config/rs6000/rs6000.opt | 4 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index 70214e4b28c5..3e118c866081 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1949,7 +1949,9 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) return (!orig_complex_p && mode == SImode); case LR_REGNO: - return (!orig_complex_p && mode == Pmode); + if (!TARGET_LRSPR) + return (!orig_complex_p && mode == Pmode); + /* fall through. */ case CTR_REGNO: case TAR_REGNO: diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 27f873972b57..137290b8364f 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -658,6 +658,10 @@ mdfspr Target Undocumented Var(TARGET_DFSPR) Init(0) Allow (do not allow) 64-bit floating point to be in the CTR or TAR registers. +mlrspr +Target Undocumented Var(TARGET_LRSPR) Init(0) +Treat (do not treat) the LR register like CTR/TAR in terms of what modes it can hold. + ; Documented parameters -param=rs6000-vect-unroll-limit=
[gcc(refs/users/meissner/heads/work168-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:34c54380d9e75419800af47d5c0a26b1bb045bd1
commit 34c54380d9e75419800af47d5c0a26b1bb045bd1
Author: Michael Meissner
Date: Mon Jun 10 18:01:50 2024 -0400
Update ChangeLog.*
Diff:
---
gcc/ChangeLog.tar | 18 ++
1 file changed, 18 insertions(+)
diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar
index a69b0f59eac..ec645be708f 100644
--- a/gcc/ChangeLog.tar
+++ b/gcc/ChangeLog.tar
@@ -1,3 +1,21 @@
+ Branch work168-tar, patch #202
+
+Add options for modes in SPR registers.
+
+2024-06-10 Michael Meissner
+
+gcc/
+
+ * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add
+ support for -m{cc,qi,hi,si,sf,df}spr.
+ (rs6000_debug_reg_global): Print out SPR mode options.
+ * config/rs6000/rs6000.opt (-mccspr): New option.
+ (-mqispr): Likewise.
+ (-mhispr): Likewise.
+ (-msispr): Likewise.
+ (-msfspr): Likewise.
+ (-mdfspr): Likewise.
+
Branch work168-tar, patch #201
Add support for the TAR register.
[gcc(refs/users/meissner/heads/work168-tar)] Add options for modes in SPR registers.
https://gcc.gnu.org/g:46132ad0081e4f55c19977b00f4c6d9280cead21
commit 46132ad0081e4f55c19977b00f4c6d9280cead21
Author: Michael Meissner
Date: Mon Jun 10 18:00:27 2024 -0400
Add options for modes in SPR registers.
2024-06-10 Michael Meissner
gcc/
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add
support for -m{cc,qi,hi,si,sf,df}spr.
(rs6000_debug_reg_global): Print out SPR mode options.
* config/rs6000/rs6000.opt (-mccspr): New option.
(-mqispr): Likewise.
(-mhispr): Likewise.
(-msispr): Likewise.
(-msfspr): Likewise.
(-mdfspr): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.cc | 60 ++--
gcc/config/rs6000/rs6000.opt | 24 ++
2 files changed, 76 insertions(+), 8 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c106e13b8ad..70214e4b28c 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1946,18 +1946,44 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
{
case VRSAVE_REGNO:
case VSCR_REGNO:
+ return (!orig_complex_p && mode == SImode);
+
case LR_REGNO:
+ return (!orig_complex_p && mode == Pmode);
+
case CTR_REGNO:
case TAR_REGNO:
- {
- unsigned reg_size = ((regno == VRSAVE_REGNO || regno == VSCR_REGNO)
-? 4
-: UNITS_PER_WORD);
+ if (orig_complex_p)
+ return 0;
- return (!orig_complex_p
- && GET_MODE_SIZE (mode) <= reg_size
- && SCALAR_INT_MODE_P (mode));
- }
+ if (GET_MODE_CLASS (mode) == MODE_CC)
+ return TARGET_CCSPR != 0;
+
+ switch (mode)
+ {
+ case E_QImode:
+ return TARGET_QISPR != 0;
+
+ case E_HImode:
+ return TARGET_HISPR != 0;
+
+ case E_SImode:
+ return (TARGET_SISPR != 0 || !TARGET_POWERPC64);
+
+ case E_DImode:
+ return TARGET_POWERPC64;
+
+ case E_SFmode:
+ return (TARGET_SFSPR != 0);
+
+ case E_DFmode:
+ return (TARGET_DFSPR != 0 && TARGET_POWERPC64);
+
+ default:
+ break;
+ }
+
+ return false;
default:
break;
@@ -2621,6 +2647,24 @@ rs6000_debug_reg_global (void)
if (TARGET_DIRECT_MOVE_128)
fprintf (stderr, DEBUG_FMT_D, "VSX easy 64-bit mfvsrld element",
(int)VECTOR_ELEMENT_MFVSRLD_64BIT);
+
+ if (TARGET_CCSPR)
+fprintf (stderr, DEBUG_FMT_S, "Condition modes in SPR", "yes");
+
+ if (TARGET_QISPR)
+fprintf (stderr, DEBUG_FMT_S, "QImode in SPR", "yes");
+
+ if (TARGET_HISPR)
+fprintf (stderr, DEBUG_FMT_S, "HImode in SPR", "yes");
+
+ if (TARGET_SISPR)
+fprintf (stderr, DEBUG_FMT_S, "SImode in SPR", "yes");
+
+ if (TARGET_SFSPR)
+fprintf (stderr, DEBUG_FMT_S, "SFmode in SPR", "yes");
+
+ if (TARGET_DFSPR)
+fprintf (stderr, DEBUG_FMT_S, "DFmode in SPR", "yes");
}
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 7f7a283bc99..27f873972b5 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -634,6 +634,30 @@ mtar
Target Undocumented Mask(TAR) Var(rs6000_isa_flags)
Allow (do not allow) use the TAR register.
+mccspr
+Target Undocumented Var(TARGET_CCSPR) Init(0)
+Allow (do not allow) condition modes to be in the CTR or TAR registers.
+
+mqispr
+Target Undocumented Var(TARGET_QISPR) Init(1)
+Allow (do not allow) 8-bit integers to be in the CTR or TAR registers.
+
+mhispr
+Target Undocumented Var(TARGET_HISPR) Init(1)
+Allow (do not allow) 16-bit integers to be in the CTR or TAR registers.
+
+msispr
+Target Undocumented Var(TARGET_SISPR) Init(1)
+Allow (do not allow) 32-bit integers to be in the CTR or TAR registers.
+
+msfspr
+Target Undocumented Var(TARGET_SFSPR) Init(0)
+Allow (do not allow) 32-bit floating point to be in the CTR or TAR registers.
+
+mdfspr
+Target Undocumented Var(TARGET_DFSPR) Init(0)
+Allow (do not allow) 64-bit floating point to be in the CTR or TAR registers.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
[gcc(refs/users/meissner/heads/work168-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:42f6f1cdec43877fd0532acd297deba0aec5c3c2 commit 42f6f1cdec43877fd0532acd297deba0aec5c3c2 Author: Michael Meissner Date: Tue Jun 4 14:29:19 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 248 +- 1 file changed, 247 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index c512209738a..a69b0f59eac 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,6 +1,252 @@ + Branch work168-tar, patch #201 + +Add support for the TAR register. + +2024-06-04 Michael Meissner + +gcc/ + + * config/rs6000/constraints.md (h constraint): Add TAR register to the + documentation. + (wt constraint): New constraint. + * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Document that we + do not explicitly add -mtar for power9. + (OTHER_POWER10_MASKS): Add -mtar. + (POWERPC_MASKS): Likewise. + * config/rs6000/rs6000.cc (rs6000_reg_names): Add TAR register support. + (alt_reg_names): Likewise. + (rs6000_hard_regno_mode_ok_uncached): Likewise. + (rs6000_debug_reg_global): Print the register class that wt maps too. + (rs6000_init_hard_regno_mode_ok): Add TAR register support. + (rs6000_option_override_internal): Restrict -mtar to power9 and above. + (rs6000_conditional_register_usage): Add TAR register support. + (print_operand): Likewise. + (rs6000_debugger_regno): Likewise. + (rs6000_opt_masks): Add support for -mtar. + * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Add TAR register + support. + (FIXED_REGISTERS): Likewise. + (CALL_REALLY_USED_REGISTERS): Likewise. + (REG_ALLOC_ORDER): Likewise. + (enum reg_class): Likewise. + (REG_CLASS_NAMES): Likewise. + (REG_CLASS_CONTENTS): Likewise. + (enum r6000_reg_class_enum): Add support for the wt constraint. + * config/rs6000/rs6000.md (TAR_REGNO): New constant. + (mov_internal): Add TAR register support. + (call_indirect_nonlocal_sysv): Likewise. + (call_value_indirect_nonlocal_sysv): Likewise. + (call_indirect_aix): Likewise. + (call_value_indirect_aix): Likewise. + (call_indirect_elfv2): Likewise. + (call_indirect_pcrel): Likewise. + (call_value_indirect_elfv2): Likewise. + (call_value_indirect_pcrel): Likewise. + (*sibcall_indirect_nonlocal_sysv): Likewise. + (sibcall_value_indirect_nonlocal_sysv): Likewise. + (indirect_jump): Likewise. + (@indirect_jump_nospec): Likewise. + (@tablejump_insn_normal): Likewise. + (@tablejump_insn_nospec): Likewise. + * config/rs6000/rs6000.opt (-mtar): New option. + +gcc/testsuite/ + + * gcc.target/powerpc/ppc-switch-1.c: Update test for the TAR register. + * gcc.target/powerpc/pr51513.c: Likewise. + * gcc.target/powerpc/safe-indirect-jump-2.c: Likewise. + * gcc.target/powerpc/safe-indirect-jump-3.c: Likewise. + * gcc.target/powerpc/tar-register.c: New test. + + Branch work168-tar, patch #200 + +Restrict SPR to appropriate integer modes. + +In preparation for the patches to add support for the TAR register, I restricted +the modes that special purpose registers (SPRs) could hold to be appropriate +sized scalar integers. I have discovered occasionally when GCC has run out of +registers, it will use the SPRs to hold values instead of spilling them to the +stack. The LR/CTR registers can hold 8/16/32-bit values and on 64-bit systems, +they can also hold 64-bit values. The VRSAVE and VSCR registers can only hold +32-bit values. + +2024-06-04 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Restrict + SPR registers to only hold scalar integer modes of an appropriate size. + * config/rs6000/rs6000.md (movcc_): Remove alternatives that move + values to/from the SPRs. + (movsf_hardfloat): Likewise. + (movsd_hardfloat): Likewise. + (mov_softfloat): Likewise. + (mov_softfloat32): Likewise. + (mov_hardfloat64): Likewise. + (*mov_softfloat64): Likewise. + + Branch work168-tar, patch #11 from work168 branch + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-06-03 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work168-tar, patch #10 from work168 branch + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the
[gcc(refs/users/meissner/heads/work168-tar)] Add support for the TAR register.
https://gcc.gnu.org/g:f5177d70ff8945e98334be05bc706e133ec83cd3
commit f5177d70ff8945e98334be05bc706e133ec83cd3
Author: Michael Meissner
Date: Tue Jun 4 14:25:29 2024 -0400
Add support for the TAR register.
2024-06-04 Michael Meissner
gcc/
* config/rs6000/constraints.md (h constraint): Add TAR register to
the
documentation.
(wt constraint): New constraint.
* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Document
that we
do not explicitly add -mtar for power9.
(OTHER_POWER10_MASKS): Add -mtar.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.cc (rs6000_reg_names): Add TAR register
support.
(alt_reg_names): Likewise.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_debug_reg_global): Print the register class that wt maps
too.
(rs6000_init_hard_regno_mode_ok): Add TAR register support.
(rs6000_option_override_internal): Restrict -mtar to power9 and
above.
(rs6000_conditional_register_usage): Add TAR register support.
(print_operand): Likewise.
(rs6000_debugger_regno): Likewise.
(rs6000_opt_masks): Add support for -mtar.
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Add TAR register
support.
(FIXED_REGISTERS): Likewise.
(CALL_REALLY_USED_REGISTERS): Likewise.
(REG_ALLOC_ORDER): Likewise.
(enum reg_class): Likewise.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(enum r6000_reg_class_enum): Add support for the wt constraint.
* config/rs6000/rs6000.md (TAR_REGNO): New constant.
(mov_internal): Add TAR register support.
(call_indirect_nonlocal_sysv): Likewise.
(call_value_indirect_nonlocal_sysv): Likewise.
(call_indirect_aix): Likewise.
(call_value_indirect_aix): Likewise.
(call_indirect_elfv2): Likewise.
(call_indirect_pcrel): Likewise.
(call_value_indirect_elfv2): Likewise.
(call_value_indirect_pcrel): Likewise.
(*sibcall_indirect_nonlocal_sysv): Likewise.
(sibcall_value_indirect_nonlocal_sysv): Likewise.
(indirect_jump): Likewise.
(@indirect_jump_nospec): Likewise.
(@tablejump_insn_normal): Likewise.
(@tablejump_insn_nospec): Likewise.
* config/rs6000/rs6000.opt (-mtar): New option.
gcc/testsuite/
* gcc.target/powerpc/ppc-switch-1.c: Update test for the TAR
register.
* gcc.target/powerpc/pr51513.c: Likewise.
* gcc.target/powerpc/safe-indirect-jump-2.c: Likewise.
* gcc.target/powerpc/safe-indirect-jump-3.c: Likewise.
* gcc.target/powerpc/tar-register.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 5 ++-
gcc/config/rs6000/rs6000-cpus.def | 7 ++--
gcc/config/rs6000/rs6000.cc| 42 ++
gcc/config/rs6000/rs6000.h | 31 +---
gcc/config/rs6000/rs6000.md| 35 +-
gcc/config/rs6000/rs6000.opt | 4 +++
gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c| 4 +--
gcc/testsuite/gcc.target/powerpc/pr51513.c | 4 +--
.../gcc.target/powerpc/safe-indirect-jump-2.c | 2 +-
.../gcc.target/powerpc/safe-indirect-jump-3.c | 2 +-
gcc/testsuite/gcc.target/powerpc/tar-register.c| 34 ++
11 files changed, 126 insertions(+), 44 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 369a7b75042..14f0465d7ae 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -57,7 +57,7 @@
"@internal A compatibility alias for @code{wa}.")
(define_register_constraint "h" "SPECIAL_REGS"
- "@internal A special register (@code{vrsave}, @code{ctr}, or @code{lr}).")
+ "@internal A special register (@code{vrsave}, @code{ctr}, @code{lr} or
@code{tar}).")
(define_register_constraint "c" "CTR_REGS"
"The count register, @code{ctr}.")
@@ -91,6 +91,9 @@
"@internal Like @code{r}, if @option{-mpowerpc64} is used; otherwise,
@code{NO_REGS}.")
+(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
+ "The tar register, @code{tar}.")
+
(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
"@internal Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise,
@code{NO_REGS}.")
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index d625dbeb91f..37366d5e056 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -59,7 +59,8 @@
|
[gcc(refs/users/meissner/heads/work168-tar)] Restrict SPR to appropriate integer modes.
https://gcc.gnu.org/g:8f96a3df132b456f535b8c94bb436dca44eecc39
commit 8f96a3df132b456f535b8c94bb436dca44eecc39
Author: Michael Meissner
Date: Tue Jun 4 13:44:01 2024 -0400
Restrict SPR to appropriate integer modes.
In preparation for the patches to add support for the TAR register, I
restricted
the modes that special purpose registers (SPRs) could hold to be appropriate
sized scalar integers. I have discovered occasionally when GCC has run out
of
registers, it will use the SPRs to hold values instead of spilling them to
the
stack. The LR/CTR registers can hold 8/16/32-bit values and on 64-bit
systems,
they can also hold 64-bit values. The VRSAVE and VSCR registers can only
hold
32-bit values.
2024-06-04 Michael Meissner
gcc/
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Restrict
SPR registers to only hold scalar integer modes of an appropriate
size.
* config/rs6000/rs6000.md (movcc_): Remove alternatives that
move
values to/from the SPRs.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
(mov_softfloat): Likewise.
(mov_softfloat32): Likewise.
(mov_hardfloat64): Likewise.
(*mov_softfloat64): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.cc | 29 ++-
gcc/config/rs6000/rs6000.md | 117 +++-
2 files changed, 77 insertions(+), 69 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c5c4191127e..c2f8096beec 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1851,9 +1851,13 @@ static int
rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
{
int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
+ bool orig_complex_p = false;
if (COMPLEX_MODE_P (mode))
-mode = GET_MODE_INNER (mode);
+{
+ mode = GET_MODE_INNER (mode);
+ orig_complex_p = true;
+}
/* Vector pair modes need even/odd VSX register pairs. Only allow vector
registers. */
@@ -1935,6 +1939,29 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if (CA_REGNO_P (regno))
return mode == Pmode || mode == SImode;
+ /* Restrict SPR registers to only hold an appropriate sized integer mode. In
+ partciular, do not allow condition codes, complex values, or floating
+ point. VRSAVE and VSCR can only hold 32-bit values. */
+ switch (regno)
+{
+case VRSAVE_REGNO:
+case VSCR_REGNO:
+case LR_REGNO:
+case CTR_REGNO:
+ {
+ unsigned reg_size = ((regno == VRSAVE_REGNO || regno == VSCR_REGNO)
+? 4
+: UNITS_PER_WORD);
+
+ return (!orig_complex_p
+ && GET_MODE_SIZE (mode) <= reg_size
+ && SCALAR_INT_MODE_P (mode));
+ }
+
+default:
+ break;
+}
+
/* AltiVec only in AldyVec registers. */
if (ALTIVEC_REGNO_P (regno))
return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 44d38df56f1..e5d3cb286cb 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8119,9 +8119,9 @@
(define_insn "*movcc_"
[(set (match_operand:CC_any 0 "nonimmediate_operand"
- "=y,x,?y,y,r,r,r,r, r,*c*l,r,m")
+ "=y,x,?y,y,r,r,r,r,r,m")
(match_operand:CC_any 1 "general_operand"
- " y,r, r,O,x,y,r,I,*h, r,m,r"))]
+ " y,r, r,O,x,y,r,I,m,r"))]
"register_operand (operands[0], mode)
|| register_operand (operands[1], mode)"
"@
@@ -8133,8 +8133,6 @@
mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf000
mr %0,%1
li %0,%1
- mf%1 %0
- mt%0 %1
lwz%U1%X1 %0,%1
stw%U0%X0 %1,%0"
[(set_attr_alternative "type"
@@ -8148,11 +8146,9 @@
(const_string "mfcrf") (const_string "mfcr"))
(const_string "integer")
(const_string "integer")
- (const_string "mfjmpr")
- (const_string "mtjmpr")
(const_string "load")
(const_string "store")])
- (set_attr "length" "*,*,12,*,*,8,*,*,*,*,*,*")])
+ (set_attr "length" "*,*,12,*,*,8,*,*,*,*")])
;; For floating-point, we normally deal with the floating-point registers
;; unless -msoft-float is used. The sole exception is that parameter passing
@@ -8203,17 +8199,17 @@
;;
;; LWZ LFSLXSSP LXSSPX STFS STXSSP
;; STXSSPX STWXXLXOR LI FMRXSCPSGNDP
-;; MR MT MF NOPXXSPLTIDP
+;; MR XXSPLTIDP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa,m, wY,
Z, m, wa, !r,
[gcc(refs/users/meissner/heads/work168-vpair)] Merge commit 'refs/users/meissner/heads/work168-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work
https://gcc.gnu.org/g:08bee21b2c54356998a8a6b13ccacdab3c5d7bed commit 08bee21b2c54356998a8a6b13ccacdab3c5d7bed Merge: d5559afa6d7 df2bf7c417c Author: Michael Meissner Date: Mon Jun 3 15:41:43 2024 -0400 Merge commit 'refs/users/meissner/heads/work168-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work168-vpair Diff:
[gcc(refs/users/meissner/heads/work168-vpair)] Add ChangeLog.vpair and update REVISION.
https://gcc.gnu.org/g:d5559afa6d758649991e344fd3f8dadec85b36ce commit d5559afa6d758649991e344fd3f8dadec85b36ce Author: Michael Meissner Date: Mon Jun 3 15:19:33 2024 -0400 Add ChangeLog.vpair and update REVISION. 2024-06-03 Michael Meissner gcc/ * ChangeLog.vpair: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.vpair | 6 ++ gcc/REVISION| 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair new file mode 100644 index 000..652419b9285 --- /dev/null +++ b/gcc/ChangeLog.vpair @@ -0,0 +1,6 @@ + Branch work168-vpair, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 907cf1840d4..f85624e476c 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work168 branch +work168-vpair branch
[gcc/meissner/heads/work168-vpair] (8 commits) Merge commit 'refs/users/meissner/heads/work168-vpair' of g
The branch 'meissner/heads/work168-vpair' was updated to point to: 08bee21b2c5... Merge commit 'refs/users/meissner/heads/work168-vpair' of g It previously pointed to: df2bf7c417c... Add ChangeLog.vpair and update REVISION. Diff: Summary of changes (added commits): --- 08bee21... Merge commit 'refs/users/meissner/heads/work168-vpair' of g d5559af... Add ChangeLog.vpair and update REVISION. 96688e3... Update ChangeLog.* (*) 4570b2a... Add -mcpu=future tuning support. (*) af0dd67... Add -mcpu=future support. (*) 9b326e6... Add -mcpu=power11 tests. (*) d6934cf... Add -mcpu=power11 tuning support. (*) 0c32a4b... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work168-vpair' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work168-test)] Merge commit 'refs/users/meissner/heads/work168-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:be4271fff78cf3ece1aba6455678b4a2af68fae4 commit be4271fff78cf3ece1aba6455678b4a2af68fae4 Merge: 5881661e1cb 04d36fb909c Author: Michael Meissner Date: Mon Jun 3 15:40:41 2024 -0400 Merge commit 'refs/users/meissner/heads/work168-test' of git+ssh://gcc.gnu.org/git/gcc into me/work168-test Diff:
[gcc(refs/users/meissner/heads/work168-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:5881661e1cbe73d0388c84e5fbca5e6d0b905325 commit 5881661e1cbe73d0388c84e5fbca5e6d0b905325 Author: Michael Meissner Date: Mon Jun 3 15:21:59 2024 -0400 Add ChangeLog.test and update REVISION. 2024-06-03 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index 000..dc8d3ec0427 --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,6 @@ + Branch work168-test, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 907cf1840d4..a8cfc9ac52f 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work168 branch +work168-test branch
[gcc/meissner/heads/work168-test] (8 commits) Merge commit 'refs/users/meissner/heads/work168-test' of gi
The branch 'meissner/heads/work168-test' was updated to point to: be4271fff78... Merge commit 'refs/users/meissner/heads/work168-test' of gi It previously pointed to: 04d36fb909c... Add ChangeLog.test and update REVISION. Diff: Summary of changes (added commits): --- be4271f... Merge commit 'refs/users/meissner/heads/work168-test' of gi 5881661... Add ChangeLog.test and update REVISION. 96688e3... Update ChangeLog.* (*) 4570b2a... Add -mcpu=future tuning support. (*) af0dd67... Add -mcpu=future support. (*) 9b326e6... Add -mcpu=power11 tests. (*) d6934cf... Add -mcpu=power11 tuning support. (*) 0c32a4b... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work168-test' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work168-tar)] Merge commit 'refs/users/meissner/heads/work168-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work16
https://gcc.gnu.org/g:c59cb87745cc36d06e4496f8412cd46ccc0c0225 commit c59cb87745cc36d06e4496f8412cd46ccc0c0225 Merge: d9c5458502a 1fe49637b45 Author: Michael Meissner Date: Mon Jun 3 15:39:22 2024 -0400 Merge commit 'refs/users/meissner/heads/work168-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work168-tar Diff:
[gcc(refs/users/meissner/heads/work168-tar)] Add ChangeLog.tar and update REVISION.
https://gcc.gnu.org/g:d9c5458502ad8719e1e444e7fd0bcfbdbae096c7 commit d9c5458502ad8719e1e444e7fd0bcfbdbae096c7 Author: Michael Meissner Date: Mon Jun 3 15:20:22 2024 -0400 Add ChangeLog.tar and update REVISION. 2024-06-03 Michael Meissner gcc/ * ChangeLog.tar: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.tar | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar new file mode 100644 index 000..c512209738a --- /dev/null +++ b/gcc/ChangeLog.tar @@ -0,0 +1,6 @@ + Branch work168-tar, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 907cf1840d4..e9a2ce134aa 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work168 branch +work168-tar branch
[gcc/meissner/heads/work168-tar] (8 commits) Merge commit 'refs/users/meissner/heads/work168-tar' of git
The branch 'meissner/heads/work168-tar' was updated to point to: c59cb87745c... Merge commit 'refs/users/meissner/heads/work168-tar' of git It previously pointed to: 1fe49637b45... Add ChangeLog.tar and update REVISION. Diff: Summary of changes (added commits): --- c59cb87... Merge commit 'refs/users/meissner/heads/work168-tar' of git d9c5458... Add ChangeLog.tar and update REVISION. 96688e3... Update ChangeLog.* (*) 4570b2a... Add -mcpu=future tuning support. (*) af0dd67... Add -mcpu=future support. (*) 9b326e6... Add -mcpu=power11 tests. (*) d6934cf... Add -mcpu=power11 tuning support. (*) 0c32a4b... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work168-tar' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work168-dmf)] Merge commit 'refs/users/meissner/heads/work168-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work16
https://gcc.gnu.org/g:cc617eb46ed709a423a1db7ca897420c84a323ea commit cc617eb46ed709a423a1db7ca897420c84a323ea Merge: e7d9f79b702 9db160a7bb0 Author: Michael Meissner Date: Mon Jun 3 15:38:15 2024 -0400 Merge commit 'refs/users/meissner/heads/work168-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work168-dmf Diff:
[gcc(refs/users/meissner/heads/work168-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:e7d9f79b70229381da4b613406c3d668146135a9 commit e7d9f79b70229381da4b613406c3d668146135a9 Author: Michael Meissner Date: Mon Jun 3 15:18:32 2024 -0400 Add ChangeLog.dmf and update REVISION. 2024-06-03 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index 000..4b46c2505ab --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,6 @@ + Branch work168-dmf, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 907cf1840d4..89b2c9424a0 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work168 branch +work168-dmf branch
[gcc/meissner/heads/work168-dmf] (8 commits) Merge commit 'refs/users/meissner/heads/work168-dmf' of git
The branch 'meissner/heads/work168-dmf' was updated to point to: cc617eb46ed... Merge commit 'refs/users/meissner/heads/work168-dmf' of git It previously pointed to: 9db160a7bb0... Add ChangeLog.dmf and update REVISION. Diff: Summary of changes (added commits): --- cc617eb... Merge commit 'refs/users/meissner/heads/work168-dmf' of git e7d9f79... Add ChangeLog.dmf and update REVISION. 96688e3... Update ChangeLog.* (*) 4570b2a... Add -mcpu=future tuning support. (*) af0dd67... Add -mcpu=future support. (*) 9b326e6... Add -mcpu=power11 tests. (*) d6934cf... Add -mcpu=power11 tuning support. (*) 0c32a4b... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work168-dmf' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work168-bugs)] Merge commit 'refs/users/meissner/heads/work168-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:550fa669fb6e683636895454d6c04a39dd5b5cdf commit 550fa669fb6e683636895454d6c04a39dd5b5cdf Merge: 2b3a2e26ba1 b49e6062b90 Author: Michael Meissner Date: Mon Jun 3 15:36:42 2024 -0400 Merge commit 'refs/users/meissner/heads/work168-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work168-bugs Diff:
[gcc(refs/users/meissner/heads/work168-bugs)] Add ChangeLog.bugs and update REVISION.
https://gcc.gnu.org/g:2b3a2e26ba1e2d743068c3391dab62398dc0d847 commit 2b3a2e26ba1e2d743068c3391dab62398dc0d847 Author: Michael Meissner Date: Mon Jun 3 15:21:10 2024 -0400 Add ChangeLog.bugs and update REVISION. 2024-06-03 Michael Meissner gcc/ * ChangeLog.bugs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.bugs | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs new file mode 100644 index 000..acfe9a8ee54 --- /dev/null +++ b/gcc/ChangeLog.bugs @@ -0,0 +1,6 @@ + Branch work168-bugs, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 907cf1840d4..1f770ce245a 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work168 branch +work168-bugs branch
[gcc/meissner/heads/work168-bugs] (8 commits) Merge commit 'refs/users/meissner/heads/work168-bugs' of gi
The branch 'meissner/heads/work168-bugs' was updated to point to: 550fa669fb6... Merge commit 'refs/users/meissner/heads/work168-bugs' of gi It previously pointed to: b49e6062b90... Add ChangeLog.bugs and update REVISION. Diff: Summary of changes (added commits): --- 550fa66... Merge commit 'refs/users/meissner/heads/work168-bugs' of gi 2b3a2e2... Add ChangeLog.bugs and update REVISION. 96688e3... Update ChangeLog.* (*) 4570b2a... Add -mcpu=future tuning support. (*) af0dd67... Add -mcpu=future support. (*) 9b326e6... Add -mcpu=power11 tests. (*) d6934cf... Add -mcpu=power11 tuning support. (*) 0c32a4b... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work168-bugs' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work168)] Update ChangeLog.*
https://gcc.gnu.org/g:96688e3d23cfc74ad1facb0347fbb75875b03825 commit 96688e3d23cfc74ad1facb0347fbb75875b03825 Author: Michael Meissner Date: Mon Jun 3 15:34:44 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 185 - 1 file changed, 184 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 91bc039d346..3eac39146fb 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,6 +1,189 @@ + Branch work168, patch #11 + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-05-23 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work168, patch #10 + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. + +This patch allows GCC to be configured with the --with-cpu=future and +--with-tune=future options. + +This patch passes -mfuture to the assembler if the user uses -mcpu=future. + +2024-05-23 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. + (POWERPC_MASKS): Add future isa bit. + (power11 cpu): Add future definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add future. + * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. + + Branch work168, patch #3 + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the appropriate option for +supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). + +2024-05-23 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + * lib/target-supports.exp (check_effective_target_power11_ok): Add new + effective target. + + Branch work168, patch #2 + +Add -mcpu=power11 tuning support. + +This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10. + +2024-05-23 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add power11 as an + alternative to power10. + + Branch work168, patch #1 + +Add -mcpu=power11 support. + +This patch adds the power11 option to the -mcpu= and -mtune= switches. + +This patch treats the power11 like a power10 in terms of costs and reassociation +width. + +This patch issues a ".machine power11" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR11 if the user uses -mcpu=power11. + +This patch allows GCC to be configured with the --with-cpu=power11 and +--with-tune=power11 options. + +This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. + +This patch adds support for using "power11" in the __builtin_cpu_is built-in +function. + +2024-05-23 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC):
[gcc(refs/users/meissner/heads/work168)] Add -mcpu=future tuning support.
https://gcc.gnu.org/g:4570b2afd304efb7efc411a1008b842624926784 commit 4570b2afd304efb7efc411a1008b842624926784 Author: Michael Meissner Date: Mon Jun 3 15:32:32 2024 -0400 Add -mcpu=future tuning support. This patch makes -mtune=future use the same tuning decision as -mtune=power11. 2024-06-03 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add future as an alterntive to power10 and power11. Diff: --- gcc/config/rs6000/power10.md | 145 ++- 1 file changed, 73 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index 90312643858..1ec1bef0726 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,5 @@ -;; Scheduling description for the IBM POWER10 and POWER11 processors. +;; Scheduling description for the IBM POWER10 and POWER11 processors as well as +;; potential future processors. ;; Copyright (C) 2020-2024 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -97,12 +98,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +111,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +125,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +133,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +149,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +179,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +192,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") ; Update
[gcc(refs/users/meissner/heads/work168)] Add -mcpu=future support.
https://gcc.gnu.org/g:af0dd67add5488fcb4b1955664df35fdc68b0e79
commit af0dd67add5488fcb4b1955664df35fdc68b0e79
Author: Michael Meissner
Date: Mon Jun 3 15:31:21 2024 -0400
Add -mcpu=future support.
This patch adds the future option to the -mcpu= and -mtune= switches.
This patch treats the future like a power11 in terms of costs and
reassociation
width.
This patch issues a ".machine future" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future.
This patch allows GCC to be configured with the --with-cpu=future and
--with-tune=future options.
This patch passes -mfuture to the assembler if the user uses -mcpu=future.
2024-06-03 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR_FUTURE if -mcpu=future.
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New
define.
(POWERPC_MASKS): Add future isa bit.
(power11 cpu): Add future definition.
* config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future
processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
future
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add future.
* config/rs6000/rs6000.opt (-mpower11): Add internal future ISA
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mcpu=future.
Diff:
---
gcc/config.gcc | 4 ++--
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 30 ++
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 +++
gcc/doc/invoke.texi | 2 +-
15 files changed, 48 insertions(+), 13 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 1364bc7b361..b297f68dad2 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -534,7 +534,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
- | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xpower1[01] | xfuture | xpower6x | xrs64a | xcell | xa2 |
xe500mc64 \
| xe5500 | xe6500)
cpu_is_64bit=yes
;;
@@ -5623,7 +5623,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power1[01] | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x |
future \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 41037b3852d..570ddcc451d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b4..242ca94bd06 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {
[gcc(refs/users/meissner/heads/work168)] Add -mcpu=power11 tests.
https://gcc.gnu.org/g:9b326e60cfba8bdcfb9dbbf7b749f07aa8aaa780
commit 9b326e60cfba8bdcfb9dbbf7b749f07aa8aaa780
Author: Michael Meissner
Date: Mon Jun 3 15:29:37 2024 -0400
Add -mcpu=power11 tests.
This patch adds some simple tests for -mcpu=power11 support. In order to
run
these tests, you need an assembler that supports the appropriate option for
supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under
AIX).
2024-06-03 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/power11-1.c: New test.
* gcc.target/powerpc/power11-2.c: Likewise.
* gcc.target/powerpc/power11-3.c: Likewise.
* lib/target-supports.exp (check_effective_target_power11_ok): Add
new
effective target.
Diff:
---
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +
gcc/testsuite/gcc.target/powerpc/power11-2.c | 20
gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++
gcc/testsuite/lib/target-supports.exp| 17 +
4 files changed, 60 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c
b/gcc/testsuite/gcc.target/powerpc/power11-1.c
new file mode 100644
index 000..6a2e802eedf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=power11. */
+
+#ifndef _ARCH_PWR11
+#error "-mcpu=power11 is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c
b/gcc/testsuite/gcc.target/powerpc/power11-2.c
new file mode 100644
index 000..7b9904c1d29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the power11 target via a target attribute. */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c
b/gcc/testsuite/gcc.target/powerpc/power11-3.c
new file mode 100644
index 000..9b2d643cc0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Check if we can set the power11 target via a target_clones attribute. */
+
+__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index 836545b4e11..9305d63aacc 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7059,6 +7059,23 @@ proc check_effective_target_power10_ok { } {
}
}
+# Return 1 if this is a PowerPC target supporting -mcpu=power11.
+
+proc check_effective_target_power11_ok { } {
+if { ([istarget powerpc*-*-*]) } {
+ return [check_no_compiler_messages power11_ok object {
+ int main (void) {
+ #ifndef _ARCH_PWR11
+ #error "-mcpu=power11 is not supported"
+ #endif
+ return 0;
+ }
+ } "-mcpu=power11"]
+} else {
+ return 0
+}
+}
+
# Return 1 if this is a PowerPC target supporting -mfloat128 via either
# software emulation on power7/power8 systems or hardware support on power9.
[gcc(refs/users/meissner/heads/work168)] Add -mcpu=power11 tuning support.
https://gcc.gnu.org/g:d6934cf7cac96e99de212b8abfd74c92b5081563 commit d6934cf7cac96e99de212b8abfd74c92b5081563 Author: Michael Meissner Date: Mon Jun 3 15:28:04 2024 -0400 Add -mcpu=power11 tuning support. This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10. 2024-06-03 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add power11 as an alternative to power10. Diff: --- gcc/config/rs6000/power10.md | 144 +-- 1 file changed, 72 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index fcc2199ab29..90312643858 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,4 @@ -;; Scheduling description for the IBM POWER10 processor. +;; Scheduling description for the IBM POWER10 and POWER11 processors. ;; Copyright (C) 2020-2024 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -97,12 +97,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +110,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +124,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +132,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +148,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +178,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +191,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle latency for updated addr reg (define_insn_reservation "power10-store-update" 2 (and (eq_attr "type" "store,fpstore") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11"))
[gcc(refs/users/meissner/heads/work168)] Add -mcpu=power11 support.
https://gcc.gnu.org/g:0c32a4bffcca0fc4ea3afbb8c7e1633197aa127f
commit 0c32a4bffcca0fc4ea3afbb8c7e1633197aa127f
Author: Michael Meissner
Date: Mon Jun 3 15:27:32 2024 -0400
Add -mcpu=power11 support.
This patch adds the power11 option to the -mcpu= and -mtune= switches.
This patch treats the power11 like a power10 in terms of costs and
reassociation
width.
This patch issues a ".machine power11" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR11 if the user uses -mcpu=power11.
This patch allows GCC to be configured with the --with-cpu=power11 and
--with-tune=power11 options.
This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11.
This patch adds support for using "power11" in the __builtin_cpu_is built-in
function.
2024-06-03 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define.
* config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR11 if -mcpu=power11.
* config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New
define.
(POWERPC_MASKS): Add power11 isa bit.
(power11 cpu): Add power11 definition.
* config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11
processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
power11
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add power11.
* config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mcpu=power11.
Diff:
---
gcc/config.gcc | 6 --
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/ppc-auxv.h| 3 +--
gcc/config/rs6000/rs6000-builtin.cc | 1 +
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 32
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 +++
gcc/doc/invoke.texi | 5 +++--
17 files changed, 56 insertions(+), 16 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index e500ba63e32..1364bc7b361 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -533,7 +533,9 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+ xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
+ | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xe5500 | xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5621,7 +5623,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power10 | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 24bc301e37d..41037b3852d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
[gcc(refs/users/meissner/heads/work168-orig)] Add REVISION.
https://gcc.gnu.org/g:059c11812d4007ab56197f9f90cabd06ed641bd9 commit 059c11812d4007ab56197f9f90cabd06ed641bd9 Author: Michael Meissner Date: Mon Jun 3 15:22:54 2024 -0400 Add REVISION. 2024-06-03 Michael Meissner gcc/ * REVISION: New file for branch. Diff: --- gcc/REVISION | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index 000..4ece1134f34 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work168-orig branch
[gcc] Created branch 'meissner/heads/work168-orig' in namespace 'refs/users'
The branch 'meissner/heads/work168-orig' was created in namespace 'refs/users' pointing to: f3d6d60d2ae... Implement wrap-around arithmetics in DWARF expressions
[gcc(refs/users/meissner/heads/work168-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:04d36fb909cf98d58f3619b4d57288ed9e47887c commit 04d36fb909cf98d58f3619b4d57288ed9e47887c Author: Michael Meissner Date: Mon Jun 3 15:21:59 2024 -0400 Add ChangeLog.test and update REVISION. 2024-06-03 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index 000..dc8d3ec0427 --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,6 @@ + Branch work168-test, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 907cf1840d4..a8cfc9ac52f 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work168 branch +work168-test branch
[gcc] Created branch 'meissner/heads/work168-test' in namespace 'refs/users'
The branch 'meissner/heads/work168-test' was created in namespace 'refs/users' pointing to: 923cac0672c... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work168-bugs)] Add ChangeLog.bugs and update REVISION.
https://gcc.gnu.org/g:b49e6062b90f39b31cbf35a8860d20c856af51b1 commit b49e6062b90f39b31cbf35a8860d20c856af51b1 Author: Michael Meissner Date: Mon Jun 3 15:21:10 2024 -0400 Add ChangeLog.bugs and update REVISION. 2024-06-03 Michael Meissner gcc/ * ChangeLog.bugs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.bugs | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs new file mode 100644 index 000..acfe9a8ee54 --- /dev/null +++ b/gcc/ChangeLog.bugs @@ -0,0 +1,6 @@ + Branch work168-bugs, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 907cf1840d4..1f770ce245a 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work168 branch +work168-bugs branch
[gcc] Created branch 'meissner/heads/work168-bugs' in namespace 'refs/users'
The branch 'meissner/heads/work168-bugs' was created in namespace 'refs/users' pointing to: 923cac0672c... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work168-tar)] Add ChangeLog.tar and update REVISION.
https://gcc.gnu.org/g:1fe49637b4527009446e87b5fd20bf3f96293772 commit 1fe49637b4527009446e87b5fd20bf3f96293772 Author: Michael Meissner Date: Mon Jun 3 15:20:22 2024 -0400 Add ChangeLog.tar and update REVISION. 2024-06-03 Michael Meissner gcc/ * ChangeLog.tar: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.tar | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar new file mode 100644 index 000..c512209738a --- /dev/null +++ b/gcc/ChangeLog.tar @@ -0,0 +1,6 @@ + Branch work168-tar, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 907cf1840d4..e9a2ce134aa 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work168 branch +work168-tar branch
[gcc] Created branch 'meissner/heads/work168-tar' in namespace 'refs/users'
The branch 'meissner/heads/work168-tar' was created in namespace 'refs/users' pointing to: 923cac0672c... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work168-vpair)] Add ChangeLog.vpair and update REVISION.
https://gcc.gnu.org/g:df2bf7c417ca6abf54d3ed7909ed519f039789e1 commit df2bf7c417ca6abf54d3ed7909ed519f039789e1 Author: Michael Meissner Date: Mon Jun 3 15:19:33 2024 -0400 Add ChangeLog.vpair and update REVISION. 2024-06-03 Michael Meissner gcc/ * ChangeLog.vpair: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.vpair | 6 ++ gcc/REVISION| 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair new file mode 100644 index 000..652419b9285 --- /dev/null +++ b/gcc/ChangeLog.vpair @@ -0,0 +1,6 @@ + Branch work168-vpair, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 907cf1840d4..f85624e476c 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work168 branch +work168-vpair branch
[gcc] Created branch 'meissner/heads/work168-vpair' in namespace 'refs/users'
The branch 'meissner/heads/work168-vpair' was created in namespace 'refs/users' pointing to: 923cac0672c... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work168-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:9db160a7bb059fa62f86e048abd4c774baf631b2 commit 9db160a7bb059fa62f86e048abd4c774baf631b2 Author: Michael Meissner Date: Mon Jun 3 15:18:32 2024 -0400 Add ChangeLog.dmf and update REVISION. 2024-06-03 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index 000..4b46c2505ab --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,6 @@ + Branch work168-dmf, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 907cf1840d4..89b2c9424a0 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work168 branch +work168-dmf branch
[gcc] Created branch 'meissner/heads/work168-dmf' in namespace 'refs/users'
The branch 'meissner/heads/work168-dmf' was created in namespace 'refs/users' pointing to: 923cac0672c... Add ChangeLog.meissner and REVISION.
[gcc(refs/users/meissner/heads/work168)] Add ChangeLog.meissner and REVISION.
https://gcc.gnu.org/g:923cac0672c565d5ce61f148992dbd7cadf594ae commit 923cac0672c565d5ce61f148992dbd7cadf594ae Author: Michael Meissner Date: Mon Jun 3 15:17:35 2024 -0400 Add ChangeLog.meissner and REVISION. 2024-06-03 Michael Meissner gcc/ * REVISION: New file for branch. * ChangeLog.meissner: New file. gcc/c-family/ * ChangeLog.meissner: New file. gcc/c/ * ChangeLog.meissner: New file. gcc/cp/ * ChangeLog.meissner: New file. gcc/fortran/ * ChangeLog.meissner: New file. gcc/testsuite/ * ChangeLog.meissner: New file. libgcc/ * ChangeLog.meissner: New file. Diff: --- gcc/ChangeLog.meissner | 6 ++ gcc/REVISION | 1 + gcc/c-family/ChangeLog.meissner | 6 ++ gcc/c/ChangeLog.meissner | 6 ++ gcc/cp/ChangeLog.meissner| 6 ++ gcc/fortran/ChangeLog.meissner | 6 ++ gcc/testsuite/ChangeLog.meissner | 6 ++ libgcc/ChangeLog.meissner| 6 ++ libstdc++-v3/ChangeLog.meissner | 6 ++ 9 files changed, 49 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner new file mode 100644 index 000..91bc039d346 --- /dev/null +++ b/gcc/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work168, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index 000..907cf1840d4 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work168 branch diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner new file mode 100644 index 000..91bc039d346 --- /dev/null +++ b/gcc/c-family/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work168, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner new file mode 100644 index 000..91bc039d346 --- /dev/null +++ b/gcc/c/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work168, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner new file mode 100644 index 000..91bc039d346 --- /dev/null +++ b/gcc/cp/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work168, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner new file mode 100644 index 000..91bc039d346 --- /dev/null +++ b/gcc/fortran/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work168, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner new file mode 100644 index 000..91bc039d346 --- /dev/null +++ b/gcc/testsuite/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work168, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner new file mode 100644 index 000..91bc039d346 --- /dev/null +++ b/libgcc/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work168, baseline + +2024-06-03 Michael Meissner + + Clone branch + diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner new file mode 100644 index 000..91bc039d346 --- /dev/null +++ b/libstdc++-v3/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work168, baseline + +2024-06-03 Michael Meissner + + Clone branch +
[gcc] Created branch 'meissner/heads/work168' in namespace 'refs/users'
The branch 'meissner/heads/work168' was created in namespace 'refs/users' pointing to: f3d6d60d2ae... Implement wrap-around arithmetics in DWARF expressions
[gcc(refs/users/meissner/heads/work167-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:f234f12040d1eb579c2de08a0fe2764cd6f87f0a commit f234f12040d1eb579c2de08a0fe2764cd6f87f0a Author: Michael Meissner Date: Thu May 30 08:36:03 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 26 ++ 1 file changed, 26 insertions(+) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index 34207e707f6..9a2d05060e4 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,3 +1,29 @@ + Branch work167-tar, patch #207 + +Add wt to move constraints. + +2024-05-30 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.md (mov_internal): Add wt to various move + constraints to support -m*spr debug switches. + (movcc_): Likewise. + (movsf_hardfloat): Likewise. + (movsd_hardfloat): Likewise. + (mov_hardfloat64): Likewise. + (mov_softfloat64): Likewise. + (*call_indirect_nonlocal_sysv): Add wt to call constraints. + (call_value_indirect_nonlocal_sysv): Likewise. + (call_indirect_aix): Likewise. + (call_value_indirect_aix): Likewise. + (call_indirect_elfv2): Likewise. + (call_indirect_pcrel): Likewise. + (call_value_indirect_elfv2): Likewise. + (call_value_indirect_pcrel): Likewise. + (sibcall_indirect_nonlocal_sysv): Likewise. + Branch work167-tar, patch #206 Add more SPR register debug options.
[gcc(refs/users/meissner/heads/work167-tar)] Add wt to move constraints.
https://gcc.gnu.org/g:6f640cba222d198bcd5a523df621e6d12b7e3901 commit 6f640cba222d198bcd5a523df621e6d12b7e3901 Author: Michael Meissner Date: Thu May 30 08:34:30 2024 -0400 Add wt to move constraints. 2024-05-30 Michael Meissner gcc/ * config/rs6000/rs6000.md (mov_internal): Add wt to various move constraints to support -m*spr debug switches. (movcc_): Likewise. (movsf_hardfloat): Likewise. (movsd_hardfloat): Likewise. (mov_hardfloat64): Likewise. (mov_softfloat64): Likewise. (*call_indirect_nonlocal_sysv): Add wt to call constraints. (call_value_indirect_nonlocal_sysv): Likewise. (call_indirect_aix): Likewise. (call_value_indirect_aix): Likewise. (call_indirect_elfv2): Likewise. (call_indirect_pcrel): Likewise. (call_value_indirect_elfv2): Likewise. (call_value_indirect_pcrel): Likewise. (sibcall_indirect_nonlocal_sysv): Likewise. Diff: --- gcc/config/rs6000/rs6000.md | 34 +- 1 file changed, 17 insertions(+), 17 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 28f8ebee738..ba22a36b82e 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8069,7 +8069,7 @@ [(set (match_operand:QHI 0 "nonimmediate_operand" "=r,r, wa,m, ?Z,r, wa,wa,wa,v, ?v,r, -wa,r, *c*l, *h") +wa,r, *wt*c*l, *h") (match_operand:QHI 1 "input_operand" "r, m, ?Z,r, wa,i, wa,O, wM,wB,wS,wa, @@ -8120,7 +8120,7 @@ (define_insn "*movcc_" [(set (match_operand:CC_any 0 "nonimmediate_operand" - "=y,x,?y,y,r,r,r,r, r,*c*l,r,m") + "=y,x,?y,y,r,r,r,r, r,*wt*c*l,r,m") (match_operand:CC_any 1 "general_operand" " y,r, r,O,x,y,r,I,*h, r,m,r"))] "register_operand (operands[0], mode) @@ -8210,7 +8210,7 @@ [(set (match_operand:SF 0 "nonimmediate_operand" "=!r, f, v, wa,m, wY, Z, m, wa, !r,f, wa, - !r,*c*l, !r, *h,wa") + !r,*wt*c*l, !r, *h,wa") (match_operand:SF 1 "input_operand" "m, m, wY, Z, f, v, wa,r, j, j, f, wa, @@ -8256,7 +8256,7 @@ (define_insn "movsd_hardfloat" [(set (match_operand:SD 0 "nonimmediate_operand" "=!r, d, m, ?Z,?d,?r, - f, !r,*c*l, !r,*h") + f, !r,*wt*c*l, !r,*h") (match_operand:SD 1 "input_operand" "m, ?Z,r, wx,r, d, f, r, r, *h,0"))] @@ -8286,7 +8286,7 @@ ;; LIS G-const. F/n-const NOP (define_insn "*mov_softfloat" [(set (match_operand:FMOVE32 0 "nonimmediate_operand" - "=r, *c*l, r, r, m, r, + "=r, *wt*c*l, r, r, m, r, r, r, r, *h") (match_operand:FMOVE32 1 "input_operand" @@ -8600,7 +8600,7 @@ [(set (match_operand:FMOVE64 0 "nonimmediate_operand" "=m, d, d, , wY, ,Z, , , !r, - YZ, r, !r, *c*l, !r, + YZ, r, !r, *wt*c*l,!r, *h, r, , wa") (match_operand:FMOVE64 1 "input_operand" "d, m, d, wY, , @@ -8652,7 +8652,7 @@ (define_insn "*mov_softfloat64" [(set (match_operand:FMOVE64 0 "nonimmediate_operand" - "=Y, r, r, *c*l, r, r, + "=Y, r, r, *wt*c*l, r, r, r, r, *h") (match_operand:FMOVE64 1 "input_operand" @@ -11501,7 +11501,7 @@ ;; which indicates how to set cr1 (define_insn "*call_indirect_nonlocal_sysv" - [(call (mem:SI (match_operand:P 0 "indirect_call_operand" "c,*l,X")) + [(call (mem:SI (match_operand:P 0 "indirect_call_operand" "wtc,*l,X")) (match_operand 1)) (use (match_operand:SI 2 "immediate_operand" "n,n,n")) (clobber (reg:P LR_REGNO))] @@ -11571,7 +11571,7 @@ (define_insn "*call_value_indirect_nonlocal_sysv" [(set (match_operand 0 "" "") - (call (mem:SI (match_operand:P 1
[gcc(refs/users/meissner/heads/work167-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:929c37f970cd75190f1b7af30c33e422c2a4952c commit 929c37f970cd75190f1b7af30c33e422c2a4952c Author: Michael Meissner Date: Tue May 28 17:36:48 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 16 1 file changed, 16 insertions(+) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index 3b2a674be1d..34207e707f6 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,3 +1,19 @@ + Branch work167-tar, patch #206 + +Add more SPR register debug options. + +2024-05-28 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add more + debug options for seeing what modes get stored in SPR registers. + * config/rs6000/rs6000.opt (-msispr): New SPR mode debut option. + (-mhispr): Likewise. + (-mqispr): Likewise.): Likewise. + (-msfspr): Likewise. + (-mdfspr): Likewise. + Branch work167-tar, patch #205 Fix test for TAR register.
[gcc(refs/users/meissner/heads/work167-tar)] Add more SPR register debug options.
https://gcc.gnu.org/g:309a32739e2d075bd62bf6767295acef596fe16c
commit 309a32739e2d075bd62bf6767295acef596fe16c
Author: Michael Meissner
Date: Tue May 28 17:23:23 2024 -0400
Add more SPR register debug options.
2024-05-28 Michael Meissner
gcc/
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add
more
debug options for seeing what modes get stored in SPR registers.
* config/rs6000/rs6000.opt (-msispr): New SPR mode debut option.
(-mhispr): Likewise.
(-mqispr): Likewise.): Likewise.
(-msfspr): Likewise.
(-mdfspr): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.cc | 30 +++---
gcc/config/rs6000/rs6000.opt | 20
2 files changed, 43 insertions(+), 7 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c6fb978977c..9a7b4cc1138 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1959,16 +1959,32 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if (GET_MODE_CLASS (mode) == MODE_CC)
return TARGET_CCSPR != 0;
- if (SCALAR_FLOAT_MODE_P (mode))
- return TARGET_FPSPR != 0;
+ switch (mode)
+ {
+ case E_QImode:
+ return (TARGET_INTSPR || TARGET_QISPR);
- if (!SCALAR_INT_MODE_P (mode))
- return false;
+ case E_HImode:
+ return (TARGET_INTSPR || TARGET_HISPR);
- if (TARGET_INTSPR)
- return true;
+ case E_SImode:
+ return (TARGET_INTSPR || TARGET_SISPR || reg_size == 4);
+
+ case E_DImode:
+ return (reg_size == 8);
+
+ case E_SFmode:
+ case E_SDmode:
+ return (TARGET_FPSPR || TARGET_SFSPR);
- return GET_MODE_SIZE (mode) == reg_size;
+ case E_DFmode:
+ case E_DDmode:
+ return (TARGET_FPSPR || TARGET_DFSPR);
+
+ default:
+ break;
+ }
+ return false;
}
default:
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 0384b92344f..7a0b52ab6e1 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -638,6 +638,18 @@ mintspr
Target Undocumented Var(TARGET_INTSPR) Init(0) Save
Allow (do not allow) small integers in SPR registers.
+msispr
+Target Undocumented Var(TARGET_SISPR) Init(0) Save
+Allow (do not allow) SImode in SPR registers.
+
+mhispr
+Target Undocumented Var(TARGET_HISPR) Init(0) Save
+Allow (do not allow) HImode in SPR registers.
+
+mqispr
+Target Undocumented Var(TARGET_QISPR) Init(0) Save
+Allow (do not allow) QImode in SPR registers.
+
mccspr
Target Undocumented Var(TARGET_CCSPR) Init(0) Save
Allow (do not allow) condition codes in SPR registers.
@@ -646,6 +658,14 @@ mfpspr
Target Undocumented Var(TARGET_FPSPR) Init(0) Save
Allow (do not allow) floating point in SPR registers.
+msfspr
+Target Undocumented Var(TARGET_SFSPR) Init(0) Save
+Allow (do not allow) SFmode in SPR registers.
+
+mdfspr
+Target Undocumented Var(TARGET_DFSPR) Init(0) Save
+Allow (do not allow) DFmode in SPR registers.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
[gcc(refs/users/meissner/heads/work167-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:1182736214c4653d481c909be58e9c53e2308f08 commit 1182736214c4653d481c909be58e9c53e2308f08 Author: Michael Meissner Date: Sat May 25 02:12:00 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 11 +++ 1 file changed, 11 insertions(+) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index 5dde9431641..3b2a674be1d 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,3 +1,14 @@ + Branch work167-tar, patch #205 + +Fix test for TAR register. + +2024-05-25 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/safe-indirect-jump-2.c: Fix test for generating the + TAR register. + Branch work167-tar, patch #204 Add -mccspr and -mfpspr
[gcc(refs/users/meissner/heads/work167-tar)] Fix test for TAR register.
https://gcc.gnu.org/g:b6efbea361aac79bcc9a28f67a20bea8db2b74e3
commit b6efbea361aac79bcc9a28f67a20bea8db2b74e3
Author: Michael Meissner
Date: Sat May 25 02:08:31 2024 -0400
Fix test for TAR register.
2024-05-25 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/safe-indirect-jump-2.c: Fix test for
generating the
TAR register.
Diff:
---
gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c
b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c
index d6fc6a3e0b7..791537921c8 100644
--- a/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c
+++ b/gcc/testsuite/gcc.target/powerpc/safe-indirect-jump-2.c
@@ -28,5 +28,5 @@ int foo (int x)
}
/* { dg-final { scan-assembler "crset" } } */
-/* { dg-final { scan-assembler "beqctr-" } } */
+/* { dg-final { scan-assembler "beq\(ctr\|tar\)-" } } */
/* { dg-final { scan-assembler {b \$} } } */
[gcc(refs/users/meissner/heads/work167-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:baa082e5aa0ab8bc2aa347ed0234eeb795367a43 commit baa082e5aa0ab8bc2aa347ed0234eeb795367a43 Author: Michael Meissner Date: Fri May 24 23:19:22 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 20 1 file changed, 20 insertions(+) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index 8141a355c54..5dde9431641 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,3 +1,23 @@ + Branch work167-tar, patch #204 + +Add -mccspr and -mfpspr + +2024-05-24 Michael Meissner + + * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add + support for -mccspr and -mfpspr debug switches + * config/rs6000/rs6000.md (movcc_): Add spr support back in. + (movsf_hardfloat): Likewise. + (movsd_hardfloat): Likewise. + (mov_softfloat): Likewise. + (mov_softfloat32): Likewise. + (ov_hardfloat64): Likewise. + (mov_softfloat64): Likewise. + (indirect_jump): Add TAR register support. + (@indirect_jump_nospec): Likewise. + * config/rs6000/rs6000.opt (-mccspr): New switch. + (-mfpspr): Likewise. + Branch work167-tar, patch #203 Add -mintspr.
[gcc(refs/users/meissner/heads/work167-tar)] Add -mccspr and -mfpspr
https://gcc.gnu.org/g:d5fdd314b266f9830ab28db14db7d0aa3f59f424
commit d5fdd314b266f9830ab28db14db7d0aa3f59f424
Author: Michael Meissner
Date: Fri May 24 23:15:34 2024 -0400
Add -mccspr and -mfpspr
2024-05-24 Michael Meissner
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add
support for -mccspr and -mfpspr debug switches
* config/rs6000/rs6000.md (movcc_): Add spr support back in.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
(mov_softfloat): Likewise.
(mov_softfloat32): Likewise.
(ov_hardfloat64): Likewise.
(mov_softfloat64): Likewise.
(indirect_jump): Add TAR register support.
(@indirect_jump_nospec): Likewise.
* config/rs6000/rs6000.opt (-mccspr): New switch.
(-mfpspr): Likewise.
Diff:
---
gcc/config/rs6000/rs6000.cc | 31
gcc/config/rs6000/rs6000.md | 118 ++-
gcc/config/rs6000/rs6000.opt | 8 +++
3 files changed, 101 insertions(+), 56 deletions(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index fa330c2a4b1..c6fb978977c 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1943,20 +1943,33 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
SPR. */
switch (regno)
{
- /* 32-bit registers. */
case VRSAVE_REGNO:
case VSCR_REGNO:
- return (!orig_complex_p && mode == SImode);
-
- /* Registers that hold addresses. */
case LR_REGNO:
case CTR_REGNO:
case TAR_REGNO:
- return (!orig_complex_p
- && (mode == Pmode
- || (TARGET_INTSPR
- && SCALAR_INT_MODE_P (mode)
- && GET_MODE_SIZE (mode) <= UNITS_PER_WORD)));
+ {
+ unsigned reg_size = ((regno == VRSAVE_REGNO || regno == VSCR_REGNO)
+? 4
+: UNITS_PER_WORD);
+
+ if (orig_complex_p || GET_MODE_SIZE (mode) > reg_size)
+ return false;
+
+ if (GET_MODE_CLASS (mode) == MODE_CC)
+ return TARGET_CCSPR != 0;
+
+ if (SCALAR_FLOAT_MODE_P (mode))
+ return TARGET_FPSPR != 0;
+
+ if (!SCALAR_INT_MODE_P (mode))
+ return false;
+
+ if (TARGET_INTSPR)
+ return true;
+
+ return GET_MODE_SIZE (mode) == reg_size;
+ }
default:
break;
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index b5dc0719a88..28f8ebee738 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -8120,9 +8120,9 @@
(define_insn "*movcc_"
[(set (match_operand:CC_any 0 "nonimmediate_operand"
- "=y,x,?y,y,r,r,r,r,r,m")
+ "=y,x,?y,y,r,r,r,r, r,*c*l,r,m")
(match_operand:CC_any 1 "general_operand"
- " y,r, r,O,x,y,r,I,m,r"))]
+ " y,r, r,O,x,y,r,I,*h, r,m,r"))]
"register_operand (operands[0], mode)
|| register_operand (operands[1], mode)"
"@
@@ -8134,6 +8134,8 @@
mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf000
mr %0,%1
li %0,%1
+ mf%1 %0
+ mt%0 %1
lwz%U1%X1 %0,%1
stw%U0%X0 %1,%0"
[(set_attr_alternative "type"
@@ -8147,9 +8149,11 @@
(const_string "mfcrf") (const_string "mfcr"))
(const_string "integer")
(const_string "integer")
+ (const_string "mfjmpr")
+ (const_string "mtjmpr")
(const_string "load")
(const_string "store")])
- (set_attr "length" "*,*,12,*,*,8,*,*,*,*")])
+ (set_attr "length" "*,*,12,*,*,8,*,*,*,*,*,*")])
;; For floating-point, we normally deal with the floating-point registers
;; unless -msoft-float is used. The sole exception is that parameter passing
@@ -8200,17 +8204,17 @@
;;
;; LWZ LFSLXSSP LXSSPX STFS STXSSP
;; STXSSPX STWXXLXOR LI FMRXSCPSGNDP
-;; MR XXSPLTIDP
+;; MR MT MF NOPXXSPLTIDP
(define_insn "movsf_hardfloat"
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa,m, wY,
Z, m, wa, !r,f, wa,
- !r,wa")
+ !r,*c*l, !r, *h,wa")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa,r, j, j, f, wa,
- r, eP"))]
+ r, r, *h, 0, eP"))]
"(register_operand (operands[0], SFmode)
|| register_operand (operands[1], SFmode))
&& TARGET_HARD_FLOAT
@@ -8230,29 +8234,32 @@
fmr %0,%1
xscpsgndp %x0,%x1,%x1
mr %0,%1
+ mt%0 %1
+ mf%1 %0
+ nop
[gcc(refs/users/meissner/heads/work167-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:eb61a824e1d8ee0c86fca797c67fe2c55cec5c33 commit eb61a824e1d8ee0c86fca797c67fe2c55cec5c33 Author: Michael Meissner Date: Fri May 24 13:21:52 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 12 1 file changed, 12 insertions(+) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index fab703bc7a4..8141a355c54 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,3 +1,15 @@ + Branch work167-tar, patch #203 + +Add -mintspr. + +2024-05-24 Michael Meissner + + * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add + support for -mintspr. + * config/rs6000/rs6000.md (mov_internal): Add support for moving + QI/HImode to/from SPRs back. + * config/rs6000/rs6000.opt (-mintspr): New switch. + Branch work167-tar, patch #202 Add -mtar.
[gcc(refs/users/meissner/heads/work167-tar)] Add -mintspr.
https://gcc.gnu.org/g:819056304acea25b44313f402a5d9d51bf49d4cf commit 819056304acea25b44313f402a5d9d51bf49d4cf Author: Michael Meissner Date: Fri May 24 13:20:47 2024 -0400 Add -mintspr. 2024-05-24 Michael Meissner * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Add support for -mintspr. * config/rs6000/rs6000.md (mov_internal): Add support for moving QI/HImode to/from SPRs back. * config/rs6000/rs6000.opt (-mintspr): New switch. Diff: --- gcc/config/rs6000/rs6000.cc | 6 +- gcc/config/rs6000/rs6000.md | 17 ++--- gcc/config/rs6000/rs6000.opt | 4 3 files changed, 19 insertions(+), 8 deletions(-) diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc index f72c62f4e5f..fa330c2a4b1 100644 --- a/gcc/config/rs6000/rs6000.cc +++ b/gcc/config/rs6000/rs6000.cc @@ -1952,7 +1952,11 @@ rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode) case LR_REGNO: case CTR_REGNO: case TAR_REGNO: - return (!orig_complex_p && mode == Pmode); + return (!orig_complex_p + && (mode == Pmode + || (TARGET_INTSPR + && SCALAR_INT_MODE_P (mode) + && GET_MODE_SIZE (mode) <= UNITS_PER_WORD))); default: break; diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index d1ab06998c7..b5dc0719a88 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8064,16 +8064,16 @@ ;; MR LHZ/LBZLXSI*ZXSTH/STBSTXSI*XLI ;; XXLOR load 0 load -1VSPLTI*# MFVSRWZ -;; MTVSRWZ +;; MTVSRWZ MF%1 MT%1 NOP (define_insn "*mov_internal" [(set (match_operand:QHI 0 "nonimmediate_operand" "=r,r, wa,m, ?Z,r, wa,wa,wa,v, ?v,r, -wa") +wa,r, *c*l, *h") (match_operand:QHI 1 "input_operand" "r, m, ?Z,r, wa,i, wa,O, wM,wB,wS,wa, -r"))] +r, *h,r, 0"))] "gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode)" "@ @@ -8089,19 +8089,22 @@ vspltis %0,%1 # mfvsrwz %0,%x1 - mtvsrwz %x0,%1" + mtvsrwz %x0,%1 + mf%1 %0 + mt%0 %1 + nop" [(set_attr "type" "*, load, fpload,store, fpstore, *, vecsimple, vecperm, vecperm, vecperm, vecperm, mfvsr, -mtvsr") +mtvsr, mfjmpr,mtjmpr,*") (set_attr "length" "*, *, *, *, *, *, *, *, *, *, 8, *, -*") +*, *, *, *") (set_attr "isa" "*, *, p9v, *, p9v, *, p9v, p9v, p9v, p9v, p9v, p9v, -p9v")]) +p9v, *, *, *")]) ;; Here is how to move condition codes around. When we store CC data in diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt index 7f7a283bc99..bac74695f64 100644 --- a/gcc/config/rs6000/rs6000.opt +++ b/gcc/config/rs6000/rs6000.opt @@ -634,6 +634,10 @@ mtar Target Undocumented Mask(TAR) Var(rs6000_isa_flags) Allow (do not allow) use the TAR register. +mintspr +Target Undocumented Var(TARGET_INTSPR) Init(0) Save +Allow (do not allow) small integers in SPR registers. + ; Documented parameters -param=rs6000-vect-unroll-limit=
[gcc(refs/users/meissner/heads/work167-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:90f22c6271a2a0802ba77bb738c2c362eb557040 commit 90f22c6271a2a0802ba77bb738c2c362eb557040 Author: Michael Meissner Date: Fri May 24 00:57:41 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 85 ++- 1 file changed, 84 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index d4668c7d115..fab703bc7a4 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,4 +1,87 @@ -a Branch work167-tar, patch #11 from work167 branch + Branch work167-tar, patch #202 + +Add -mtar. + +gcc/ + +2024-05-23 Michael Meissner + + * config/rs6000/constraints.md (h constraint): Add documentation for TAR + register. + (wt constraint): New constraint. + * config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Document that we + are intentionally not setting -mtar for power9. + (OTHER_POWER10_MASKS): Add -mtar. + (POWERPC_MASKS): Likewise. + * config/rs6000/rs6000.cc (rs6000_reg_names): Add TAR register. + (alt_reg_names): Likewise. + (rs6000_hard_regno_mode_ok_uncached): Add support for -mtar. + (rs6000_debug_reg_global): Print information about the TAR register and + the wt constraint. + (rs6000_init_hard_regno_mode_ok): Setup the TAR register. Set up the wt + constraint if -mtar. + (rs6000_option_override_internal): If -mtar, make sure we are running on + at least a power9. + (rs6000_conditional_register_usage): Enable TAR register if -mtar. + (print_operand): Handle the TAR register. + (rs6000_debugger_regno): Likewise. + (rs6000_opt_masks): Add -mtar. + * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Add TAR register. + (FIXED_REGISTERS): Likewise. + (CALL_REALLY_USED_REGISTERS): Likewise. + (REG_ALLOC_ORDER): Likewise. + (enum reg_class): Add TAR_REGS register class. + (REG_CLASS_NAMES): Likewise. + (REG_CLASS_CONTENTS): Likewise. + (enum r6000_reg_class_enum): Add wt constraint. + (rs6000_reg_names): Add TAR register. + * config/rs6000/rs6000.md (TAR_REGNO): New constant. + (@tablejump_insn_normal): Add support for the TAR register. + (@tablejump_insn_nospec): Likewise. + * config/rs6000/rs6000.opt (-mtar): New option. + +gcc/testsuite/ + +2024-05-23 Michael Meissner + + * gcc.target/powerpc/ppc-switch-1.c: Update test for the TAR register. + * gcc.target/powerpc/pr51513.c: Likewise. + * gcc.target/powerpc/safe-indirect-jump-3.c: Likewise. + + Branch work167-tar, patch #201 + +Remove insn alternatives for SPRs with non-integer modes + +The previous patch changed the modes that SPR registers can hold to just be +appropriate sized integers (VSAVE and VSCR can only hold SImode, while CTR and +LR can only hold pointer sized values). This patch updates all of the move +insns for CC modes and floating point types from having alternatives to move +values to and from SPR registers. + +2024-05-23 Michael Meissner + + * config/rs6000/rs6000.md (mov_internal): Remove alternatives + moving values to and from SPR registers. + (movcc_): Likewise. + (movsf_hardfloat): Likewise. + (movsd_hardfloat): Likewise. + (mov_softfloat): Likewise. + (mov_hardfloat64): Likewise. + (mov_softfloat64): Likewise. + + Branch work167-tar, patch #200 + +Restrict SPR registers to only use integer modes. + +2024-05-23 Michael Meissner + +gcc/ + + * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Restrict + VRSAVE and VSCR to only hold hold SImode. Restrict LR and CTR to only + hold SImode or DImode, based on the address size. + + Branch work167-tar, patch #11 from work167 branch Add -mcpu=future tuning support.
[gcc(refs/users/meissner/heads/work167-tar)] Add -mtar.
https://gcc.gnu.org/g:f6ec5eb0db9232ae32f7ce9ddbfba54a48818e24
commit f6ec5eb0db9232ae32f7ce9ddbfba54a48818e24
Author: Michael Meissner
Date: Fri May 24 00:55:08 2024 -0400
Add -mtar.
gcc/
2024-05-23 Michael Meissner
* config/rs6000/constraints.md (h constraint): Add documentation
for TAR
register.
(wt constraint): New constraint.
* config/rs6000/rs6000-cpus.def (ISA_3_0_MASKS_SERVER): Document
that we
are intentionally not setting -mtar for power9.
(OTHER_POWER10_MASKS): Add -mtar.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.cc (rs6000_reg_names): Add TAR register.
(alt_reg_names): Likewise.
(rs6000_hard_regno_mode_ok_uncached): Add support for -mtar.
(rs6000_debug_reg_global): Print information about the TAR register
and
the wt constraint.
(rs6000_init_hard_regno_mode_ok): Setup the TAR register. Set up
the wt
constraint if -mtar.
(rs6000_option_override_internal): If -mtar, make sure we are
running on
at least a power9.
(rs6000_conditional_register_usage): Enable TAR register if -mtar.
(print_operand): Handle the TAR register.
(rs6000_debugger_regno): Likewise.
(rs6000_opt_masks): Add -mtar.
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Add TAR register.
(FIXED_REGISTERS): Likewise.
(CALL_REALLY_USED_REGISTERS): Likewise.
(REG_ALLOC_ORDER): Likewise.
(enum reg_class): Add TAR_REGS register class.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(enum r6000_reg_class_enum): Add wt constraint.
(rs6000_reg_names): Add TAR register.
* config/rs6000/rs6000.md (TAR_REGNO): New constant.
(@tablejump_insn_normal): Add support for the TAR register.
(@tablejump_insn_nospec): Likewise.
* config/rs6000/rs6000.opt (-mtar): New option.
gcc/testsuite/
2024-05-23 Michael Meissner
* gcc.target/powerpc/ppc-switch-1.c: Update test for the TAR
register.
* gcc.target/powerpc/pr51513.c: Likewise.
* gcc.target/powerpc/safe-indirect-jump-3.c: Likewise.
Diff:
---
gcc/config/rs6000/constraints.md | 5 ++-
gcc/config/rs6000/rs6000-cpus.def | 7 ++--
gcc/config/rs6000/rs6000.cc| 42 ++
gcc/config/rs6000/rs6000.h | 31 +---
gcc/config/rs6000/rs6000.md| 7 ++--
gcc/config/rs6000/rs6000.opt | 4 +++
gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c| 4 +--
gcc/testsuite/gcc.target/powerpc/pr51513.c | 4 +--
.../gcc.target/powerpc/safe-indirect-jump-3.c | 2 +-
9 files changed, 77 insertions(+), 29 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 369a7b75042..14f0465d7ae 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -57,7 +57,7 @@
"@internal A compatibility alias for @code{wa}.")
(define_register_constraint "h" "SPECIAL_REGS"
- "@internal A special register (@code{vrsave}, @code{ctr}, or @code{lr}).")
+ "@internal A special register (@code{vrsave}, @code{ctr}, @code{lr} or
@code{tar}).")
(define_register_constraint "c" "CTR_REGS"
"The count register, @code{ctr}.")
@@ -91,6 +91,9 @@
"@internal Like @code{r}, if @option{-mpowerpc64} is used; otherwise,
@code{NO_REGS}.")
+(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
+ "The tar register, @code{tar}.")
+
(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
"@internal Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise,
@code{NO_REGS}.")
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index d625dbeb91f..37366d5e056 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -59,7 +59,8 @@
| OPTION_MASK_P8_FUSION_SIGN)
/* Add ISEL back into ISA 3.0, since it is supposed to be a win. Do not add
- FLOAT128_HW here until we are ready to make -mfloat128 on by default. */
+ FLOAT128_HW here until we are ready to make -mfloat128 on by default. Also
+ do not add -mtar, since it isn't as helpful on power9. */
#define ISA_3_0_MASKS_SERVER ((ISA_2_7_MASKS_SERVER \
| OPTION_MASK_ISEL\
| OPTION_MASK_MODULO \
@@ -80,7 +81,8 @@
#define OTHER_POWER10_MASKS(OPTION_MASK_MMA\
| OPTION_MASK_PCREL\
[gcc(refs/users/meissner/heads/work167-tar)] Remove insn alternatives for SPRs with non-integer modes
https://gcc.gnu.org/g:4e4216bde017b1e531702599d6a02f5b708629a1 commit 4e4216bde017b1e531702599d6a02f5b708629a1 Author: Michael Meissner Date: Fri May 24 00:42:25 2024 -0400 Remove insn alternatives for SPRs with non-integer modes The previous patch changed the modes that SPR registers can hold to just be appropriate sized integers (VSAVE and VSCR can only hold SImode, while CTR and LR can only hold pointer sized values). This patch updates all of the move insns for CC modes and floating point types from having alternatives to move values to and from SPR registers. 2024-05-23 Michael Meissner * config/rs6000/rs6000.md (mov_internal): Remove alternatives moving values to and from SPR registers. (movcc_): Likewise. (movsf_hardfloat): Likewise. (movsd_hardfloat): Likewise. (mov_softfloat): Likewise. (mov_hardfloat64): Likewise. (mov_softfloat64): Likewise. Diff: --- gcc/config/rs6000/rs6000.md | 129 ++-- 1 file changed, 51 insertions(+), 78 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9503871ffd8..52e0fbc9564 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8063,16 +8063,16 @@ ;; MR LHZ/LBZLXSI*ZXSTH/STBSTXSI*XLI ;; XXLOR load 0 load -1VSPLTI*# MFVSRWZ -;; MTVSRWZ MF%1 MT%1 NOP +;; MTVSRWZ (define_insn "*mov_internal" [(set (match_operand:QHI 0 "nonimmediate_operand" "=r,r, wa,m, ?Z,r, wa,wa,wa,v, ?v,r, -wa,r, *c*l, *h") +wa") (match_operand:QHI 1 "input_operand" "r, m, ?Z,r, wa,i, wa,O, wM,wB,wS,wa, -r, *h,r, 0"))] +r"))] "gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode)" "@ @@ -8088,22 +8088,19 @@ vspltis %0,%1 # mfvsrwz %0,%x1 - mtvsrwz %x0,%1 - mf%1 %0 - mt%0 %1 - nop" + mtvsrwz %x0,%1" [(set_attr "type" "*, load, fpload,store, fpstore, *, vecsimple, vecperm, vecperm, vecperm, vecperm, mfvsr, -mtvsr, mfjmpr,mtjmpr,*") +mtvsr") (set_attr "length" "*, *, *, *, *, *, *, *, *, *, 8, *, -*, *, *, *") +*") (set_attr "isa" "*, *, p9v, *, p9v, *, p9v, p9v, p9v, p9v, p9v, p9v, -p9v, *, *, *")]) +p9v")]) ;; Here is how to move condition codes around. When we store CC data in @@ -8119,9 +8116,9 @@ (define_insn "*movcc_" [(set (match_operand:CC_any 0 "nonimmediate_operand" - "=y,x,?y,y,r,r,r,r, r,*c*l,r,m") + "=y,x,?y,y,r,r,r,r,r,m") (match_operand:CC_any 1 "general_operand" - " y,r, r,O,x,y,r,I,*h, r,m,r"))] + " y,r, r,O,x,y,r,I,m,r"))] "register_operand (operands[0], mode) || register_operand (operands[1], mode)" "@ @@ -8133,8 +8130,6 @@ mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf000 mr %0,%1 li %0,%1 - mf%1 %0 - mt%0 %1 lwz%U1%X1 %0,%1 stw%U0%X0 %1,%0" [(set_attr_alternative "type" @@ -8148,11 +8143,9 @@ (const_string "mfcrf") (const_string "mfcr")) (const_string "integer") (const_string "integer") - (const_string "mfjmpr") - (const_string "mtjmpr") (const_string "load") (const_string "store")]) - (set_attr "length" "*,*,12,*,*,8,*,*,*,*,*,*")]) + (set_attr "length" "*,*,12,*,*,8,*,*,*,*")]) ;; For floating-point, we normally deal with the floating-point registers ;; unless -msoft-float is used. The sole exception is that parameter passing @@ -8203,17 +8196,17 @@ ;; ;; LWZ LFSLXSSP LXSSPX STFS STXSSP ;; STXSSPX STWXXLXOR LI FMRXSCPSGNDP -;; MR MT MF NOPXXSPLTIDP +;; MR XXSPLTIDP (define_insn "movsf_hardfloat" [(set (match_operand:SF 0 "nonimmediate_operand" "=!r, f, v, wa,m, wY, Z, m, wa, !r,f, wa, - !r,*c*l, !r,
[gcc(refs/users/meissner/heads/work167-tar)] Revert all changes
https://gcc.gnu.org/g:1123234bcfb7308469c1ab9cc3103ff4472c7a43 commit 1123234bcfb7308469c1ab9cc3103ff4472c7a43 Author: Michael Meissner Date: Fri May 24 00:35:02 2024 -0400 Revert all changes Diff: --- gcc/config/rs6000/rs6000.md | 119 ++-- 1 file changed, 70 insertions(+), 49 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index e2d679e0b61..9503871ffd8 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8063,16 +8063,16 @@ ;; MR LHZ/LBZLXSI*ZXSTH/STBSTXSI*XLI ;; XXLOR load 0 load -1VSPLTI*# MFVSRWZ -;; MTVSRWZ +;; MTVSRWZ MF%1 MT%1 NOP (define_insn "*mov_internal" [(set (match_operand:QHI 0 "nonimmediate_operand" "=r,r, wa,m, ?Z,r, wa,wa,wa,v, ?v,r, -wa") +wa,r, *c*l, *h") (match_operand:QHI 1 "input_operand" "r, m, ?Z,r, wa,i, wa,O, wM,wB,wS,wa, -r"))] +r, *h,r, 0"))] "gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode)" "@ @@ -8088,19 +8088,22 @@ vspltis %0,%1 # mfvsrwz %0,%x1 - mtvsrwz %x0,%1" + mtvsrwz %x0,%1 + mf%1 %0 + mt%0 %1 + nop" [(set_attr "type" "*, load, fpload,store, fpstore, *, vecsimple, vecperm, vecperm, vecperm, vecperm, mfvsr, -mtvsr") +mtvsr, mfjmpr,mtjmpr,*") (set_attr "length" "*, *, *, *, *, *, *, *, *, *, 8, *, -*") +*, *, *, *") (set_attr "isa" "*, *, p9v, *, p9v, *, p9v, p9v, p9v, p9v, p9v, p9v, -p9v")]) +p9v, *, *, *")]) ;; Here is how to move condition codes around. When we store CC data in @@ -8116,9 +8119,9 @@ (define_insn "*movcc_" [(set (match_operand:CC_any 0 "nonimmediate_operand" - "=y,x,?y,y,r,r,r,r,r,m") + "=y,x,?y,y,r,r,r,r, r,*c*l,r,m") (match_operand:CC_any 1 "general_operand" - " y,r, r,O,x,y,r,I,m,r"))] + " y,r, r,O,x,y,r,I,*h, r,m,r"))] "register_operand (operands[0], mode) || register_operand (operands[1], mode)" "@ @@ -8130,6 +8133,8 @@ mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf000 mr %0,%1 li %0,%1 + mf%1 %0 + mt%0 %1 lwz%U1%X1 %0,%1 stw%U0%X0 %1,%0" [(set_attr_alternative "type" @@ -8143,9 +8148,11 @@ (const_string "mfcrf") (const_string "mfcr")) (const_string "integer") (const_string "integer") + (const_string "mfjmpr") + (const_string "mtjmpr") (const_string "load") (const_string "store")]) - (set_attr "length" "*,*,12,*,*,8,*,*,*,*")]) + (set_attr "length" "*,*,12,*,*,8,*,*,*,*,*,*")]) ;; For floating-point, we normally deal with the floating-point registers ;; unless -msoft-float is used. The sole exception is that parameter passing @@ -8196,17 +8203,17 @@ ;; ;; LWZ LFSLXSSP LXSSPX STFS STXSSP ;; STXSSPX STWXXLXOR LI FMRXSCPSGNDP -;; MR XXSPLTIDP +;; MR MT MF NOPXXSPLTIDP (define_insn "movsf_hardfloat" [(set (match_operand:SF 0 "nonimmediate_operand" "=!r, f, v, wa,m, wY, Z, m, wa, !r,f, wa, - !r,wa") + !r,*c*l, !r, *h,wa") (match_operand:SF 1 "input_operand" "m, m, wY, Z, f, v, wa,r, j, j, f, wa, - r, eP"))] + r, r, *h, 0, eP"))] "(register_operand (operands[0], SFmode) || register_operand (operands[1], SFmode)) && TARGET_HARD_FLOAT @@ -8226,29 +8233,32 @@ fmr %0,%1 xscpsgndp %x0,%x1,%x1 mr %0,%1 + mt%0 %1 + mf%1 %0 + nop #" [(set_attr "type" "load, fpload,fpload, fpload,fpstore, fpstore, fpstore,store, veclogical, integer, fpsimple, fpsimple, -*, vecperm") +*, mtjmpr,mfjmpr, *, vecperm")
[gcc(refs/users/meissner/heads/work167-tar)] Remove insn alternatives for SPRs with non-integer modes
https://gcc.gnu.org/g:f742d074a2e258b4bf938c89337d6c6bc58df3a5 commit f742d074a2e258b4bf938c89337d6c6bc58df3a5 Author: Michael Meissner Date: Fri May 24 00:22:22 2024 -0400 Remove insn alternatives for SPRs with non-integer modes The previous patch changed the modes that SPR registers can hold to just be appropriate sized integers (VSAVE and VSCR can only hold SImode, while CTR and LR can only hold pointer sized values). This patch updates all of the move insns for CC modes and floating point types from having alternatives to move values to and from SPR registers. 2024-05-23 Michael Meissner * config/rs6000/rs6000.md (mov_internal): Remove alternatives moving values to and from SPR registers. (movcc_): Likewise. (movsf_hardfloat): Likewise. (movsd_hardfloat): Likewise. (mov_softfloat): Likewise. (mov_hardfloat64): Likewise. (mov_softfloat64): Likewise. Diff: --- gcc/config/rs6000/rs6000.md | 119 ++-- 1 file changed, 49 insertions(+), 70 deletions(-) diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md index 9503871ffd8..e2d679e0b61 100644 --- a/gcc/config/rs6000/rs6000.md +++ b/gcc/config/rs6000/rs6000.md @@ -8063,16 +8063,16 @@ ;; MR LHZ/LBZLXSI*ZXSTH/STBSTXSI*XLI ;; XXLOR load 0 load -1VSPLTI*# MFVSRWZ -;; MTVSRWZ MF%1 MT%1 NOP +;; MTVSRWZ (define_insn "*mov_internal" [(set (match_operand:QHI 0 "nonimmediate_operand" "=r,r, wa,m, ?Z,r, wa,wa,wa,v, ?v,r, -wa,r, *c*l, *h") +wa") (match_operand:QHI 1 "input_operand" "r, m, ?Z,r, wa,i, wa,O, wM,wB,wS,wa, -r, *h,r, 0"))] +r"))] "gpc_reg_operand (operands[0], mode) || gpc_reg_operand (operands[1], mode)" "@ @@ -8088,22 +8088,19 @@ vspltis %0,%1 # mfvsrwz %0,%x1 - mtvsrwz %x0,%1 - mf%1 %0 - mt%0 %1 - nop" + mtvsrwz %x0,%1" [(set_attr "type" "*, load, fpload,store, fpstore, *, vecsimple, vecperm, vecperm, vecperm, vecperm, mfvsr, -mtvsr, mfjmpr,mtjmpr,*") +mtvsr") (set_attr "length" "*, *, *, *, *, *, *, *, *, *, 8, *, -*, *, *, *") +*") (set_attr "isa" "*, *, p9v, *, p9v, *, p9v, p9v, p9v, p9v, p9v, p9v, -p9v, *, *, *")]) +p9v")]) ;; Here is how to move condition codes around. When we store CC data in @@ -8119,9 +8116,9 @@ (define_insn "*movcc_" [(set (match_operand:CC_any 0 "nonimmediate_operand" - "=y,x,?y,y,r,r,r,r, r,*c*l,r,m") + "=y,x,?y,y,r,r,r,r,r,m") (match_operand:CC_any 1 "general_operand" - " y,r, r,O,x,y,r,I,*h, r,m,r"))] + " y,r, r,O,x,y,r,I,m,r"))] "register_operand (operands[0], mode) || register_operand (operands[1], mode)" "@ @@ -8133,8 +8130,6 @@ mfcr %0%Q1\;rlwinm %0,%0,%f1,0xf000 mr %0,%1 li %0,%1 - mf%1 %0 - mt%0 %1 lwz%U1%X1 %0,%1 stw%U0%X0 %1,%0" [(set_attr_alternative "type" @@ -8148,11 +8143,9 @@ (const_string "mfcrf") (const_string "mfcr")) (const_string "integer") (const_string "integer") - (const_string "mfjmpr") - (const_string "mtjmpr") (const_string "load") (const_string "store")]) - (set_attr "length" "*,*,12,*,*,8,*,*,*,*,*,*")]) + (set_attr "length" "*,*,12,*,*,8,*,*,*,*")]) ;; For floating-point, we normally deal with the floating-point registers ;; unless -msoft-float is used. The sole exception is that parameter passing @@ -8203,17 +8196,17 @@ ;; ;; LWZ LFSLXSSP LXSSPX STFS STXSSP ;; STXSSPX STWXXLXOR LI FMRXSCPSGNDP -;; MR MT MF NOPXXSPLTIDP +;; MR XXSPLTIDP (define_insn "movsf_hardfloat" [(set (match_operand:SF 0 "nonimmediate_operand" "=!r, f, v, wa,m, wY, Z, m, wa, !r,f, wa, - !r,*c*l, !r,
[gcc(refs/users/meissner/heads/work167-tar)] Restrict SPR registers to only use integer modes.
https://gcc.gnu.org/g:beb07e21e70fceee2cdf6c7bc5e880836a875d69
commit beb07e21e70fceee2cdf6c7bc5e880836a875d69
Author: Michael Meissner
Date: Thu May 23 20:35:49 2024 -0400
Restrict SPR registers to only use integer modes.
2024-05-23 Michael Meissner
gcc/
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Restrict
VRSAVE and VSCR to only hold hold SImode. Restrict LR and CTR to
only
hold SImode or DImode, based on the address size.
Diff:
---
gcc/config/rs6000/rs6000.cc | 24 +++-
1 file changed, 23 insertions(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index c5c4191127e..87861164b07 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1851,9 +1851,13 @@ static int
rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
{
int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
+ bool orig_complex_p = false;
if (COMPLEX_MODE_P (mode))
-mode = GET_MODE_INNER (mode);
+{
+ mode = GET_MODE_INNER (mode);
+ orig_complex_p = true;
+}
/* Vector pair modes need even/odd VSX register pairs. Only allow vector
registers. */
@@ -1935,6 +1939,24 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if (CA_REGNO_P (regno))
return mode == Pmode || mode == SImode;
+ /* Restrict SPR registers to only hold the integer mode natural for the
+ SPR. */
+ switch (regno)
+{
+ /* 32-bit registers. */
+case VRSAVE_REGNO:
+case VSCR_REGNO:
+ return (!orig_complex_p && mode == SImode);
+
+ /* Registers that hold addresses. */
+case LR_REGNO:
+case CTR_REGNO:
+ return (!orig_complex_p && mode == Pmode);
+
+default:
+ break;
+}
+
/* AltiVec only in AldyVec registers. */
if (ALTIVEC_REGNO_P (regno))
return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
[gcc(refs/users/meissner/heads/work167-vpair)] Apply patches from work167 branch
https://gcc.gnu.org/g:c61bf92e8617f3f95eb202fe2cac8f3286153fa5 commit c61bf92e8617f3f95eb202fe2cac8f3286153fa5 Author: Michael Meissner Date: Thu May 23 18:27:03 2024 -0400 Apply patches from work167 branch Diff: --- gcc/ChangeLog.vpair | 161 ++- gcc/config.gcc | 6 +- gcc/config/rs6000/aix71.h| 2 + gcc/config/rs6000/aix72.h| 2 + gcc/config/rs6000/aix73.h| 2 + gcc/config/rs6000/driver-rs6000.cc | 4 + gcc/config/rs6000/power10.md | 145 gcc/config/rs6000/ppc-auxv.h | 3 +- gcc/config/rs6000/rs6000-builtin.cc | 1 + gcc/config/rs6000/rs6000-c.cc| 4 + gcc/config/rs6000/rs6000-cpus.def| 10 ++ gcc/config/rs6000/rs6000-opts.h | 4 +- gcc/config/rs6000/rs6000-string.cc | 2 + gcc/config/rs6000/rs6000-tables.opt | 6 + gcc/config/rs6000/rs6000.cc | 46 ++-- gcc/config/rs6000/rs6000.h | 2 + gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt | 6 + gcc/doc/invoke.texi | 5 +- gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +++ gcc/testsuite/gcc.target/powerpc/power11-2.c | 20 gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++ gcc/testsuite/lib/target-supports.exp| 17 +++ 23 files changed, 384 insertions(+), 89 deletions(-) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair index bd1c672d118..d71e2b66d66 100644 --- a/gcc/ChangeLog.vpair +++ b/gcc/ChangeLog.vpair @@ -1,6 +1,165 @@ + Branch work167-vpair, patch #11 from work167 branch + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-05-23 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work167-vpair, patch #10 from work167 branch + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. + +This patch allows GCC to be configured with the --with-cpu=future and +--with-tune=future options. + +This patch passes -mfuture to the assembler if the user uses -mcpu=future. + +2024-05-23 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. + (POWERPC_MASKS): Add future isa bit. + (power11 cpu): Add future definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add future. + * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. + + Branch work167-vpair, patch #3 from work167 branch + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the appropriate option for +supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). + +2024-05-23 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + * lib/target-supports.exp (check_effective_target_power11_ok):
[gcc(refs/users/meissner/heads/work167-test)] Apply patches from work167 branch
https://gcc.gnu.org/g:abe02039b33a581d439e874edda3f0cb68bc32de commit abe02039b33a581d439e874edda3f0cb68bc32de Author: Michael Meissner Date: Thu May 23 18:25:57 2024 -0400 Apply patches from work167 branch Diff: --- gcc/ChangeLog.test | 161 ++- gcc/config.gcc | 6 +- gcc/config/rs6000/aix71.h| 2 + gcc/config/rs6000/aix72.h| 2 + gcc/config/rs6000/aix73.h| 2 + gcc/config/rs6000/driver-rs6000.cc | 4 + gcc/config/rs6000/power10.md | 145 gcc/config/rs6000/ppc-auxv.h | 3 +- gcc/config/rs6000/rs6000-builtin.cc | 1 + gcc/config/rs6000/rs6000-c.cc| 4 + gcc/config/rs6000/rs6000-cpus.def| 10 ++ gcc/config/rs6000/rs6000-opts.h | 4 +- gcc/config/rs6000/rs6000-string.cc | 2 + gcc/config/rs6000/rs6000-tables.opt | 6 + gcc/config/rs6000/rs6000.cc | 46 ++-- gcc/config/rs6000/rs6000.h | 2 + gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt | 6 + gcc/doc/invoke.texi | 5 +- gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +++ gcc/testsuite/gcc.target/powerpc/power11-2.c | 20 gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++ gcc/testsuite/lib/target-supports.exp| 17 +++ 23 files changed, 384 insertions(+), 89 deletions(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test index a23763d2a41..fd1478e3c43 100644 --- a/gcc/ChangeLog.test +++ b/gcc/ChangeLog.test @@ -1,6 +1,165 @@ + Branch work167-test, patch #11 from work167 branch + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-05-23 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work167-test, patch #10 from work167 branch + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. + +This patch allows GCC to be configured with the --with-cpu=future and +--with-tune=future options. + +This patch passes -mfuture to the assembler if the user uses -mcpu=future. + +2024-05-23 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. + (POWERPC_MASKS): Add future isa bit. + (power11 cpu): Add future definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add future. + * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. + + Branch work167-test, patch #3 from work167 branch + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the appropriate option for +supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). + +2024-05-23 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + * lib/target-supports.exp (check_effective_target_power11_ok): Add new
[gcc(refs/users/meissner/heads/work167-tar)] Apply patches from work167 branch
https://gcc.gnu.org/g:c11b1647ef8e4bb650c603a358aa0ef031b89298 commit c11b1647ef8e4bb650c603a358aa0ef031b89298 Author: Michael Meissner Date: Thu May 23 18:24:42 2024 -0400 Apply patches from work167 branch Diff: --- gcc/ChangeLog.tar| 161 ++- gcc/config.gcc | 6 +- gcc/config/rs6000/aix71.h| 2 + gcc/config/rs6000/aix72.h| 2 + gcc/config/rs6000/aix73.h| 2 + gcc/config/rs6000/driver-rs6000.cc | 4 + gcc/config/rs6000/power10.md | 145 gcc/config/rs6000/ppc-auxv.h | 3 +- gcc/config/rs6000/rs6000-builtin.cc | 1 + gcc/config/rs6000/rs6000-c.cc| 4 + gcc/config/rs6000/rs6000-cpus.def| 10 ++ gcc/config/rs6000/rs6000-opts.h | 4 +- gcc/config/rs6000/rs6000-string.cc | 2 + gcc/config/rs6000/rs6000-tables.opt | 6 + gcc/config/rs6000/rs6000.cc | 46 ++-- gcc/config/rs6000/rs6000.h | 2 + gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt | 6 + gcc/doc/invoke.texi | 5 +- gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +++ gcc/testsuite/gcc.target/powerpc/power11-2.c | 20 gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++ gcc/testsuite/lib/target-supports.exp| 17 +++ 23 files changed, 384 insertions(+), 89 deletions(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index 78607d8f05c..d4668c7d115 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,6 +1,165 @@ +a Branch work167-tar, patch #11 from work167 branch + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-05-23 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work167-tar, patch #10 from work167 branch + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. + +This patch allows GCC to be configured with the --with-cpu=future and +--with-tune=future options. + +This patch passes -mfuture to the assembler if the user uses -mcpu=future. + +2024-05-23 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. + (POWERPC_MASKS): Add future isa bit. + (power11 cpu): Add future definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add future. + * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. + + Branch work167-tar, patch #3 from work167 branch + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the appropriate option for +supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). + +2024-05-23 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + * lib/target-supports.exp (check_effective_target_power11_ok): Add new +
[gcc(refs/users/meissner/heads/work167-bugs)] Apply patches from work167 branch
https://gcc.gnu.org/g:ebeaf030cae130a8eeb9176e590cfce454aa7802 commit ebeaf030cae130a8eeb9176e590cfce454aa7802 Author: Michael Meissner Date: Thu May 23 18:23:14 2024 -0400 Apply patches from work167 branch Diff: --- gcc/ChangeLog.bugs | 161 ++- gcc/config.gcc | 6 +- gcc/config/rs6000/aix71.h| 2 + gcc/config/rs6000/aix72.h| 2 + gcc/config/rs6000/aix73.h| 2 + gcc/config/rs6000/driver-rs6000.cc | 4 + gcc/config/rs6000/power10.md | 145 gcc/config/rs6000/ppc-auxv.h | 3 +- gcc/config/rs6000/rs6000-builtin.cc | 1 + gcc/config/rs6000/rs6000-c.cc| 4 + gcc/config/rs6000/rs6000-cpus.def| 10 ++ gcc/config/rs6000/rs6000-opts.h | 4 +- gcc/config/rs6000/rs6000-string.cc | 2 + gcc/config/rs6000/rs6000-tables.opt | 6 + gcc/config/rs6000/rs6000.cc | 46 ++-- gcc/config/rs6000/rs6000.h | 2 + gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt | 6 + gcc/doc/invoke.texi | 5 +- gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +++ gcc/testsuite/gcc.target/powerpc/power11-2.c | 20 gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++ gcc/testsuite/lib/target-supports.exp| 17 +++ 23 files changed, 384 insertions(+), 89 deletions(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs index c9c1ff8d5e8..0fe7f63f94c 100644 --- a/gcc/ChangeLog.bugs +++ b/gcc/ChangeLog.bugs @@ -1,6 +1,165 @@ + Branch work167-bugs, patch #11 from work167 branch + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-05-23 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work167-bugs, patch #10 from work167 branch + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. + +This patch allows GCC to be configured with the --with-cpu=future and +--with-tune=future options. + +This patch passes -mfuture to the assembler if the user uses -mcpu=future. + +2024-05-23 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. + (POWERPC_MASKS): Add future isa bit. + (power11 cpu): Add future definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add future. + * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. + + Branch work167-bugs, patch #3 from work167 branch + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the appropriate option for +supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). + +2024-05-23 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + * lib/target-supports.exp (check_effective_target_power11_ok): Add new
[gcc(refs/users/meissner/heads/work167-dmf)] Apply patches from work167 branch
https://gcc.gnu.org/g:56895e0d810dd51becf2565c58b2dc0cdb54bb82 commit 56895e0d810dd51becf2565c58b2dc0cdb54bb82 Author: Michael Meissner Date: Thu May 23 18:21:32 2024 -0400 Apply patches from work167 branch Diff: --- gcc/ChangeLog.dmf| 161 ++- gcc/config.gcc | 6 +- gcc/config/rs6000/aix71.h| 2 + gcc/config/rs6000/aix72.h| 2 + gcc/config/rs6000/aix73.h| 2 + gcc/config/rs6000/driver-rs6000.cc | 4 + gcc/config/rs6000/power10.md | 145 gcc/config/rs6000/ppc-auxv.h | 3 +- gcc/config/rs6000/rs6000-builtin.cc | 1 + gcc/config/rs6000/rs6000-c.cc| 4 + gcc/config/rs6000/rs6000-cpus.def| 10 ++ gcc/config/rs6000/rs6000-opts.h | 4 +- gcc/config/rs6000/rs6000-string.cc | 2 + gcc/config/rs6000/rs6000-tables.opt | 6 + gcc/config/rs6000/rs6000.cc | 46 ++-- gcc/config/rs6000/rs6000.h | 2 + gcc/config/rs6000/rs6000.md | 2 +- gcc/config/rs6000/rs6000.opt | 6 + gcc/doc/invoke.texi | 5 +- gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +++ gcc/testsuite/gcc.target/powerpc/power11-2.c | 20 gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++ gcc/testsuite/lib/target-supports.exp| 17 +++ 23 files changed, 384 insertions(+), 89 deletions(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf index b6a636e362c..38fafbf300f 100644 --- a/gcc/ChangeLog.dmf +++ b/gcc/ChangeLog.dmf @@ -1,6 +1,165 @@ + Branch work167-dmf, patch #11 from work167 branch + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-05-23 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work167-dmf, patch #10 from work167 branch + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. + +This patch allows GCC to be configured with the --with-cpu=future and +--with-tune=future options. + +This patch passes -mfuture to the assembler if the user uses -mcpu=future. + +2024-05-23 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. + (POWERPC_MASKS): Add future isa bit. + (power11 cpu): Add future definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add future. + * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. + + Branch work167-dmf, patch #3 from work167 branch + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the appropriate option for +supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). + +2024-05-23 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + * lib/target-supports.exp (check_effective_target_power11_ok): Add new +
[gcc(refs/users/meissner/heads/work167)] Update ChangeLog.*
https://gcc.gnu.org/g:ada4006a6807cf3b41b4e9b7ae67132b9e2ffd4c commit ada4006a6807cf3b41b4e9b7ae67132b9e2ffd4c Author: Michael Meissner Date: Thu May 23 18:18:13 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 64 ++ 1 file changed, 64 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 27de0c5d65c..05080a966cd 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,3 +1,67 @@ + Branch work167, patch #11 + +Add -mcpu=future tuning support. + +This patch makes -mtune=future use the same tuning decision as -mtune=power11. + +2024-05-23 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add future as an + alterntive to power10 and power11. + + Branch work167, patch #10 + +Add -mcpu=future support. + +This patch adds the future option to the -mcpu= and -mtune= switches. + +This patch treats the future like a power11 in terms of costs and reassociation +width. + +This patch issues a ".machine future" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future. + +This patch allows GCC to be configured with the --with-cpu=future and +--with-tune=future options. + +This patch passes -mfuture to the assembler if the user uses -mcpu=future. + +2024-05-23 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR_FUTURE if -mcpu=future. + * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New define. + (POWERPC_MASKS): Add future isa bit. + (power11 cpu): Add future definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add future + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add future. + * config/rs6000/rs6000.opt (-mpower11): Add internal future ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=future. + Branch work167, patch #3 Add -mcpu=power11 tests.
[gcc(refs/users/meissner/heads/work167)] Add -mcpu=future tuning support.
https://gcc.gnu.org/g:c2547683f516bca26a655fd1ce4859b0485e720f commit c2547683f516bca26a655fd1ce4859b0485e720f Author: Michael Meissner Date: Thu May 23 18:16:54 2024 -0400 Add -mcpu=future tuning support. This patch makes -mtune=future use the same tuning decision as -mtune=power11. 2024-05-23 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add future as an alterntive to power10 and power11. Diff: --- gcc/config/rs6000/power10.md | 145 ++- 1 file changed, 73 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index 90312643858..1ec1bef0726 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,5 @@ -;; Scheduling description for the IBM POWER10 and POWER11 processors. +;; Scheduling description for the IBM POWER10 and POWER11 processors as well as +;; potential future processors. ;; Copyright (C) 2020-2024 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -97,12 +98,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +111,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +125,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +133,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +149,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +179,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +192,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10,power11")) + (eq_attr "cpu" "power10,power11,future")) "DU_even_power10,STU_power10") ; Update
[gcc(refs/users/meissner/heads/work167)] Add -mcpu=future support.
https://gcc.gnu.org/g:213ee672c76fdf1ed5a019bd6d3e113cf20e5b40
commit 213ee672c76fdf1ed5a019bd6d3e113cf20e5b40
Author: Michael Meissner
Date: Thu May 23 18:14:24 2024 -0400
Add -mcpu=future support.
This patch adds the future option to the -mcpu= and -mtune= switches.
This patch treats the future like a power11 in terms of costs and
reassociation
width.
This patch issues a ".machine future" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR_FUTURE if the user uses -mcpu=future.
This patch allows GCC to be configured with the --with-cpu=future and
--with-tune=future options.
This patch passes -mfuture to the assembler if the user uses -mcpu=future.
2024-05-23 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR_FUTURE if -mcpu=future.
* config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): New
define.
(POWERPC_MASKS): Add future isa bit.
(power11 cpu): Add future definition.
* config/rs6000/rs6000-opts.h (PROCESSOR_FUTURE): Add future
processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
future
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add future.
* config/rs6000/rs6000.opt (-mpower11): Add internal future ISA
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mcpu=future.
Diff:
---
gcc/config.gcc | 4 ++--
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 30 ++
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 +++
gcc/doc/invoke.texi | 2 +-
15 files changed, 48 insertions(+), 13 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index 32f6800e57c..6727868b008 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -534,7 +534,7 @@ powerpc*-*-*)
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
- | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xpower1[01] | xfuture | xpower6x | xrs64a | xcell | xa2 |
xe500mc64 \
| xe5500 | xe6500)
cpu_is_64bit=yes
;;
@@ -5623,7 +5623,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power1[01] | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x |
future \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 41037b3852d..570ddcc451d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
\
#undef ASM_CPU_SPEC
#define ASM_CPU_SPEC \
"%{mcpu=native: %(asm_cpu_native); \
+ mcpu=future: -mfuture; \
mcpu=power11: -mpwr11; \
mcpu=power10: -mpwr10; \
mcpu=power9: -mpwr9; \
diff --git a/gcc/config/rs6000/aix72.h b/gcc/config/rs6000/aix72.h
index fe59f8319b4..242ca94bd06 100644
--- a/gcc/config/rs6000/aix72.h
+++ b/gcc/config/rs6000/aix72.h
@@ -79,6 +79,7 @@ do {
[gcc(refs/users/meissner/heads/work167)] Update ChangeLog.*
https://gcc.gnu.org/g:f686e7a45871c01cee1a6bb07ff3fd88d5fd14c4 commit f686e7a45871c01cee1a6bb07ff3fd88d5fd14c4 Author: Michael Meissner Date: Thu May 23 17:55:53 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.meissner | 121 - 1 file changed, 120 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner index 2245f2111cb..27de0c5d65c 100644 --- a/gcc/ChangeLog.meissner +++ b/gcc/ChangeLog.meissner @@ -1,6 +1,125 @@ + Branch work167, patch #3 + +Add -mcpu=power11 tests. + +This patch adds some simple tests for -mcpu=power11 support. In order to run +these tests, you need an assembler that supports the appropriate option for +supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under AIX). + +2024-05-17 Michael Meissner + +gcc/testsuite/ + + * gcc.target/powerpc/power11-1.c: New test. + * gcc.target/powerpc/power11-2.c: Likewise. + * gcc.target/powerpc/power11-3.c: Likewise. + * lib/target-supports.exp (check_effective_target_power11_ok): Add new + effective target. + + Branch work167, patch #2 + +Add -mcpu=power11 tuning support. + +This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10. + +2024-05-17 Michael Meissner + +gcc/ + + * config/rs6000/power10.md (all reservations): Add power11 as an + alternative to power10. + + Branch work167, patch #1 + +Add -mcpu=power11 support. + +This patch adds the power11 option to the -mcpu= and -mtune= switches. + +This patch treats the power11 like a power10 in terms of costs and reassociation +width. + +This patch issues a ".machine power11" to the assembly file if you use +-mcpu=power11. + +This patch defines _ARCH_PWR11 if the user uses -mcpu=power11. + +This patch allows GCC to be configured with the --with-cpu=power11 and +--with-tune=power11 options. + +This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11. + +This patch adds support for using "power11" in the __builtin_cpu_is built-in +function. + +2024-05-17 Michael Meissner + +gcc/ + + * config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11. + * config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for -mcpu=power11. + * config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/driver-rs6000.cc (asm_names): Likewise. + * config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define. + * config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11. + * config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define + _ARCH_PWR11 if -mcpu=power11. + * config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New define. + (POWERPC_MASKS): Add power11 isa bit. + (power11 cpu): Add power11 definition. + * config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11 processor. + * config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise. + * config/rs6000/rs6000-tables.opt: Regenerate. + * config/rs6000/rs6000.cc (rs6000_option_override_internal): Add power11 + support. + (rs6000_machine_from_flags): Likewise. + (rs6000_reassociation_width): Likewise. + (rs6000_adjust_cost): Likewise. + (rs6000_issue_rate): Likewise. + (rs6000_sched_reorder): Likewise. + (rs6000_sched_reorder2): Likewise. + (rs6000_register_move_cost): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise. + * config/rs6000/rs6000.md (cpu attribute): Add power11. + * config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA flag. + * doc/invoke.texi (RS/6000 and PowerPC Options): Document -mcpu=power11. + Branch work167, baseline +Add ChangeLog.meissner and REVISION. + +2024-05-17 Michael Meissner + +gcc/ + + * REVISION: New file for branch. + * ChangeLog.meissner: New file. + +gcc/c-family/ + + * ChangeLog.meissner: New file. + +gcc/c/ + + * ChangeLog.meissner: New file. + +gcc/cp/ + + * ChangeLog.meissner: New file. + +gcc/fortran/ + + * ChangeLog.meissner: New file. + +gcc/testsuite/ + + * ChangeLog.meissner: New file. + +libgcc/ + + * ChangeLog.meissner: New file. + 2024-05-23 Michael Meissner Clone branch -
[gcc(refs/users/meissner/heads/work167)] Add -mcpu=power11 tests.
https://gcc.gnu.org/g:fdac16c009af4cc1392c127311adf5a90da3b7a6
commit fdac16c009af4cc1392c127311adf5a90da3b7a6
Author: Michael Meissner
Date: Thu May 23 17:49:40 2024 -0400
Add -mcpu=power11 tests.
This patch adds some simple tests for -mcpu=power11 support. In order to
run
these tests, you need an assembler that supports the appropriate option for
supporting the Power11 processor (-mpower11 under Linux or -mpwr11 under
AIX).
2024-05-23 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/power11-1.c: New test.
* gcc.target/powerpc/power11-2.c: Likewise.
* gcc.target/powerpc/power11-3.c: Likewise.
* lib/target-supports.exp (check_effective_target_power11_ok): Add
new
effective target.
Diff:
---
gcc/testsuite/gcc.target/powerpc/power11-1.c | 13 +
gcc/testsuite/gcc.target/powerpc/power11-2.c | 20
gcc/testsuite/gcc.target/powerpc/power11-3.c | 10 ++
gcc/testsuite/lib/target-supports.exp| 17 +
4 files changed, 60 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-1.c
b/gcc/testsuite/gcc.target/powerpc/power11-1.c
new file mode 100644
index 000..6a2e802eedf
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-1.c
@@ -0,0 +1,13 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power11 -O2" } */
+
+/* Basic check to see if the compiler supports -mcpu=power11. */
+
+#ifndef _ARCH_PWR11
+#error "-mcpu=power11 is not supported"
+#endif
+
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-2.c
b/gcc/testsuite/gcc.target/powerpc/power11-2.c
new file mode 100644
index 000..7b9904c1d29
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-2.c
@@ -0,0 +1,20 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-O2" } */
+
+/* Check if we can set the power11 target via a target attribute. */
+
+__attribute__((__target__("cpu=power9")))
+void foo_p9 (void)
+{
+}
+
+__attribute__((__target__("cpu=power10")))
+void foo_p10 (void)
+{
+}
+
+__attribute__((__target__("cpu=power11")))
+void foo_p11 (void)
+{
+}
diff --git a/gcc/testsuite/gcc.target/powerpc/power11-3.c
b/gcc/testsuite/gcc.target/powerpc/power11-3.c
new file mode 100644
index 000..9b2d643cc0f
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/power11-3.c
@@ -0,0 +1,10 @@
+/* { dg-do compile { target powerpc*-*-* } } */
+/* { dg-require-effective-target power11_ok } */
+/* { dg-options "-mdejagnu-cpu=power8 -O2" } */
+
+/* Check if we can set the power11 target via a target_clones attribute. */
+
+__attribute__((__target_clones__("cpu=power11,cpu=power9,default")))
+void foo (void)
+{
+}
diff --git a/gcc/testsuite/lib/target-supports.exp
b/gcc/testsuite/lib/target-supports.exp
index f0f6da52275..44bee60d433 100644
--- a/gcc/testsuite/lib/target-supports.exp
+++ b/gcc/testsuite/lib/target-supports.exp
@@ -7014,6 +7014,23 @@ proc check_effective_target_power10_ok { } {
}
}
+# Return 1 if this is a PowerPC target supporting -mcpu=power11.
+
+proc check_effective_target_power11_ok { } {
+if { ([istarget powerpc*-*-*]) } {
+ return [check_no_compiler_messages power11_ok object {
+ int main (void) {
+ #ifndef _ARCH_PWR11
+ #error "-mcpu=power11 is not supported"
+ #endif
+ return 0;
+ }
+ } "-mcpu=power11"]
+} else {
+ return 0
+}
+}
+
# Return 1 if this is a PowerPC target supporting -mfloat128 via either
# software emulation on power7/power8 systems or hardware support on power9.
[gcc(refs/users/meissner/heads/work167)] Add -mcpu=power11 tuning support.
https://gcc.gnu.org/g:1bd0632bafa64815b5d5eb7585578c324377d869 commit 1bd0632bafa64815b5d5eb7585578c324377d869 Author: Michael Meissner Date: Thu May 23 17:48:42 2024 -0400 Add -mcpu=power11 tuning support. This patch makes -mtune=power11 use the same tuning decisions as -mtune=power10. 2024-05-23 Michael Meissner gcc/ * config/rs6000/power10.md (all reservations): Add power11 as an alternative to power10. Diff: --- gcc/config/rs6000/power10.md | 144 +-- 1 file changed, 72 insertions(+), 72 deletions(-) diff --git a/gcc/config/rs6000/power10.md b/gcc/config/rs6000/power10.md index fcc2199ab29..90312643858 100644 --- a/gcc/config/rs6000/power10.md +++ b/gcc/config/rs6000/power10.md @@ -1,4 +1,4 @@ -;; Scheduling description for the IBM POWER10 processor. +;; Scheduling description for the IBM POWER10 and POWER11 processors. ;; Copyright (C) 2020-2024 Free Software Foundation, Inc. ;; ;; Contributed by Pat Haugen (pthau...@us.ibm.com). @@ -97,12 +97,12 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-fused-load" 4 (and (eq_attr "type" "fused_load_cmpi,fused_addis_load,fused_load_load") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-prefixed-load" 4 @@ -110,13 +110,13 @@ (eq_attr "update" "no") (eq_attr "size" "!128") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-load-update" 4 (and (eq_attr "type" "load") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-fpload-double" 4 @@ -124,7 +124,7 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "no") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") (define_insn_reservation "power10-prefixed-fpload-double" 4 @@ -132,14 +132,14 @@ (eq_attr "update" "no") (eq_attr "size" "64") (eq_attr "prefixed" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-double" 4 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "64") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; SFmode loads are cracked and have additional 3 cycles over DFmode @@ -148,27 +148,27 @@ (and (eq_attr "type" "fpload") (eq_attr "update" "no") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10") (define_insn_reservation "power10-fpload-update-single" 7 (and (eq_attr "type" "fpload") (eq_attr "update" "yes") (eq_attr "size" "32") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") (define_insn_reservation "power10-vecload" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,LU_power10") ; lxvp (define_insn_reservation "power10-vecload-pair" 4 (and (eq_attr "type" "vecload") (eq_attr "size" "256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,LU_power10+SXU_power10") ; Store Unit @@ -178,12 +178,12 @@ (eq_attr "prefixed" "no") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_any_power10,STU_power10") (define_insn_reservation "power10-fused-store" 0 (and (eq_attr "type" "fused_store_store") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") (define_insn_reservation "power10-prefixed-store" 0 @@ -191,52 +191,52 @@ (eq_attr "prefixed" "yes") (eq_attr "size" "!128") (eq_attr "size" "!256") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11")) "DU_even_power10,STU_power10") ; Update forms have 2 cycle latency for updated addr reg (define_insn_reservation "power10-store-update" 2 (and (eq_attr "type" "store,fpstore") (eq_attr "update" "yes") - (eq_attr "cpu" "power10")) + (eq_attr "cpu" "power10,power11"))
[gcc(refs/users/meissner/heads/work167)] Add -mcpu=power11 support.
https://gcc.gnu.org/g:9acc34653e38e169291be00b3e46a63b852adfad
commit 9acc34653e38e169291be00b3e46a63b852adfad
Author: Michael Meissner
Date: Thu May 23 17:46:40 2024 -0400
Add -mcpu=power11 support.
This patch adds the power11 option to the -mcpu= and -mtune= switches.
This patch treats the power11 like a power10 in terms of costs and
reassociation
width.
This patch issues a ".machine power11" to the assembly file if you use
-mcpu=power11.
This patch defines _ARCH_PWR11 if the user uses -mcpu=power11.
This patch allows GCC to be configured with the --with-cpu=power11 and
--with-tune=power11 options.
This patch passes -mpwr11 to the assembler if the user uses -mcpu=power11.
This patch adds support for using "power11" in the __builtin_cpu_is built-in
function.
2024-05-23 Michael Meissner
gcc/
* config.gcc (rs6000*-*-*, powerpc*-*-*): Add support for power11.
* config/rs6000/aix71.h (ASM_CPU_SPEC): Add support for
-mcpu=power11.
* config/rs6000/aix72.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/aix73.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/driver-rs6000.cc (asm_names): Likewise.
* config/rs6000/ppc-auxv.h (PPC_PLATFORM_POWER11): New define.
* config/rs6000/rs6000-builtin.cc (cpu_is_info): Add power11.
* config/rs6000/rs6000-c.cc (rs6000_target_modify_macros): Define
_ARCH_PWR11 if -mcpu=power11.
* config/rs6000/rs6000-cpus.def (ISA_POWER11_MASKS_SERVER): New
define.
(POWERPC_MASKS): Add power11 isa bit.
(power11 cpu): Add power11 definition.
* config/rs6000/rs6000-opts.h (PROCESSOR_POWER11): Add power11
processor.
* config/rs6000/rs6000-string.cc (expand_compare_loop): Likewise.
* config/rs6000/rs6000-tables.opt: Regenerate.
* config/rs6000/rs6000.cc (rs6000_option_override_internal): Add
power11
support.
(rs6000_machine_from_flags): Likewise.
(rs6000_reassociation_width): Likewise.
(rs6000_adjust_cost): Likewise.
(rs6000_issue_rate): Likewise.
(rs6000_sched_reorder): Likewise.
(rs6000_sched_reorder2): Likewise.
(rs6000_register_move_cost): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (ASM_CPU_SPEC): Likewise.
* config/rs6000/rs6000.md (cpu attribute): Add power11.
* config/rs6000/rs6000.opt (-mpower11): Add internal power11 ISA
flag.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mcpu=power11.
Diff:
---
gcc/config.gcc | 6 --
gcc/config/rs6000/aix71.h | 1 +
gcc/config/rs6000/aix72.h | 1 +
gcc/config/rs6000/aix73.h | 1 +
gcc/config/rs6000/driver-rs6000.cc | 2 ++
gcc/config/rs6000/ppc-auxv.h| 3 +--
gcc/config/rs6000/rs6000-builtin.cc | 1 +
gcc/config/rs6000/rs6000-c.cc | 2 ++
gcc/config/rs6000/rs6000-cpus.def | 5 +
gcc/config/rs6000/rs6000-opts.h | 3 ++-
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/rs6000-tables.opt | 3 +++
gcc/config/rs6000/rs6000.cc | 32
gcc/config/rs6000/rs6000.h | 1 +
gcc/config/rs6000/rs6000.md | 2 +-
gcc/config/rs6000/rs6000.opt| 3 +++
gcc/doc/invoke.texi | 5 +++--
17 files changed, 56 insertions(+), 16 deletions(-)
diff --git a/gcc/config.gcc b/gcc/config.gcc
index a37113bd00a..32f6800e57c 100644
--- a/gcc/config.gcc
+++ b/gcc/config.gcc
@@ -533,7 +533,9 @@ powerpc*-*-*)
extra_headers="${extra_headers} ppu_intrinsics.h spu2vmx.h vec_types.h
si2vmx.h"
extra_headers="${extra_headers} amo.h"
case x$with_cpu in
-
xpowerpc64|xdefault64|x6[23]0|x970|xG5|xpower[3456789]|xpower10|xpower6x|xrs64a|xcell|xa2|xe500mc64|xe5500|xe6500)
+ xpowerpc64 | xdefault64 | x6[23]0 | x970 | xG5 | xpower[3456789] \
+ | xpower1[01] | xpower6x | xrs64a | xcell | xa2 | xe500mc64 \
+ | xe5500 | xe6500)
cpu_is_64bit=yes
;;
esac
@@ -5621,7 +5623,7 @@ case "${target}" in
eval "with_$which=405"
;;
"" | common | native \
- | power[3456789] | power10 | power5+ | power6x \
+ | power[3456789] | power1[01] | power5+ | power6x \
| powerpc | powerpc64 | powerpc64le \
| rs64 \
| 401 | 403 | 405 | 405fp | 440 | 440fp | 464 | 464fp \
diff --git a/gcc/config/rs6000/aix71.h b/gcc/config/rs6000/aix71.h
index 24bc301e37d..41037b3852d 100644
--- a/gcc/config/rs6000/aix71.h
+++ b/gcc/config/rs6000/aix71.h
@@ -79,6 +79,7 @@ do {
[gcc(refs/users/meissner/heads/work167-orig)] Add REVISION.
https://gcc.gnu.org/g:078fca545fc4a6700191ccb1571cd692a381932a commit 078fca545fc4a6700191ccb1571cd692a381932a Author: Michael Meissner Date: Thu May 23 16:37:10 2024 -0400 Add REVISION. 2024-05-23 Michael Meissner gcc/ * REVISION: New file for branch. Diff: --- gcc/REVISION | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index 000..7cb30e39db6 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work167-orig branch
[gcc] Created branch 'meissner/heads/work167-orig' in namespace 'refs/users'
The branch 'meissner/heads/work167-orig' was created in namespace 'refs/users' pointing to: ed63cd2aa5b... c++: deleting array temporary [PR115187]
[gcc(refs/users/meissner/heads/work167-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:da03885cd30e53ccd98867f4405bb774e3422c6b commit da03885cd30e53ccd98867f4405bb774e3422c6b Author: Michael Meissner Date: Thu May 23 16:36:13 2024 -0400 Add ChangeLog.test and update REVISION. 2024-05-23 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 6 ++ gcc/REVISION | 1 + 2 files changed, 7 insertions(+) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index 000..a23763d2a41 --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,6 @@ + Branch work167-test, baseline + +2024-05-23 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index 000..cb9a9b840e8 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work167-test branch
[gcc] Created branch 'meissner/heads/work167-test' in namespace 'refs/users'
The branch 'meissner/heads/work167-test' was created in namespace 'refs/users' pointing to: ed63cd2aa5b... c++: deleting array temporary [PR115187]
[gcc(refs/users/meissner/heads/work167-bugs)] Add ChangeLog.bugs and update REVISION.
https://gcc.gnu.org/g:ac38da2da2c5982de1597a0eb1ecefd2a41b174c commit ac38da2da2c5982de1597a0eb1ecefd2a41b174c Author: Michael Meissner Date: Thu May 23 16:35:25 2024 -0400 Add ChangeLog.bugs and update REVISION. 2024-05-23 Michael Meissner gcc/ * ChangeLog.bugs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.bugs | 6 ++ gcc/REVISION | 1 + 2 files changed, 7 insertions(+) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs new file mode 100644 index 000..c9c1ff8d5e8 --- /dev/null +++ b/gcc/ChangeLog.bugs @@ -0,0 +1,6 @@ + Branch work167-bugs, baseline + +2024-05-23 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index 000..eb73642b7ee --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work167-bugs branch
[gcc] Created branch 'meissner/heads/work167-bugs' in namespace 'refs/users'
The branch 'meissner/heads/work167-bugs' was created in namespace 'refs/users' pointing to: ed63cd2aa5b... c++: deleting array temporary [PR115187]
[gcc(refs/users/meissner/heads/work167-tar)] Add ChangeLog.tar and update REVISION.
https://gcc.gnu.org/g:26caf436849198bcd21a038268c009c1d11868be commit 26caf436849198bcd21a038268c009c1d11868be Author: Michael Meissner Date: Thu May 23 16:34:28 2024 -0400 Add ChangeLog.tar and update REVISION. 2024-05-23 Michael Meissner gcc/ * ChangeLog.tar: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.tar | 6 ++ gcc/REVISION | 1 + 2 files changed, 7 insertions(+) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar new file mode 100644 index 000..78607d8f05c --- /dev/null +++ b/gcc/ChangeLog.tar @@ -0,0 +1,6 @@ + Branch work167-tar, baseline + +2024-05-23 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index 000..8d12d08aa00 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work167-tar branch
[gcc] Created branch 'meissner/heads/work167-tar' in namespace 'refs/users'
The branch 'meissner/heads/work167-tar' was created in namespace 'refs/users' pointing to: ed63cd2aa5b... c++: deleting array temporary [PR115187]
[gcc(refs/users/meissner/heads/work167-vpair)] Add ChangeLog.vpair and update REVISION.
https://gcc.gnu.org/g:35bb83b6bf20348d3538ad8278ab49d4c0f92f04 commit 35bb83b6bf20348d3538ad8278ab49d4c0f92f04 Author: Michael Meissner Date: Thu May 23 16:33:37 2024 -0400 Add ChangeLog.vpair and update REVISION. 2024-05-23 Michael Meissner gcc/ * ChangeLog.vpair: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.vpair | 6 ++ gcc/REVISION| 1 + 2 files changed, 7 insertions(+) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair new file mode 100644 index 000..bd1c672d118 --- /dev/null +++ b/gcc/ChangeLog.vpair @@ -0,0 +1,6 @@ + Branch work167-vpair, baseline + +2024-05-23 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index 000..9331b8afb5d --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work167-vpair branch
[gcc] Created branch 'meissner/heads/work167-vpair' in namespace 'refs/users'
The branch 'meissner/heads/work167-vpair' was created in namespace 'refs/users' pointing to: ed63cd2aa5b... c++: deleting array temporary [PR115187]
[gcc(refs/users/meissner/heads/work167-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:20c9227b667baf56dfea8d2d4bb44d5650b9e2e2 commit 20c9227b667baf56dfea8d2d4bb44d5650b9e2e2 Author: Michael Meissner Date: Thu May 23 16:32:19 2024 -0400 Add ChangeLog.dmf and update REVISION. 2024-05-23 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 6 ++ gcc/REVISION | 1 + 2 files changed, 7 insertions(+) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index 000..b6a636e362c --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,6 @@ + Branch work167-dmf, baseline + +2024-05-23 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index 000..fbb05404a74 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work167-dmf branch
[gcc] Created branch 'meissner/heads/work167-dmf' in namespace 'refs/users'
The branch 'meissner/heads/work167-dmf' was created in namespace 'refs/users' pointing to: ed63cd2aa5b... c++: deleting array temporary [PR115187]
[gcc(refs/users/meissner/heads/work167)] Add ChangeLog.meissner and REVISION.
https://gcc.gnu.org/g:8821f30cbf6b5a6c5adc0df5c64798609fc0ecdd commit 8821f30cbf6b5a6c5adc0df5c64798609fc0ecdd Author: Michael Meissner Date: Thu May 23 16:31:21 2024 -0400 Add ChangeLog.meissner and REVISION. 2024-05-23 Michael Meissner gcc/ * REVISION: New file for branch. * ChangeLog.meissner: New file. gcc/c-family/ * ChangeLog.meissner: New file. gcc/c/ * ChangeLog.meissner: New file. gcc/cp/ * ChangeLog.meissner: New file. gcc/fortran/ * ChangeLog.meissner: New file. gcc/testsuite/ * ChangeLog.meissner: New file. libgcc/ * ChangeLog.meissner: New file. Diff: --- gcc/ChangeLog.meissner | 6 ++ gcc/REVISION | 1 + gcc/c-family/ChangeLog.meissner | 6 ++ gcc/c/ChangeLog.meissner | 6 ++ gcc/cp/ChangeLog.meissner| 6 ++ gcc/fortran/ChangeLog.meissner | 6 ++ gcc/testsuite/ChangeLog.meissner | 6 ++ libgcc/ChangeLog.meissner| 6 ++ libstdc++-v3/ChangeLog.meissner | 6 ++ 9 files changed, 49 insertions(+) diff --git a/gcc/ChangeLog.meissner b/gcc/ChangeLog.meissner new file mode 100644 index 000..2245f2111cb --- /dev/null +++ b/gcc/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work167, baseline + +2024-05-23 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION new file mode 100644 index 000..076e233d227 --- /dev/null +++ b/gcc/REVISION @@ -0,0 +1 @@ +work167 branch diff --git a/gcc/c-family/ChangeLog.meissner b/gcc/c-family/ChangeLog.meissner new file mode 100644 index 000..2245f2111cb --- /dev/null +++ b/gcc/c-family/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work167, baseline + +2024-05-23 Michael Meissner + + Clone branch + diff --git a/gcc/c/ChangeLog.meissner b/gcc/c/ChangeLog.meissner new file mode 100644 index 000..2245f2111cb --- /dev/null +++ b/gcc/c/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work167, baseline + +2024-05-23 Michael Meissner + + Clone branch + diff --git a/gcc/cp/ChangeLog.meissner b/gcc/cp/ChangeLog.meissner new file mode 100644 index 000..2245f2111cb --- /dev/null +++ b/gcc/cp/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work167, baseline + +2024-05-23 Michael Meissner + + Clone branch + diff --git a/gcc/fortran/ChangeLog.meissner b/gcc/fortran/ChangeLog.meissner new file mode 100644 index 000..2245f2111cb --- /dev/null +++ b/gcc/fortran/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work167, baseline + +2024-05-23 Michael Meissner + + Clone branch + diff --git a/gcc/testsuite/ChangeLog.meissner b/gcc/testsuite/ChangeLog.meissner new file mode 100644 index 000..2245f2111cb --- /dev/null +++ b/gcc/testsuite/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work167, baseline + +2024-05-23 Michael Meissner + + Clone branch + diff --git a/libgcc/ChangeLog.meissner b/libgcc/ChangeLog.meissner new file mode 100644 index 000..2245f2111cb --- /dev/null +++ b/libgcc/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work167, baseline + +2024-05-23 Michael Meissner + + Clone branch + diff --git a/libstdc++-v3/ChangeLog.meissner b/libstdc++-v3/ChangeLog.meissner new file mode 100644 index 000..2245f2111cb --- /dev/null +++ b/libstdc++-v3/ChangeLog.meissner @@ -0,0 +1,6 @@ + Branch work167, baseline + +2024-05-23 Michael Meissner + + Clone branch +
[gcc] Created branch 'meissner/heads/work167' in namespace 'refs/users'
The branch 'meissner/heads/work167' was created in namespace 'refs/users' pointing to: ed63cd2aa5b... c++: deleting array temporary [PR115187]
[gcc(refs/users/meissner/heads/work166-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:2b03ff803c7f0e6c4f695a0969c966f30c2cf9db commit 2b03ff803c7f0e6c4f695a0969c966f30c2cf9db Author: Michael Meissner Date: Mon May 20 17:18:26 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 94 ++- 1 file changed, 93 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index 3e168fa367eb..c09b96a6afc1 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,6 +1,98 @@ + Branch work166-tar, patch #202 + +Add -mtar. + +gcc/ + +2024-05-20 Michael Meissner + + * config/rs6000/constraints.md (h constraint): Add documentation for TAR + register. + (wt constraint): New constraint. + * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mtar. + * config/rs6000/rs6000.cc (rs6000_reg_names): Add TAR register. + (alt_reg_names): Likewise. + (rs6000_hard_regno_mode_ok_uncached): Add support for -mintspr. + (rs6000_debug_reg_global): Print information about the TAR register and + the wt constraint. + (rs6000_init_hard_regno_mode_ok): Setup the TAR register. Set up the wt + constraint if -mtar. + (rs6000_option_override_internal): If -mtar, make sure we are running on + at least a power9. + (rs6000_conditional_register_usage): Enable TAR register if -mtar. + (print_operand): Handle the TAR register. + (rs6000_debugger_regno): Likewise. + (rs6000_opt_masks): Add -mtar. + * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Add TAR register. + (FIXED_REGISTERS): Likewise. + (CALL_REALLY_USED_REGISTERS): Likewise. + (REG_ALLOC_ORDER): Likewise. + (enum reg_class): Add TAR_REGS register class. + (REG_CLASS_NAMES): Likewise. + (REG_CLASS_CONTENTS): Likewise. + (enum r6000_reg_class_enum): Add wt constraint. + (rs6000_reg_names): Add TAR register. + * config/rs6000/rs6000.md (TAR_REGNO): New constant. + (mov_internal): Add support for the TAR register. + (movcc_): Likewise. + (movsf_hardfloat): Likewise. + (movsf_hardfloat): Likewise. + (movsd_hardfloat): Likewise. + (mov_hardfloat64): Likewise. + (mov_softfloat64): Likewise. + (@tablejump_insn_normal): Likewise. + (@tablejump_insn_nospec): Likewise. + * config/rs6000/rs6000.opt (-mtar): New option. + +gcc/testsuite/ + +2024-05-14 Michael Meissner + + * gcc.target/powerpc/ppc-switch-1.c: Update test for the TAR register. + * gcc.target/powerpc/pr51513.c: Likewise. + * gcc.target/powerpc/safe-indirect-jump-3.c: Likewise. + + Branch work166-tar, patch #201 + +Add -mmfspr + +2024-05-20 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mmfspr. + * config/rs6000/rs6000.cc (rs6000_register_move_cost): If -mmfspr, make + moves from CTR more expensive. + (rs6000_opt_masks): Add -mmfspr. + * config/rs6000/rs6000.opt (-mmfspr): New option. + + Branch work166-tar, patch #200 + +Add -mintspr + +2024-05-20 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mintspr. + * config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached): Restrict + modes that go in SPRs to modes that fit in the SPR and are not complex + modes. If -mintspr, restrict modes that go into SPRs to be scalar + integers. + (rs6000_opt_masks): Add -mintspr. + * config/rs6000/rs6000 (-mintspr): New option. + Branch work166-tar, baseline +Add ChangeLog.tar and update REVISION. + +2024-05-02 Michael Meissner + +gcc/ + + * ChangeLog.tar: New file for branch. + * REVISION: Update. + 2024-05-17 Michael Meissner Clone branch -
[gcc(refs/users/meissner/heads/work166-tar)] Add -mtar.
https://gcc.gnu.org/g:978a8513f7cf7f6a26750d9f7fc1e23d04c34c48
commit 978a8513f7cf7f6a26750d9f7fc1e23d04c34c48
Author: Michael Meissner
Date: Mon May 20 17:11:58 2024 -0400
Add -mtar.
gcc/
2024-05-20 Michael Meissner
* config/rs6000/constraints.md (h constraint): Add documentation
for TAR
register.
(wt constraint): New constraint.
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mtar.
* config/rs6000/rs6000.cc (rs6000_reg_names): Add TAR register.
(alt_reg_names): Likewise.
(rs6000_hard_regno_mode_ok_uncached): Add support for -mintspr.
(rs6000_debug_reg_global): Print information about the TAR register
and
the wt constraint.
(rs6000_init_hard_regno_mode_ok): Setup the TAR register. Set up
the wt
constraint if -mtar.
(rs6000_option_override_internal): If -mtar, make sure we are
running on
at least a power9.
(rs6000_conditional_register_usage): Enable TAR register if -mtar.
(print_operand): Handle the TAR register.
(rs6000_debugger_regno): Likewise.
(rs6000_opt_masks): Add -mtar.
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Add TAR register.
(FIXED_REGISTERS): Likewise.
(CALL_REALLY_USED_REGISTERS): Likewise.
(REG_ALLOC_ORDER): Likewise.
(enum reg_class): Add TAR_REGS register class.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(enum r6000_reg_class_enum): Add wt constraint.
(rs6000_reg_names): Add TAR register.
* config/rs6000/rs6000.md (TAR_REGNO): New constant.
(mov_internal): Add support for the TAR register.
(movcc_): Likewise.
(movsf_hardfloat): Likewise.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
(mov_hardfloat64): Likewise.
(mov_softfloat64): Likewise.
(@tablejump_insn_normal): Likewise.
(@tablejump_insn_nospec): Likewise.
* config/rs6000/rs6000.opt (-mtar): New option.
gcc/testsuite/
2024-05-14 Michael Meissner
* gcc.target/powerpc/ppc-switch-1.c: Update test for the TAR
register.
* gcc.target/powerpc/pr51513.c: Likewise.
* gcc.target/powerpc/safe-indirect-jump-3.c: Likewise.
Diff:
---
gcc/config/rs6000/constraints.md | 5 ++-
gcc/config/rs6000/rs6000-cpus.def | 1 +
gcc/config/rs6000/rs6000.cc| 46 ++
gcc/config/rs6000/rs6000.h | 31 +--
gcc/config/rs6000/rs6000.md| 23 +--
gcc/config/rs6000/rs6000.opt | 4 ++
gcc/testsuite/gcc.target/powerpc/ppc-switch-1.c| 4 +-
gcc/testsuite/gcc.target/powerpc/pr51513.c | 4 +-
.../gcc.target/powerpc/safe-indirect-jump-3.c | 2 +-
9 files changed, 83 insertions(+), 37 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 369a7b75042d..14f0465d7ae5 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -57,7 +57,7 @@
"@internal A compatibility alias for @code{wa}.")
(define_register_constraint "h" "SPECIAL_REGS"
- "@internal A special register (@code{vrsave}, @code{ctr}, or @code{lr}).")
+ "@internal A special register (@code{vrsave}, @code{ctr}, @code{lr} or
@code{tar}).")
(define_register_constraint "c" "CTR_REGS"
"The count register, @code{ctr}.")
@@ -91,6 +91,9 @@
"@internal Like @code{r}, if @option{-mpowerpc64} is used; otherwise,
@code{NO_REGS}.")
+(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
+ "The tar register, @code{tar}.")
+
(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
"@internal Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise,
@code{NO_REGS}.")
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 47aca85aa4bc..0907930b2d8b 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -160,6 +160,7 @@
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL\
+| OPTION_MASK_TAR \
| OPTION_MASK_VSX)
#endif
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index ce1a49abe598..1fe3eda838fe 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1224,8 +1224,8 @@ char rs6000_reg_names[][8] =
"lr", "ctr", "ca", "ap",
/* cr0..cr7 */
[gcc(refs/users/meissner/heads/work166-tar)] Add -mmfspr
https://gcc.gnu.org/g:5816726d26832b3d0f3a87f06b4b3e38982ce89c
commit 5816726d26832b3d0f3a87f06b4b3e38982ce89c
Author: Michael Meissner
Date: Mon May 20 16:38:25 2024 -0400
Add -mmfspr
2024-05-20 Michael Meissner
gcc/
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mmfspr.
* config/rs6000/rs6000.cc (rs6000_register_move_cost): If -mmfspr,
make
moves from CTR more expensive.
(rs6000_opt_masks): Add -mmfspr.
* config/rs6000/rs6000.opt (-mmfspr): New option.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 1 +
gcc/config/rs6000/rs6000.cc | 12
gcc/config/rs6000/rs6000.opt | 4
3 files changed, 17 insertions(+)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index 6fcbcbdadef7..47aca85aa4bc 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -136,6 +136,7 @@
| OPTION_MASK_INTSPR \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF\
+| OPTION_MASK_MFSPR\
| OPTION_MASK_MMA \
| OPTION_MASK_MODULO \
| OPTION_MASK_MULHW\
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 7d5b94cda101..ce1a49abe598 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -22807,6 +22807,17 @@ rs6000_register_move_cost (machine_mode mode,
ret = 2 * hard_regno_nregs (reg, mode);
}
+ /* Make moves from the CTR register more expensive so that the register
+ allocator does not think of these registers are useful for saving
+ results. */
+ else if (TARGET_MFSPR
+ && reg_classes_intersect_p (to, GENERAL_REGS)
+ && reg_classes_intersect_p (from, CTR_REGS))
+{
+ rclass = from;
+ ret = 32;
+}
+
/* Moves from/to GENERAL_REGS. */
else if ((rclass = from, reg_classes_intersect_p (to, GENERAL_REGS))
|| (rclass = to, reg_classes_intersect_p (from, GENERAL_REGS)))
@@ -24491,6 +24502,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "isel",OPTION_MASK_ISEL, false, true },
{ "mfcrf", OPTION_MASK_MFCRF, false, true },
{ "mfpgpr", 0, false, true },
+ { "mfspr", OPTION_MASK_MFSPR, false, true },
{ "mma", OPTION_MASK_MMA,false, true },
{ "modulo", OPTION_MASK_MODULO, false, true },
{ "mulhw", OPTION_MASK_MULHW, false, true },
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 2f3970b664cc..d45746bc24f4 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -634,6 +634,10 @@ mintspr
Target Undocumented Mask(INTSPR) Var(rs6000_isa_flags)
Disallow (allow) non-integer types in SPR registers.
+mmfspr
+Target Undocumented Mask(MFSPR) Var(rs6000_isa_flags)
+Disallow (allow) non-integer types in SPR registers.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
[gcc(refs/users/meissner/heads/work166-tar)] Add -mintspr
https://gcc.gnu.org/g:fb7e62663cd40d434bbd2ae53082ca3f56ef2ef7
commit fb7e62663cd40d434bbd2ae53082ca3f56ef2ef7
Author: Michael Meissner
Date: Mon May 20 14:25:40 2024 -0400
Add -mintspr
2024-05-20 Michael Meissner
gcc/
* config/rs6000/rs6000-cpus.def (POWERPC_MASKS): Add -mintspr.
* config/rs6000/rs6000.cc (rs6000_hard_regno_mode_ok_uncached):
Restrict
modes that go in SPRs to modes that fit in the SPR and are not
complex
modes. If -mintspr, restrict modes that go into SPRs to be scalar
integers.
(rs6000_opt_masks): Add -mintspr.
* config/rs6000/rs6000 (-mintspr): New option.
Diff:
---
gcc/config/rs6000/rs6000-cpus.def | 1 +
gcc/config/rs6000/rs6000.cc | 27 ++-
gcc/config/rs6000/rs6000.opt | 4
3 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index d625dbeb91fd..6fcbcbdadef7 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -133,6 +133,7 @@
| OPTION_MASK_POWER11 \
| OPTION_MASK_P10_FUSION \
| OPTION_MASK_HTM \
+| OPTION_MASK_INTSPR \
| OPTION_MASK_ISEL \
| OPTION_MASK_MFCRF\
| OPTION_MASK_MMA \
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 96241c18b617..7d5b94cda101 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1851,9 +1851,13 @@ static int
rs6000_hard_regno_mode_ok_uncached (int regno, machine_mode mode)
{
int last_regno = regno + rs6000_hard_regno_nregs[mode][regno] - 1;
+ bool orig_complex_p = false;
if (COMPLEX_MODE_P (mode))
-mode = GET_MODE_INNER (mode);
+{
+ mode = GET_MODE_INNER (mode);
+ orig_complex_p = true;
+}
/* Vector pair modes need even/odd VSX register pairs. Only allow vector
registers. */
@@ -1935,6 +1939,26 @@ rs6000_hard_regno_mode_ok_uncached (int regno,
machine_mode mode)
if (CA_REGNO_P (regno))
return mode == Pmode || mode == SImode;
+ /* Possibly restrict SPR registers to have small scalar integers. */
+ switch (regno)
+{
+case VRSAVE_REGNO:
+case VSCR_REGNO:
+case LR_REGNO:
+case CTR_REGNO:
+ {
+ unsigned reg_size = ((regno == VRSAVE_REGNO || regno == VSCR_REGNO)
+? 4
+: UNITS_PER_WORD);
+
+ return (!orig_complex_p && GET_MODE_SIZE (mode) <= reg_size
+ && (!TARGET_INTSPR || SCALAR_INT_MODE_P (mode)));
+ }
+
+default:
+ break;
+}
+
/* AltiVec only in AldyVec registers. */
if (ALTIVEC_REGNO_P (regno))
return (VECTOR_MEM_ALTIVEC_OR_VSX_P (mode)
@@ -24463,6 +24487,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "power11", OPTION_MASK_POWER11,false, false },
{ "hard-dfp",OPTION_MASK_DFP,false,
true },
{ "htm", OPTION_MASK_HTM,false, true },
+ { "intspr", OPTION_MASK_INTSPR, false, true },
{ "isel",OPTION_MASK_ISEL, false, true },
{ "mfcrf", OPTION_MASK_MFCRF, false, true },
{ "mfpgpr", 0, false, true },
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 70fd7080bc52..2f3970b664cc 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -630,6 +630,10 @@ mieee128-constant
Target Var(TARGET_IEEE128_CONSTANT) Init(1) Save
Generate (do not generate) code that uses the LXVKQ instruction.
+mintspr
+Target Undocumented Mask(INTSPR) Var(rs6000_isa_flags)
+Disallow (allow) non-integer types in SPR registers.
+
; Documented parameters
-param=rs6000-vect-unroll-limit=
[gcc(refs/users/meissner/heads/work166-vpair)] Merge commit 'refs/users/meissner/heads/work166-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work
https://gcc.gnu.org/g:e60cea0eb7b7a7887270717e3acb24a280af9f95 commit e60cea0eb7b7a7887270717e3acb24a280af9f95 Merge: d8ce7db4c231 371220eb0c01 Author: Michael Meissner Date: Fri May 17 21:07:48 2024 -0400 Merge commit 'refs/users/meissner/heads/work166-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work166-vpair Diff:
[gcc(refs/users/meissner/heads/work166-vpair)] Add ChangeLog.vpair and update REVISION.
https://gcc.gnu.org/g:d8ce7db4c231d73ebba1285e237f8b34e8e502fb commit d8ce7db4c231d73ebba1285e237f8b34e8e502fb Author: Michael Meissner Date: Fri May 17 20:41:52 2024 -0400 Add ChangeLog.vpair and update REVISION. 2024-05-17 Michael Meissner gcc/ * ChangeLog.vpair: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.vpair | 6 ++ gcc/REVISION| 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair new file mode 100644 index ..172fd3d00bc4 --- /dev/null +++ b/gcc/ChangeLog.vpair @@ -0,0 +1,6 @@ + Branch work166-vpair, baseline + +2024-05-17 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 42eef54d0aeb..155b9d8d70eb 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work166 branch +work166-vpair branch
[gcc/meissner/heads/work166-vpair] (8 commits) Merge commit 'refs/users/meissner/heads/work166-vpair' of g
The branch 'meissner/heads/work166-vpair' was updated to point to: e60cea0eb7b7... Merge commit 'refs/users/meissner/heads/work166-vpair' of g It previously pointed to: 371220eb0c01... Add ChangeLog.vpair and update REVISION. Diff: Summary of changes (added commits): --- e60cea0... Merge commit 'refs/users/meissner/heads/work166-vpair' of g d8ce7db... Add ChangeLog.vpair and update REVISION. 373ebc4... Update ChangeLog.* (*) a0ccb78... Add -mcpu=future tuning support. (*) 78dc639... Add -mcpu=future support. (*) d69f7b4... Add -mcpu=power11 tests. (*) c47c66e... Add -mcpu=power11 tuning support. (*) 00c9f9b... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work166-vpair' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work166-test)] Merge commit 'refs/users/meissner/heads/work166-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:92c1554aaa046ea67e52cebf8616390f8d772878 commit 92c1554aaa046ea67e52cebf8616390f8d772878 Merge: d955b23a2461 ebd3fabfb5ba Author: Michael Meissner Date: Fri May 17 21:06:41 2024 -0400 Merge commit 'refs/users/meissner/heads/work166-test' of git+ssh://gcc.gnu.org/git/gcc into me/work166-test Diff:
[gcc(refs/users/meissner/heads/work166-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:d955b23a2461097fbd714d30945505762cdd0a21 commit d955b23a2461097fbd714d30945505762cdd0a21 Author: Michael Meissner Date: Fri May 17 20:48:57 2024 -0400 Add ChangeLog.test and update REVISION. 2024-05-17 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index ..e2a281f8f9ec --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,6 @@ + Branch work166-test, baseline + +2024-05-17 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 42eef54d0aeb..a8ef9d6b8080 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work166 branch +work166-test branch
[gcc/meissner/heads/work166-test] (8 commits) Merge commit 'refs/users/meissner/heads/work166-test' of gi
The branch 'meissner/heads/work166-test' was updated to point to: 92c1554aaa04... Merge commit 'refs/users/meissner/heads/work166-test' of gi It previously pointed to: ebd3fabfb5ba... Add ChangeLog.test and update REVISION. Diff: Summary of changes (added commits): --- 92c1554... Merge commit 'refs/users/meissner/heads/work166-test' of gi d955b23... Add ChangeLog.test and update REVISION. 373ebc4... Update ChangeLog.* (*) a0ccb78... Add -mcpu=future tuning support. (*) 78dc639... Add -mcpu=future support. (*) d69f7b4... Add -mcpu=power11 tests. (*) c47c66e... Add -mcpu=power11 tuning support. (*) 00c9f9b... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work166-test' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work166-tar)] Merge commit 'refs/users/meissner/heads/work166-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work16
https://gcc.gnu.org/g:7f03db8d29149b9b3c0a04f849d38649e5917c08 commit 7f03db8d29149b9b3c0a04f849d38649e5917c08 Merge: b0dd90490ee6 1a2e3e0e4240 Author: Michael Meissner Date: Fri May 17 21:05:34 2024 -0400 Merge commit 'refs/users/meissner/heads/work166-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work166-tar Diff:
[gcc/meissner/heads/work166-tar] (8 commits) Merge commit 'refs/users/meissner/heads/work166-tar' of git
The branch 'meissner/heads/work166-tar' was updated to point to: 7f03db8d2914... Merge commit 'refs/users/meissner/heads/work166-tar' of git It previously pointed to: 1a2e3e0e4240... Add ChangeLog.tar and update REVISION. Diff: Summary of changes (added commits): --- 7f03db8... Merge commit 'refs/users/meissner/heads/work166-tar' of git b0dd904... Add ChangeLog.tar and update REVISION. 373ebc4... Update ChangeLog.* (*) a0ccb78... Add -mcpu=future tuning support. (*) 78dc639... Add -mcpu=future support. (*) d69f7b4... Add -mcpu=power11 tests. (*) c47c66e... Add -mcpu=power11 tuning support. (*) 00c9f9b... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work166-tar' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work166-tar)] Add ChangeLog.tar and update REVISION.
https://gcc.gnu.org/g:b0dd90490ee602491f114faf07969e6baf4b9f49 commit b0dd90490ee602491f114faf07969e6baf4b9f49 Author: Michael Meissner Date: Fri May 17 20:47:03 2024 -0400 Add ChangeLog.tar and update REVISION. 2024-05-17 Michael Meissner gcc/ * ChangeLog.tar: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.tar | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar new file mode 100644 index ..3e168fa367eb --- /dev/null +++ b/gcc/ChangeLog.tar @@ -0,0 +1,6 @@ + Branch work166-tar, baseline + +2024-05-17 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 42eef54d0aeb..3b5b120ee37e 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work166 branch +work166-tar branch
[gcc(refs/users/meissner/heads/work166-dmf)] Merge commit 'refs/users/meissner/heads/work166-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work16
https://gcc.gnu.org/g:93ac8e1984dd4f23f79508ab73112adb197dfba2 commit 93ac8e1984dd4f23f79508ab73112adb197dfba2 Merge: 4c7f5203b45e 40164d125941 Author: Michael Meissner Date: Fri May 17 21:03:34 2024 -0400 Merge commit 'refs/users/meissner/heads/work166-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work166-dmf Diff:
[gcc(refs/users/meissner/heads/work166-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:4c7f5203b45e07a82673f95f5dfa8fb6c9dde105 commit 4c7f5203b45e07a82673f95f5dfa8fb6c9dde105 Author: Michael Meissner Date: Fri May 17 20:40:56 2024 -0400 Add ChangeLog.dmf and update REVISION. 2024-05-17 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index ..ab0fdd1054fb --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,6 @@ + Branch work166-dmf, baseline + +2024-05-17 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index 42eef54d0aeb..ee73a03644d7 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work166 branch +work166-dmf branch
[gcc/meissner/heads/work166-dmf] (8 commits) Merge commit 'refs/users/meissner/heads/work166-dmf' of git
The branch 'meissner/heads/work166-dmf' was updated to point to: 93ac8e1984dd... Merge commit 'refs/users/meissner/heads/work166-dmf' of git It previously pointed to: 40164d125941... Add ChangeLog.dmf and update REVISION. Diff: Summary of changes (added commits): --- 93ac8e1... Merge commit 'refs/users/meissner/heads/work166-dmf' of git 4c7f520... Add ChangeLog.dmf and update REVISION. 373ebc4... Update ChangeLog.* (*) a0ccb78... Add -mcpu=future tuning support. (*) 78dc639... Add -mcpu=future support. (*) d69f7b4... Add -mcpu=power11 tests. (*) c47c66e... Add -mcpu=power11 tuning support. (*) 00c9f9b... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work166-dmf' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
