[gcc(refs/users/meissner/heads/work165-tar)] Update ChangeLog.*
https://gcc.gnu.org/g:6365a8475fd30393b104753a1e5a7aa85b031605 commit 6365a8475fd30393b104753a1e5a7aa85b031605 Author: Michael Meissner Date: Fri May 3 22:07:15 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.tar | 56 ++- 1 file changed, 55 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar index 26f27bb12ae..5083f34c4cf 100644 --- a/gcc/ChangeLog.tar +++ b/gcc/ChangeLog.tar @@ -1,6 +1,60 @@ + Branch work165-tar, patch #200 + +Add support for -mtar + +2024-05-03 Michael Meissner + +gcc/ + + * config/rs6000/constraints.md (h constraint): Add tar register to + documentation. + (wt constraint): New constraint. + * config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add -mtar. + (POWERPC_MASKS): Likewise. + * config/rs6000/rs6000.cc (rs6000_reg_names): Add new tar register. + (alt_reg_names): Likewise. + (rs6000_debug_reg_global): Likewise. + (rs6000_init_hard_regno_mode_ok): Likewise. + (rs6000_option_override_internal): Likewise. + (rs6000_conditional_register_usage): Likewise. + (print_operand): Likewise. + (rs6000_debugger_regno): Likewise. + (rs6000_opt_masks): Likewise. + * config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Likewise. + (FiXED_REGISTERS): Likewise. + (CALL_REALLY_USED_REGISTERS): Likewise. + (REG_ALLOC_ORDER): Likewise. + (reg_class): Add new TAR_REGS register class. + (REG_CLASS_NAMES): Likewise. + (REG_CLASS_CONTENTS): Likewise. + (r6000_reg_class_enum): Add RS6000_CONSTRAINT_wt. + (REG_NAMES): Add tar register. + * config/rs6000/rs6000.md (TAR_REGNO): New constant. + (mov_internal): Add support for tar register. + (movcc_): Likewise. + (movsf_hardfloat): Likewise. + (movsd_hardfloat): Likewise. + (mov_softfloat): Likewise. + (mov_hardfloat64): Likewise. + (mov_softfloat64): Likewise. + (@tablejump_insn_normal); Likewise. + (@tablejump_insn_nospec); Likewise. + * config/rs6000/rs6000.opt (-mtar): New option. + * doc/invoke.texi (RS/6000 options): Document -mtar. + * lra-constraints.md (lra_constraints): Print out insn that we can't + generate reloads for. + Branch work165-tar, baseline +Add ChangeLog.tar and update REVISION. + +2024-05-02 Michael Meissner + +gcc/ + + * ChangeLog.tar: New file for branch. + * REVISION: Update. + 2024-05-02 Michael Meissner Clone branch -
[gcc(refs/users/meissner/heads/work165-tar)] Add support for -mtar
https://gcc.gnu.org/g:70c202710f25f02a52d560b5fa814f0b42d5ad4c
commit 70c202710f25f02a52d560b5fa814f0b42d5ad4c
Author: Michael Meissner
Date: Fri May 3 22:04:58 2024 -0400
Add support for -mtar
2024-05-03 Michael Meissner
gcc/
* config/rs6000/constraints.md (h constraint): Add tar register to
documentation.
(wt constraint): New constraint.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add -mtar.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.cc (rs6000_reg_names): Add new tar register.
(alt_reg_names): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_conditional_register_usage): Likewise.
(print_operand): Likewise.
(rs6000_debugger_regno): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Likewise.
(FiXED_REGISTERS): Likewise.
(CALL_REALLY_USED_REGISTERS): Likewise.
(REG_ALLOC_ORDER): Likewise.
(reg_class): Add new TAR_REGS register class.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(r6000_reg_class_enum): Add RS6000_CONSTRAINT_wt.
(REG_NAMES): Add tar register.
* config/rs6000/rs6000.md (TAR_REGNO): New constant.
(mov_internal): Add support for tar register.
(movcc_): Likewise.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
(mov_softfloat): Likewise.
(mov_hardfloat64): Likewise.
(mov_softfloat64): Likewise.
(@tablejump_insn_normal); Likewise.
(@tablejump_insn_nospec); Likewise.
* config/rs6000/rs6000.opt (-mtar): New option.
* doc/invoke.texi (RS/6000 options): Document -mtar.
* lra-constraints.md (lra_constraints): Print out insn that we can't
generate reloads for.
Diff:
---
gcc/config/rs6000/constraints.md | 5 -
gcc/config/rs6000/rs6000-cpus.def | 4 +++-
gcc/config/rs6000/rs6000.cc | 41 +--
gcc/config/rs6000/rs6000.h| 31 +
gcc/config/rs6000/rs6000.md | 23 +++---
gcc/config/rs6000/rs6000.opt | 4
gcc/doc/invoke.texi | 12 ++--
gcc/lra-constraints.cc| 9 ++---
8 files changed, 93 insertions(+), 36 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 369a7b75042..14f0465d7ae 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -57,7 +57,7 @@
"@internal A compatibility alias for @code{wa}.")
(define_register_constraint "h" "SPECIAL_REGS"
- "@internal A special register (@code{vrsave}, @code{ctr}, or @code{lr}).")
+ "@internal A special register (@code{vrsave}, @code{ctr}, @code{lr} or
@code{tar}).")
(define_register_constraint "c" "CTR_REGS"
"The count register, @code{ctr}.")
@@ -91,6 +91,9 @@
"@internal Like @code{r}, if @option{-mpowerpc64} is used; otherwise,
@code{NO_REGS}.")
+(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
+ "The tar register, @code{tar}.")
+
(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
"@internal Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise,
@code{NO_REGS}.")
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index d625dbeb91f..29a5398b16d 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -52,7 +52,8 @@
| OPTION_MASK_CRYPTO \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_QUAD_MEMORY \
-| OPTION_MASK_QUAD_MEMORY_ATOMIC)
+| OPTION_MASK_QUAD_MEMORY_ATOMIC \
+| OPTION_MASK_TAR)
/* ISA masks setting fusion options. */
#define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \
@@ -158,6 +159,7 @@
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL\
+| OPTION_MASK_TAR \
| OPTION_MASK_VSX)
#endif
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 5bb66dca81d..463d27fa61b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1224,8 +1224,8 @@ char rs6000_reg_names[][8] =
[gcc(refs/users/meissner/heads/work165-dmf)] Update ChangeLog.*
https://gcc.gnu.org/g:2504d90098995277aed551c7fb771ce753b76285 commit 2504d90098995277aed551c7fb771ce753b76285 Author: Michael Meissner Date: Fri May 3 21:14:51 2024 -0400 Update ChangeLog.* Diff: --- gcc/ChangeLog.dmf | 449 +- 1 file changed, 448 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf index d94e03e767e..9aab2635c98 100644 --- a/gcc/ChangeLog.dmf +++ b/gcc/ChangeLog.dmf @@ -1,6 +1,453 @@ + Branch work165-dmf, patch #113 + +RFC2677-Add xvrlw support. + +2024-05-03 Michael Meissner + +gcc/ + + * config/rs6000/altivec.md (xvrlw): New insn. + * config/rs6000/rs6000.h (TARGET_XVRLW): New macro. + +gcc/testsuite/ + + * gcc.target/powerpc/vector-rotate-left.c: New test. + + Branch work165-dmf, patch #112 + +RFC2686-Add paddis support. + +2024-05-03 Michael Meissner + +gcc/ + + * config/rs6000/constraints.md (eU): New constraint. + (eV): Likewise. + * config/rs6000/predicates.md (paddis_operand): New predicate. + (paddis_paddi_operand): Likewise. + (add_operand): Add paddis support. + * config/rs6000/rs6000.cc (num_insns_constant_gpr): Add paddis support. + (num_insns_constant_multi): Likewise. + (print_operand): Add %B for paddis support. + * config/rs6000/rs6000.h (TARGET_PADDIS): New macro. + (SIGNED_INTEGER_32BIT_P): Likewise. + * config/rs6000/rs6000.md (isa attribute): Add paddis support. + (enabled attribute); Likewise. + (add3): Likewise. + (adddi3 splitter): New splitter for paddis. + (movdi_internal64): Add paddis support. + (movdi splitter): New splitter for paddis. + +gcc/testsuite/ + + * gcc.target/powerpc/prefixed-addis.c: New test. + + Branch work165-dmf, patch #111 + +RFC2655-Add saturating subtract built-ins. + +This patch adds support for a saturating subtract built-in function that may be +added to a future PowerPC processor. Note, if it is added, the name of the +built-in function may change before GCC 13 is released. If the name changes, +we will submit a patch changing the name. + +I also added support for providing dense math built-in functions, even though +at present, we have not added any new built-in functions for dense math. It is +likely we will want to add new dense math built-in functions as the dense math +support is fleshed out. + +The patches have been tested on both little and big endian systems. Can I check +it into the master branch? + +2024-05-03 Michael Meissner + +gcc/ + + * config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Add support + for flagging invalid use of future built-in functions. + (rs6000_builtin_is_supported): Add support for future built-in + functions. + * config/rs6000/rs6000-builtins.def (__builtin_saturate_subtract32): New + built-in function for -mcpu=future. + (__builtin_saturate_subtract64): Likewise. + * config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add stanzas + for -mcpu=future built-ins. + (stanza_map): Likewise. + (enable_string): Likewise. + (struct attrinfo): Likewise. + (parse_bif_attrs): Likewise. + (write_decls): Likewise. + * config/rs6000/rs6000.md (sat_sub3): Add saturating subtract + built-in insn declarations. + (sat_sub3_dot): Likewise. + (sat_sub3_dot2): Likewise. + * doc/extend.texi (Future PowerPC built-ins): New section. + +gcc/testsuite/ + + * gcc.target/powerpc/subfus-1.c: New test. + * gcc.target/powerpc/subfus-2.c: Likewise. + + Branch work165-dmf, patch #110 + +RFC2656-Support load/store vector with right length. + +This patch adds support for new instructions that may be added to the PowerPC +architecture in the future to enhance the load and store vector with length +instructions. + +The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to use +since the count for the number of bytes must be in the top 8 bits of the GPR +register, instead of the bottom 8 bits. This meant that code generating these +instructions typically had to do a shift left by 56 bits to get the count into +the right position. In a future version of the PowerPC architecture, new +variants of these instructions might be added that expect the count to be in +the bottom 8 bits of the GPR register. These patches add this support to GCC +if the user uses the -mcpu=future option. + +I discovered that the code in rs6000-string.cc to generate ISA 3.1 lxvl/stxvl +future lxvll/stxvll instructions would generate these instructions on 32-bit. +However the patterns for these instructions is only done on 64-bit systems. So +I added a check for 64-bit support before generating the instructions. + +The patches
[gcc(refs/users/meissner/heads/work165-dmf)] RFC2677-Add xvrlw support.
https://gcc.gnu.org/g:f44372f7e53e70b3a18822cbcc9fd024efea1152
commit f44372f7e53e70b3a18822cbcc9fd024efea1152
Author: Michael Meissner
Date: Fri May 3 21:06:39 2024 -0400
RFC2677-Add xvrlw support.
2024-05-03 Michael Meissner
gcc/
* config/rs6000/altivec.md (xvrlw): New insn.
* config/rs6000/rs6000.h (TARGET_XVRLW): New macro.
gcc/testsuite/
* gcc.target/powerpc/vector-rotate-left.c: New test.
Diff:
---
gcc/config/rs6000/altivec.md | 14 +
gcc/config/rs6000/rs6000.h | 3 ++
.../gcc.target/powerpc/vector-rotate-left.c| 34 ++
3 files changed, 51 insertions(+)
diff --git a/gcc/config/rs6000/altivec.md b/gcc/config/rs6000/altivec.md
index bb20441c096..5e802c59b69 100644
--- a/gcc/config/rs6000/altivec.md
+++ b/gcc/config/rs6000/altivec.md
@@ -1883,6 +1883,20 @@
}
[(set_attr "type" "vecperm")])
+;; -mcpu=future adds a vector rotate left word variant. There is no vector
+;; byte/half-word/double-word/quad-word rotate left. This insn occurs before
+;; altivec_vrl and will match for -mcpu=future, while other cpus will
+;; match the generic insn.
+(define_insn "*xvrlw"
+ [(set (match_operand:V4SI 0 "register_operand" "=v,wa")
+ (rotate:V4SI (match_operand:V4SI 1 "register_operand" "v,wa")
+(match_operand:V4SI 2 "register_operand" "v,wa")))]
+ "TARGET_XVRLW"
+ "@
+ vrlw %0,%1,%2
+ xvrlw %x0,%x1,%x2"
+ [(set_attr "type" "vecsimple")])
+
(define_insn "altivec_vrl"
[(set (match_operand:VI2 0 "register_operand" "=v")
(rotate:VI2 (match_operand:VI2 1 "register_operand" "v")
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 1c44726f074..474c47a7959 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -578,6 +578,9 @@ extern int rs6000_vector_align[];
/* Whether we have PADDIS support. */
#define TARGET_PADDIS TARGET_FUTURE
+/* Whether we have XVRLW support. */
+#define TARGET_XVRLW TARGET_FUTURE
+
/* Whether the various reciprocal divide/square root estimate instructions
exist, and whether we should automatically generate code for the instruction
by default. */
diff --git a/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
new file mode 100644
index 000..5a5f3775507
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/vector-rotate-left.c
@@ -0,0 +1,34 @@
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_future_ok } */
+/* { dg-require-effective-target lp64 } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+/* Test whether the xvrl (vector word rotate left using VSX registers insead of
+ Altivec registers is generated. */
+
+#include
+
+typedef vector unsigned int v4si_t;
+
+v4si_t
+rotl_v4si_scalar (v4si_t x, unsigned long n)
+{
+ __asm__ (" # %x0" : "+f" (x));
+ return (x << n) | (x >> (32 - n)); /* xvrlw. */
+}
+
+v4si_t
+rotr_v4si_scalar (v4si_t x, unsigned long n)
+{
+ __asm__ (" # %x0" : "+f" (x));
+ return (x >> n) | (x << (32 - n)); /* xvrlw. */
+}
+
+v4si_t
+rotl_v4si_vector (v4si_t x, v4si_t y)
+{
+ __asm__ (" # %x0" : "+f" (x)); /* xvrlw. */
+ return vec_rl (x, y);
+}
+
+/* { dg-final { scan-assembler-times {\mxvrlw\M} 3 } } */
[gcc(refs/users/meissner/heads/work165-dmf)] RFC2686-Add paddis support.
https://gcc.gnu.org/g:c2f3d78cf66caa49c8379cca1f2604bf1de4b2fc
commit c2f3d78cf66caa49c8379cca1f2604bf1de4b2fc
Author: Michael Meissner
Date: Fri May 3 20:57:14 2024 -0400
RFC2686-Add paddis support.
2024-05-03 Michael Meissner
gcc/
* config/rs6000/constraints.md (eU): New constraint.
(eV): Likewise.
* config/rs6000/predicates.md (paddis_operand): New predicate.
(paddis_paddi_operand): Likewise.
(add_operand): Add paddis support.
* config/rs6000/rs6000.cc (num_insns_constant_gpr): Add paddis
support.
(num_insns_constant_multi): Likewise.
(print_operand): Add %B for paddis support.
* config/rs6000/rs6000.h (TARGET_PADDIS): New macro.
(SIGNED_INTEGER_32BIT_P): Likewise.
* config/rs6000/rs6000.md (isa attribute): Add paddis support.
(enabled attribute); Likewise.
(add3): Likewise.
(adddi3 splitter): New splitter for paddis.
(movdi_internal64): Add paddis support.
(movdi splitter): New splitter for paddis.
gcc/testsuite/
* gcc.target/powerpc/prefixed-addis.c: New test.
Diff:
---
gcc/config/rs6000/constraints.md | 10 +++
gcc/config/rs6000/predicates.md | 52 +++-
gcc/config/rs6000/rs6000.cc | 25 ++
gcc/config/rs6000/rs6000.h| 4 +
gcc/config/rs6000/rs6000.md | 96 ---
gcc/testsuite/gcc.target/powerpc/prefixed-addis.c | 24 ++
6 files changed, 197 insertions(+), 14 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 277a30a8245..4d8d21fd6bb 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -222,6 +222,16 @@
"An IEEE 128-bit constant that can be loaded into VSX registers."
(match_operand 0 "easy_vector_constant_ieee128"))
+(define_constraint "eU"
+ "@internal integer constant that can be loaded with paddis"
+ (and (match_code "const_int")
+ (match_operand 0 "paddis_operand")))
+
+(define_constraint "eV"
+ "@internal integer constant that can be loaded with paddis + paddi"
+ (and (match_code "const_int")
+ (match_operand 0 "paddis_paddi_operand")))
+
;; Floating-point constraints. These two are defined so that insn
;; length attributes can be calculated exactly.
diff --git a/gcc/config/rs6000/predicates.md b/gcc/config/rs6000/predicates.md
index b325000690b..0b7c0bf4b0f 100644
--- a/gcc/config/rs6000/predicates.md
+++ b/gcc/config/rs6000/predicates.md
@@ -369,6 +369,53 @@
return SIGNED_INTEGER_34BIT_P (INTVAL (op));
})
+;; Return 1 if op is a 64-bit constant that uses the paddis instruction
+(define_predicate "paddis_operand"
+ (match_code "const_int")
+{
+ if (!TARGET_PADDIS && TARGET_POWERPC64)
+return 0;
+
+ /* If addi, addis, or paddi can handle the number, don't return true. */
+ HOST_WIDE_INT value = INTVAL (op);
+ if (SIGNED_INTEGER_34BIT_P (value))
+return false;
+
+ /* If the number is too large for padds, return false. */
+ if (!SIGNED_INTEGER_32BIT_P (value >> 32))
+return false;
+
+ /* If the bottom 32-bits are non-zero, paddis can't handle it. */
+ if ((value & HOST_WIDE_INT_C(0x)) != 0)
+return false;
+
+ return true;
+})
+
+;; Return 1 if op is a 64-bit constant that needs the paddis instruction and an
+;; addi/addis/paddi instruction combination.
+(define_predicate "paddis_paddi_operand"
+ (match_code "const_int")
+{
+ if (!TARGET_PADDIS && TARGET_POWERPC64)
+return 0;
+
+ /* If addi, addis, or paddi can handle the number, don't return true. */
+ HOST_WIDE_INT value = INTVAL (op);
+ if (SIGNED_INTEGER_34BIT_P (value))
+return false;
+
+ /* If the number is too large for padds, return false. */
+ if (!SIGNED_INTEGER_32BIT_P (value >> 32))
+return false;
+
+ /* If the bottom 32-bits are zero, we can use paddis alone to handle it. */
+ if ((value & HOST_WIDE_INT_C(0x)) == 0)
+return false;
+
+ return true;
+})
+
;; Return 1 if op is a register that is not special.
;; Disallow (SUBREG:SF (REG:SI)) and (SUBREG:SI (REG:SF)) on VSX systems where
;; you need to be careful in moving a SFmode to SImode and vice versa due to
@@ -1050,7 +1097,10 @@
(if_then_else (match_code "const_int")
(match_test "satisfies_constraint_I (op)
|| satisfies_constraint_L (op)
-|| satisfies_constraint_eI (op)")
+|| satisfies_constraint_eI (op)
+|| satisfies_constraint_eU (op)
+|| satisfies_constraint_eV (op)")
+
(match_operand 0 "gpc_reg_operand")))
;; Return 1 if the operand is either a non-special register, or 0, or -1.
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 4dabf13aee9..160db4bba7a 100644
---
[gcc(refs/users/meissner/heads/work165-dmf)] RFC2655-Add saturating subtract built-ins.
https://gcc.gnu.org/g:050e208c0ee395174512f6248ae173ad152e3cd0
commit 050e208c0ee395174512f6248ae173ad152e3cd0
Author: Michael Meissner
Date: Fri May 3 20:44:50 2024 -0400
RFC2655-Add saturating subtract built-ins.
This patch adds support for a saturating subtract built-in function that
may be
added to a future PowerPC processor. Note, if it is added, the name of the
built-in function may change before GCC 13 is released. If the name
changes,
we will submit a patch changing the name.
I also added support for providing dense math built-in functions, even
though
at present, we have not added any new built-in functions for dense math.
It is
likely we will want to add new dense math built-in functions as the dense
math
support is fleshed out.
The patches have been tested on both little and big endian systems. Can I
check
it into the master branch?
2024-05-03 Michael Meissner
gcc/
* config/rs6000/rs6000-builtin.cc (rs6000_invalid_builtin): Add
support
for flagging invalid use of future built-in functions.
(rs6000_builtin_is_supported): Add support for future built-in
functions.
* config/rs6000/rs6000-builtins.def
(__builtin_saturate_subtract32): New
built-in function for -mcpu=future.
(__builtin_saturate_subtract64): Likewise.
* config/rs6000/rs6000-gen-builtins.cc (enum bif_stanza): Add
stanzas
for -mcpu=future built-ins.
(stanza_map): Likewise.
(enable_string): Likewise.
(struct attrinfo): Likewise.
(parse_bif_attrs): Likewise.
(write_decls): Likewise.
* config/rs6000/rs6000.md (sat_sub3): Add saturating subtract
built-in insn declarations.
(sat_sub3_dot): Likewise.
(sat_sub3_dot2): Likewise.
* doc/extend.texi (Future PowerPC built-ins): New section.
gcc/testsuite/
* gcc.target/powerpc/subfus-1.c: New test.
* gcc.target/powerpc/subfus-2.c: Likewise.
Diff:
---
gcc/config/rs6000/rs6000-builtin.cc | 17
gcc/config/rs6000/rs6000-builtins.def | 10 +
gcc/config/rs6000/rs6000-gen-builtins.cc| 35 ++---
gcc/config/rs6000/rs6000.md | 60 +
gcc/doc/extend.texi | 24
gcc/testsuite/gcc.target/powerpc/subfus-1.c | 32 +++
gcc/testsuite/gcc.target/powerpc/subfus-2.c | 32 +++
7 files changed, 205 insertions(+), 5 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-builtin.cc
b/gcc/config/rs6000/rs6000-builtin.cc
index 4b315cca351..172e5621f54 100644
--- a/gcc/config/rs6000/rs6000-builtin.cc
+++ b/gcc/config/rs6000/rs6000-builtin.cc
@@ -139,6 +139,17 @@ rs6000_invalid_builtin (enum rs6000_gen_builtins fncode)
case ENB_MMA:
error ("%qs requires the %qs option", name, "-mmma");
break;
+case ENB_FUTURE:
+ error ("%qs requires the %qs option", name, "-mcpu=future");
+ break;
+case ENB_FUTURE_64:
+ error ("%qs requires the %qs option and either the %qs or %qs option",
+name, "-mcpu=future", "-m64", "-mpowerpc64");
+ break;
+case ENB_DM:
+ error ("%qs requires the %qs or %qs options", name, "-mcpu=future",
+"-mdense-math");
+ break;
default:
case ENB_ALWAYS:
gcc_unreachable ();
@@ -194,6 +205,12 @@ rs6000_builtin_is_supported (enum rs6000_gen_builtins
fncode)
return TARGET_HTM;
case ENB_MMA:
return TARGET_MMA;
+case ENB_FUTURE:
+ return TARGET_FUTURE;
+case ENB_FUTURE_64:
+ return TARGET_FUTURE && TARGET_POWERPC64;
+case ENB_DM:
+ return TARGET_DENSE_MATH;
default:
gcc_unreachable ();
}
diff --git a/gcc/config/rs6000/rs6000-builtins.def
b/gcc/config/rs6000/rs6000-builtins.def
index 3bc7fed6956..437ab0e09e9 100644
--- a/gcc/config/rs6000/rs6000-builtins.def
+++ b/gcc/config/rs6000/rs6000-builtins.def
@@ -139,6 +139,8 @@
; endian Needs special handling for endianness
; ibmldRestrict usage to the case when TFmode is IBM-128
; ibm128 Restrict usage to the case where __ibm128 is supported or if ibmld
+; future Restrict usage to future instructions
+; dm Restrict usage to dense math
;
; Each attribute corresponds to extra processing required when
; the built-in is expanded. All such special processing should
@@ -4131,3 +4133,11 @@
void __builtin_vsx_stxvp (v256, unsigned long, const v256 *);
STXVP nothing {mma,pair}
+
+[future]
+ const signed int __builtin_saturate_subtract32 (signed int, signed int);
+ SAT_SUBSI sat_subsi3 {}
+
+[future-64]
+ const signed long __builtin_saturate_subtract64 (signed long, signed long);
+ SAT_SUBDI sat_subdi3 {}
diff --git a/gcc/config/rs6000/rs6000-gen-builtins.cc
[gcc(refs/users/meissner/heads/work165-dmf)] RFC2656-Support load/store vector with right length.
https://gcc.gnu.org/g:e3be5e2b224450ef7468af4e04755aa0dc0980ad
commit e3be5e2b224450ef7468af4e04755aa0dc0980ad
Author: Michael Meissner
Date: Fri May 3 20:39:15 2024 -0400
RFC2656-Support load/store vector with right length.
This patch adds support for new instructions that may be added to the
PowerPC
architecture in the future to enhance the load and store vector with length
instructions.
The current instructions (lxvl, lxvll, stxvl, and stxvll) are inconvient to
use
since the count for the number of bytes must be in the top 8 bits of the GPR
register, instead of the bottom 8 bits. This meant that code generating
these
instructions typically had to do a shift left by 56 bits to get the count
into
the right position. In a future version of the PowerPC architecture, new
variants of these instructions might be added that expect the count to be in
the bottom 8 bits of the GPR register. These patches add this support to
GCC
if the user uses the -mcpu=future option.
I discovered that the code in rs6000-string.cc to generate ISA 3.1
lxvl/stxvl
future lxvll/stxvll instructions would generate these instructions on
32-bit.
However the patterns for these instructions is only done on 64-bit systems.
So
I added a check for 64-bit support before generating the instructions.
The patches have been tested on both little and big endian systems. Can I
check
it into the master branch?
2024-05-03 Michael Meissner
gcc/
* config/rs6000/rs6000-string.cc (expand_block_move): Do not
generate
lxvl and stxvl on 32-bit.
* config/rs6000/vsx.md (lxvl): If -mcpu=future, generate the lxvl
with
the shift count automaticaly used in the insn.
(lxvrl): New insn for -mcpu=future.
(lxvrll): Likewise.
(stxvl): If -mcpu=future, generate the stxvl with the shift count
automaticaly used in the insn.
(stxvrl): New insn for -mcpu=future.
(stxvrll): Likewise.
gcc/testsuite/
* gcc.target/powerpc/lxvrl.c: New test.
* lib/target-supports.exp
(check_effective_target_powerpc_future_ok):
New effective target.
Diff:
---
gcc/config/rs6000/rs6000-string.cc | 1 +
gcc/config/rs6000/vsx.md | 122 +--
gcc/testsuite/gcc.target/powerpc/lxvrl.c | 32
gcc/testsuite/lib/target-supports.exp| 12 +++
4 files changed, 146 insertions(+), 21 deletions(-)
diff --git a/gcc/config/rs6000/rs6000-string.cc
b/gcc/config/rs6000/rs6000-string.cc
index e74ccf41937..c6737e66cbe 100644
--- a/gcc/config/rs6000/rs6000-string.cc
+++ b/gcc/config/rs6000/rs6000-string.cc
@@ -2787,6 +2787,7 @@ expand_block_move (rtx operands[], bool might_overlap)
if (TARGET_MMA && TARGET_BLOCK_OPS_UNALIGNED_VSX
&& TARGET_BLOCK_OPS_VECTOR_PAIR
+ && TARGET_POWERPC64
&& bytes >= 32
&& (align >= 256 || !STRICT_ALIGNMENT))
{
diff --git a/gcc/config/rs6000/vsx.md b/gcc/config/rs6000/vsx.md
index f135fa079bd..9520191e613 100644
--- a/gcc/config/rs6000/vsx.md
+++ b/gcc/config/rs6000/vsx.md
@@ -5629,20 +5629,32 @@
DONE;
})
-;; Load VSX Vector with Length
+;; Load VSX Vector with Length. If we have lxvrl, we don't have to do an
+;; explicit shift left into a pseudo.
(define_expand "lxvl"
- [(set (match_dup 3)
-(ashift:DI (match_operand:DI 2 "register_operand")
- (const_int 56)))
- (set (match_operand:V16QI 0 "vsx_register_operand")
- (unspec:V16QI
-[(match_operand:DI 1 "gpc_reg_operand")
- (mem:V16QI (match_dup 1))
- (match_dup 3)]
-UNSPEC_LXVL))]
+ [(use (match_operand:V16QI 0 "vsx_register_operand"))
+ (use (match_operand:DI 1 "gpc_reg_operand"))
+ (use (match_operand:DI 2 "gpc_reg_operand"))]
"TARGET_P9_VECTOR && TARGET_64BIT"
{
- operands[3] = gen_reg_rtx (DImode);
+ rtx shift_len = gen_rtx_ASHIFT (DImode, operands[2], GEN_INT (56));
+ rtx len;
+
+ if (TARGET_FUTURE)
+len = shift_len;
+ else
+{
+ len = gen_reg_rtx (DImode);
+ emit_insn (gen_rtx_SET (len, shift_len));
+}
+
+ rtx dest = operands[0];
+ rtx addr = operands[1];
+ rtx mem = gen_rtx_MEM (V16QImode, addr);
+ rtvec rv = gen_rtvec (3, addr, mem, len);
+ rtx lxvl = gen_rtx_UNSPEC (V16QImode, rv, UNSPEC_LXVL);
+ emit_insn (gen_rtx_SET (dest, lxvl));
+ DONE;
})
(define_insn "*lxvl"
@@ -5666,6 +5678,34 @@
"lxvll %x0,%1,%2"
[(set_attr "type" "vecload")])
+;; For lxvrl and lxvrll, use the combiner to eliminate the shift. The
+;; define_expand for lxvl will already incorporate the shift in generating the
+;; insn. The lxvll buitl-in function required the user to have already done
+;; the shift. Defining lxvrll this way, will optimize cases where the user has
+;; done the shift immediately before the
[gcc(refs/users/meissner/heads/work165-dmf)] RFC2653-PowerPC: Add support for 1, 024 bit DMR registers.
https://gcc.gnu.org/g:7992af1753d9b60cebc5eb360058c04d57053c7a
commit 7992af1753d9b60cebc5eb360058c04d57053c7a
Author: Michael Meissner
Date: Fri May 3 20:31:57 2024 -0400
RFC2653-PowerPC: Add support for 1,024 bit DMR registers.
This patch is a prelimianry patch to add the full 1,024 bit dense math
register
(DMRs) for -mcpu=future. The MMA 512-bit accumulators map onto the top of
the
DMR register.
This patch only adds the new 1,024 bit register support. It does not add
support for any instructions that need 1,024 bit registers instead of 512
bit
registers.
I used the new mode 'TDOmode' to be the opaque mode used for 1,024 bit
registers. The 'wD' constraint added in previous patches is used for these
registers. I added support to do load and store of DMRs via the VSX
registers,
since there are no load/store dense math instructions. I added the new
keyword
'__dmr' to create 1,024 bit types that can be loaded into DMRs. At
present, I
don't have aliases for __dmr512 and __dmr1024 that we've discussed
internally.
The patches have been tested on both little and big endian systems. Can I
check
it into the master branch?
2024-05-03 Michael Meissner
gcc/
* config/rs6000/mma.md (UNSPEC_DM_INSERT512_UPPER): New unspec.
(UNSPEC_DM_INSERT512_LOWER): Likewise.
(UNSPEC_DM_EXTRACT512): Likewise.
(UNSPEC_DMR_RELOAD_FROM_MEMORY): Likewise.
(UNSPEC_DMR_RELOAD_TO_MEMORY): Likewise.
(movtdo): New define_expand and define_insn_and_split to implement
1,024
bit DMR registers.
(movtdo_insert512_upper): New insn.
(movtdo_insert512_lower): Likewise.
(movtdo_extract512): Likewise.
(reload_dmr_from_memory): Likewise.
(reload_dmr_to_memory): Likewise.
* config/rs6000/rs6000-builtin.cc (rs6000_type_string): Add DMR
support.
(rs6000_init_builtins): Add support for __dmr keyword.
* config/rs6000/rs6000-call.cc (rs6000_return_in_memory): Add
support
for TDOmode.
(rs6000_function_arg): Likewise.
* config/rs6000/rs6000-modes.def (TDOmode): New mode.
* config/rs6000/rs6000.cc (rs6000_hard_regno_nregs_internal): Add
support for TDOmode.
(rs6000_hard_regno_mode_ok_uncached): Likewise.
(rs6000_hard_regno_mode_ok): Likewise.
(rs6000_modes_tieable_p): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_setup_reg_addr_masks): Likewise.
(rs6000_init_hard_regno_mode_ok): Add support for TDOmode. Setup
reload
hooks for DMR mode.
(reg_offset_addressing_ok_p): Add support for TDOmode.
(rs6000_emit_move): Likewise.
(rs6000_secondary_reload_simple_move): Likewise.
(rs6000_preferred_reload_class): Likewise.
(rs6000_secondary_reload_class): Likewise.
(rs6000_mangle_type): Add mangling for __dmr type.
(rs6000_dmr_register_move_cost): Add support for TDOmode.
(rs6000_split_multireg_move): Likewise.
(rs6000_invalid_conversion): Likewise.
* config/rs6000/rs6000.h (VECTOR_ALIGNMENT_P): Add TDOmode.
(enum rs6000_builtin_type_index): Add DMR type nodes.
(dmr_type_node): Likewise.
(ptr_dmr_type_node): Likewise.
gcc/testsuite/
* gcc.target/powerpc/dm-1024bit.c: New test.
Diff:
---
gcc/config/rs6000/mma.md | 154 ++
gcc/config/rs6000/rs6000-builtin.cc | 17 +++
gcc/config/rs6000/rs6000-call.cc | 10 +-
gcc/config/rs6000/rs6000-modes.def| 4 +
gcc/config/rs6000/rs6000.cc | 101 -
gcc/config/rs6000/rs6000.h| 6 +-
gcc/testsuite/gcc.target/powerpc/dm-1024bit.c | 63 +++
7 files changed, 321 insertions(+), 34 deletions(-)
diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md
index 2e04eb653fa..8461499e1c3 100644
--- a/gcc/config/rs6000/mma.md
+++ b/gcc/config/rs6000/mma.md
@@ -92,6 +92,11 @@
UNSPEC_MMA_XXMFACC
UNSPEC_MMA_XXMTACC
UNSPEC_MMA_DMSETDMRZ
+ UNSPEC_DM_INSERT512_UPPER
+ UNSPEC_DM_INSERT512_LOWER
+ UNSPEC_DM_EXTRACT512
+ UNSPEC_DMR_RELOAD_FROM_MEMORY
+ UNSPEC_DMR_RELOAD_TO_MEMORY
])
(define_c_enum "unspecv"
@@ -793,3 +798,152 @@
}
[(set_attr "type" "mma")
(set_attr "prefixed" "yes")])
+
+;; TDOmode (__dmr keyword for 1,024 bit registers).
+(define_expand "movtdo"
+ [(set (match_operand:TDO 0 "nonimmediate_operand")
+ (match_operand:TDO 1 "input_operand"))]
+ "TARGET_MMA_DENSE_MATH"
+{
+ rs6000_emit_move (operands[0], operands[1], TDOmode);
+ DONE;
+})
+
+(define_insn_and_split "*movtdo"
+ [(set (match_operand:TDO 0
[gcc(refs/users/meissner/heads/work165-dmf)] RFC2653-Add dense math test for new instruction names.
https://gcc.gnu.org/g:7c3dc8dcd8d5ab0f99607172153e5c521a79b643
commit 7c3dc8dcd8d5ab0f99607172153e5c521a79b643
Author: Michael Meissner
Date: Fri May 3 20:25:28 2024 -0400
RFC2653-Add dense math test for new instruction names.
2024-05-03 Michael Meissner
gcc/testsuite/
* gcc.target/powerpc/dm-double-test.c: New test.
* lib/target-supports.exp (check_effective_target_ppc_dmr_ok): New
target test.
Diff:
---
gcc/testsuite/gcc.target/powerpc/dm-double-test.c | 194 ++
gcc/testsuite/lib/target-supports.exp | 23 +++
2 files changed, 217 insertions(+)
diff --git a/gcc/testsuite/gcc.target/powerpc/dm-double-test.c
b/gcc/testsuite/gcc.target/powerpc/dm-double-test.c
new file mode 100644
index 000..66c19779585
--- /dev/null
+++ b/gcc/testsuite/gcc.target/powerpc/dm-double-test.c
@@ -0,0 +1,194 @@
+/* Test derived from mma-double-1.c, modified for dense math. */
+/* { dg-do compile } */
+/* { dg-require-effective-target powerpc_dense_math_ok } */
+/* { dg-options "-mdejagnu-cpu=future -O2" } */
+
+#include
+#include
+#include
+
+typedef unsigned char vec_t __attribute__ ((vector_size (16)));
+typedef double v4sf_t __attribute__ ((vector_size (16)));
+#define SAVE_ACC(ACC, ldc, J) \
+ __builtin_mma_disassemble_acc (result, ACC); \
+ rowC = (v4sf_t *) [0*ldc+J]; \
+ rowC[0] += result[0]; \
+ rowC = (v4sf_t *) [1*ldc+J]; \
+ rowC[0] += result[1]; \
+ rowC = (v4sf_t *) [2*ldc+J]; \
+ rowC[0] += result[2]; \
+ rowC = (v4sf_t *) [3*ldc+J]; \
+ rowC[0] += result[3];
+
+void
+DM (int m, int n, int k, double *A, double *B, double *C)
+{
+ __vector_quad acc0, acc1, acc2, acc3, acc4, acc5, acc6, acc7;
+ v4sf_t result[4];
+ v4sf_t *rowC;
+ for (int l = 0; l < n; l += 4)
+{
+ double *CO;
+ double *AO;
+ AO = A;
+ CO = C;
+ C += m * 4;
+ for (int j = 0; j < m; j += 16)
+ {
+ double *BO = B;
+ __builtin_mma_xxsetaccz ();
+ __builtin_mma_xxsetaccz ();
+ __builtin_mma_xxsetaccz ();
+ __builtin_mma_xxsetaccz ();
+ __builtin_mma_xxsetaccz ();
+ __builtin_mma_xxsetaccz ();
+ __builtin_mma_xxsetaccz ();
+ __builtin_mma_xxsetaccz ();
+ unsigned long i;
+
+ for (i = 0; i < k; i++)
+ {
+ vec_t *rowA = (vec_t *) & AO[i * 16];
+ __vector_pair rowB;
+ vec_t *rb = (vec_t *) & BO[i * 4];
+ __builtin_mma_assemble_pair (, rb[1], rb[0]);
+ __builtin_mma_xvf64gerpp (, rowB, rowA[0]);
+ __builtin_mma_xvf64gerpp (, rowB, rowA[1]);
+ __builtin_mma_xvf64gerpp (, rowB, rowA[2]);
+ __builtin_mma_xvf64gerpp (, rowB, rowA[3]);
+ __builtin_mma_xvf64gerpp (, rowB, rowA[4]);
+ __builtin_mma_xvf64gerpp (, rowB, rowA[5]);
+ __builtin_mma_xvf64gerpp (, rowB, rowA[6]);
+ __builtin_mma_xvf64gerpp (, rowB, rowA[7]);
+ }
+ SAVE_ACC (, m, 0);
+ SAVE_ACC (, m, 4);
+ SAVE_ACC (, m, 2);
+ SAVE_ACC (, m, 6);
+ SAVE_ACC (, m, 8);
+ SAVE_ACC (, m, 12);
+ SAVE_ACC (, m, 10);
+ SAVE_ACC (, m, 14);
+ AO += k * 16;
+ BO += k * 4;
+ CO += 16;
+ }
+ B += k * 4;
+}
+}
+
+void
+init (double *matrix, int row, int column)
+{
+ for (int j = 0; j < column; j++)
+{
+ for (int i = 0; i < row; i++)
+ {
+ matrix[j * row + i] = (i * 16 + 2 + j) / 0.123;
+ }
+}
+}
+
+void
+init0 (double *matrix, double *matrix1, int row, int column)
+{
+ for (int j = 0; j < column; j++)
+for (int i = 0; i < row; i++)
+ matrix[j * row + i] = matrix1[j * row + i] = 0;
+}
+
+
+void
+print (const char *name, const double *matrix, int row, int column)
+{
+ printf ("Matrix %s has %d rows and %d columns:\n", name, row, column);
+ for (int i = 0; i < row; i++)
+{
+ for (int j = 0; j < column; j++)
+ {
+ printf ("%f ", matrix[j * row + i]);
+ }
+ printf ("\n");
+}
+ printf ("\n");
+}
+
+int
+main (int argc, char *argv[])
+{
+ int rowsA, colsB, common;
+ int i, j, k;
+ int ret = 0;
+
+ for (int t = 16; t <= 128; t += 16)
+{
+ for (int t1 = 4; t1 <= 16; t1 += 4)
+ {
+ rowsA = t;
+ colsB = t1;
+ common = 1;
+ /* printf ("Running test for rows = %d,cols = %d\n", t, t1); */
+ double A[rowsA * common];
+ double B[common * colsB];
+ double C[rowsA * colsB];
+ double D[rowsA * colsB];
+
+
+ init (A, rowsA, common);
+ init (B, common, colsB);
+ init0 (C, D, rowsA, colsB);
+ DM (rowsA, colsB, common, A, B, C);
+
+ for (i = 0; i < colsB; i++)
+ {
+ for (j = 0; j < rowsA; j++)
+ {
+
[gcc(refs/users/meissner/heads/work165-dmf)] RFC2653-PowerPC: Switch to dense math names for all MMA operations.
https://gcc.gnu.org/g:d6ee9c4c5ed2a14f66e32feeffc429d7cd5c0ee2 commit d6ee9c4c5ed2a14f66e32feeffc429d7cd5c0ee2 Author: Michael Meissner Date: Fri May 3 20:23:42 2024 -0400 RFC2653-PowerPC: Switch to dense math names for all MMA operations. This patch changes the assembler instruction names for MMA instructions from the original name used in power10 to the new name when used with the dense math system. I.e. xvf64gerpp becomes dmxvf64gerpp. The assembler will emit the same bits for either spelling. For the non-prefixed MMA instructions, we add a 'dm' prefix in front of the instruction. However, the prefixed instructions have a 'pm' prefix, and we add the 'dm' prefix afterwards. To prevent having two sets of parallel int attributes, we remove the "pm" prefix from the instruction string in the attributes, and add it later, both in the insn name and in the output template. 2024-05-03 Michael Meissner gcc/ * config/rs6000/mma.md (vvi4i4i8): Change the instruction to not have a "pm" prefix. (avvi4i4i8): Likewise. (vvi4i4i2): Likewise. (avvi4i4i2): Likewise. (vvi4i4): Likewise. (avvi4i4): Likewise. (pvi4i2): Likewise. (apvi4i2): Likewise. (vvi4i4i4): Likewise. (avvi4i4i4): Likewise. (mma_): Add support for running on DMF systems, generating the dense math instruction and using the dense math accumulators. (mma_): Likewise. (mma_): Likewise. (mma_): Likewise. (mma_pm): Add support for running on DMF systems, generating the dense math instruction and using the dense math accumulators. Rename the insn with a 'pm' prefix and add either 'pm' or 'pmdm' prefixes based on whether we have the original MMA specification or if we have dense math support. (mma_pm): Likewise. (mma_pm): Likewise. (mma_pm): Likewise. (mma_pm): Likewise. (mma_pm): Likewise. (mma_pm): Likewise. (mma_pm): Likewise. Diff: --- gcc/config/rs6000/mma.md | 157 +++ 1 file changed, 104 insertions(+), 53 deletions(-) diff --git a/gcc/config/rs6000/mma.md b/gcc/config/rs6000/mma.md index ae6e7e9695b..2e04eb653fa 100644 --- a/gcc/config/rs6000/mma.md +++ b/gcc/config/rs6000/mma.md @@ -225,44 +225,47 @@ (UNSPEC_MMA_XVF64GERNP "xvf64gernp") (UNSPEC_MMA_XVF64GERNN "xvf64gernn")]) -(define_int_attr vvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8 "pmxvi4ger8")]) +;; The "pm" prefix is not in these expansions, so that we can generate +;; pmdmxvi4ger8 on systems with dense math registers and xvi4ger8 on systems +;; without dense math registers. +(define_int_attr vvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8 "xvi4ger8")]) -(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP "pmxvi4ger8pp")]) +(define_int_attr avvi4i4i8 [(UNSPEC_MMA_PMXVI4GER8PP "xvi4ger8pp")]) -(define_int_attr vvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2"pmxvi16ger2") -(UNSPEC_MMA_PMXVI16GER2S "pmxvi16ger2s") -(UNSPEC_MMA_PMXVF16GER2"pmxvf16ger2") -(UNSPEC_MMA_PMXVBF16GER2 "pmxvbf16ger2")]) +(define_int_attr vvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2"xvi16ger2") +(UNSPEC_MMA_PMXVI16GER2S "xvi16ger2s") +(UNSPEC_MMA_PMXVF16GER2"xvf16ger2") +(UNSPEC_MMA_PMXVBF16GER2 "xvbf16ger2")]) -(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP "pmxvi16ger2pp") -(UNSPEC_MMA_PMXVI16GER2SPP "pmxvi16ger2spp") -(UNSPEC_MMA_PMXVF16GER2PP "pmxvf16ger2pp") -(UNSPEC_MMA_PMXVF16GER2PN "pmxvf16ger2pn") -(UNSPEC_MMA_PMXVF16GER2NP "pmxvf16ger2np") -(UNSPEC_MMA_PMXVF16GER2NN "pmxvf16ger2nn") -(UNSPEC_MMA_PMXVBF16GER2PP "pmxvbf16ger2pp") -(UNSPEC_MMA_PMXVBF16GER2PN "pmxvbf16ger2pn") -(UNSPEC_MMA_PMXVBF16GER2NP "pmxvbf16ger2np") -(UNSPEC_MMA_PMXVBF16GER2NN "pmxvbf16ger2nn")]) +(define_int_attr avvi4i4i2 [(UNSPEC_MMA_PMXVI16GER2PP "xvi16ger2pp") +(UNSPEC_MMA_PMXVI16GER2SPP "xvi16ger2spp") +(UNSPEC_MMA_PMXVF16GER2PP "xvf16ger2pp") +(UNSPEC_MMA_PMXVF16GER2PN
[gcc(refs/users/meissner/heads/work165-dmf)] RFC2653-Add support for dense math registers.
https://gcc.gnu.org/g:ee62835648847f71e55d04ec088d9b410e701507 commit ee62835648847f71e55d04ec088d9b410e701507 Author: Michael Meissner Date: Fri May 3 20:18:09 2024 -0400 RFC2653-Add support for dense math registers. The MMA subsystem added the notion of accumulator registers as an optional feature of ISA 3.1 (power10). In ISA 3.1, these accumulators overlapped with the VSX registers 0..31, but logically the accumulator registers were separate from the FPR registers. In ISA 3.1, it was anticipated that in future systems, the accumulator registers may no overlap with the FPR registers. This patch adds the support for dense math registers as separate registers. This particular patch does not change the MMA support to use the accumulators within the dense math registers. This patch just adds the basic support for having separate DMRs. The next patch will switch the MMA support to use the accumulators if -mcpu=future is used. For testing purposes, I added an undocumented option '-mdense-math' to enable or disable the dense math support. This patch adds a new constraint (wD). If MMA is selected but dense math is not selected (i.e. -mcpu=power10), the wD constraint will allow access to accumulators that overlap with VSX registers 0..31. If both MMA and dense math are selected (i.e. -mcpu=future), the wD constraint will only allow dense math registers. This patch modifies the existing %A output modifier. If MMA is selected but dense math is not selected, then %A output modifier converts the VSX register number to the accumulator number, by dividing it by 4. If both MMA and dense math are selected, then %A will map the separate DMR registers into 0..7. The intention is that user code using extended asm can be modified to run on both MMA without dense math and MMA with dense math: 1) If possible, don't use extended asm, but instead use the MMA built-in functions; 2) If you do need to write extended asm, change the d constraints targetting accumulators should now use wD; 3) Only use the built-in zero, assemble and disassemble functions create move data between vector quad types and dense math accumulators. I.e. do not use the xxmfacc, xxmtacc, and xxsetaccz directly in the extended asm code. The reason is these instructions assume there is a 1-to-1 correspondence between 4 adjacent FPR registers and an accumulator that overlaps with those instructions. With accumulators now being separate registers, there no longer is a 1-to-1 correspondence. It is possible that the mangling for DMRs and the GDB register numbers may produce other changes in the future. 2024-05-03 Michael Meissner * config/rs6000/mma.md (UNSPEC_MMA_DMSETDMRZ): New unspec. (movxo): Add comments about dense math registers. (movxo_nodm): Rename from movxo and restrict the usage to machines without dense math registers. (movxo_dm): New insn for movxo support for machines with dense math registers. (mma_): Restrict usage to machines without dense math registers. (mma_xxsetaccz): Add a define_expand wrapper, and add support for dense math registers. (mma_dmsetaccz): New insn. * config/rs6000/predicates.md (dmr_operand): New predicate. (accumulator_operand): Add support for dense math registers. * config/rs6000/rs6000-builtin.cc (rs6000_gimple_fold_mma_builtin): Do not issue a de-prime instruction when disassembling a vector quad on a system with dense math registers. * config/rs6000/rs6000-c.cc (rs6000_define_or_undefine_macro): Define __DENSE_MATH__ if we have dense math registers. * config/rs6000/rs6000.cc (enum rs6000_reg_type): Add DMR_REG_TYPE. (enum rs6000_reload_reg_type): Add RELOAD_REG_DMR. (LAST_RELOAD_REG_CLASS): Add support for DMR registers and the wD constraint. (reload_reg_map): Likewise. (rs6000_reg_names): Likewise. (alt_reg_names): Likewise. (rs6000_hard_regno_nregs_internal): Likewise. (rs6000_hard_regno_mode_ok_uncached): Likewise. (rs6000_debug_reg_global): Likewise. (rs6000_setup_reg_addr_masks): Likewise. (rs6000_init_hard_regno_mode_ok): Likewise. (rs6000_secondary_reload_memory): Add support for DMR registers. (rs6000_secondary_reload_simple_move): Likewise. (rs6000_preferred_reload_class): Likewise. (rs6000_secondary_reload_class): Likewise. (print_operand): Make %A handle both FPRs and DMRs.
[gcc(refs/users/meissner/heads/work165-dmf)] RFC2653-Add wD constraint.
https://gcc.gnu.org/g:d2cb7b48c27f62f4508716ac9428f1466b0dd810
commit d2cb7b48c27f62f4508716ac9428f1466b0dd810
Author: Michael Meissner
Date: Fri May 3 20:13:14 2024 -0400
RFC2653-Add wD constraint.
This patch adds a new constraint ('wD') that matches the accumulator
registers
that overlap with VSX registers 0..31 on power10. Future patches will add
the
support for a separate accumulator register class that will be used when the
support for dense math registes is added.
2024-04-08 Michael Meissner
* config/rs6000/constraints.md (wD): New constraint.
* config/rs6000/mma.md (mma_): Prepare for alternate
accumulator
registers. Use wD constraint instead of 'd' constraint. Use
accumulator_operand instead of fpr_reg_operand.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_): Likewise.
(mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0")]
+ [(set (match_operand:XO 0 "accumulator_operand" "=")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0")]
MMA_ACC))]
"TARGET_MMA"
" %A0"
@@ -523,7 +523,7 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
+ [(set (match_operand:XO 0 "accumulator_operand" "=,")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_VV))]
@@ -532,8 +532,8 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ [(set (match_operand:XO 0 "accumulator_operand" "=,")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_AVV))]
@@ -542,7 +542,7 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
+ [(set (match_operand:XO 0 "accumulator_operand" "=,")
(unspec:XO [(match_operand:OO 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")]
MMA_PV))]
@@ -551,8 +551,8 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ [(set (match_operand:XO 0 "accumulator_operand" "=,")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:OO 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")]
MMA_APV))]
@@ -561,7 +561,7 @@
[(set_attr "type" "mma")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
+ [(set (match_operand:XO 0 "accumulator_operand" "=,")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -574,8 +574,8 @@
(set_attr "prefixed" "yes")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ [(set (match_operand:XO 0 "accumulator_operand" "=,")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 3 "vsx_register_operand" "v,?wa")
(match_operand:SI 4 "const_0_to_15_operand" "n,n")
@@ -588,7 +588,7 @@
(set_attr "prefixed" "yes")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
+ [(set (match_operand:XO 0 "accumulator_operand" "=,")
(unspec:XO [(match_operand:V16QI 1 "vsx_register_operand" "v,?wa")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
(match_operand:SI 3 "const_0_to_15_operand" "n,n")
@@ -601,8 +601,8 @@
(set_attr "prefixed" "yes")])
(define_insn "mma_"
- [(set (match_operand:XO 0 "fpr_reg_operand" "=,")
- (unspec:XO [(match_operand:XO 1 "fpr_reg_operand" "0,0")
+ [(set (match_operand:XO 0 "accumulator_operand" "=,")
+ (unspec:XO [(match_operand:XO 1 "accumulator_operand" "0,0")
(match_operand:V16QI 2 "vsx_register_operand" "v,?wa")
[gcc(refs/users/meissner/heads/work165-dmf)] Use vector pair load/store for memcpy with -mcpu=future
https://gcc.gnu.org/g:7b62e438a22c49786f703b3290e741def25a3a73 commit 7b62e438a22c49786f703b3290e741def25a3a73 Author: Michael Meissner Date: Fri May 3 20:07:32 2024 -0400 Use vector pair load/store for memcpy with -mcpu=future In the development for the power10 processor, GCC did not enable using the load vector pair and store vector pair instructions when optimizing things like memory copy. This patch enables using those instructions if -mcpu=future is used. 2024-05-03 Michael Meissner gcc/ * config/rs6000/rs6000-cpus.def (ISA_FUTURE_MASKS_SERVER): Enable using load vector pair and store vector pair instructions for memory copy operations. (POWERPC_MASKS): Make the bit for enabling using load vector pair and store vector pair operations set and reset when the PowerPC processor is changed. Diff: --- gcc/config/rs6000/rs6000-cpus.def | 2 ++ 1 file changed, 2 insertions(+) diff --git a/gcc/config/rs6000/rs6000-cpus.def b/gcc/config/rs6000/rs6000-cpus.def index d625dbeb91f..3604a6f0126 100644 --- a/gcc/config/rs6000/rs6000-cpus.def +++ b/gcc/config/rs6000/rs6000-cpus.def @@ -90,6 +90,7 @@ | OPTION_MASK_POWER11) #define ISA_FUTURE_MASKS_SERVER(ISA_POWER11_MASKS_SERVER \ +| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR\ | OPTION_MASK_FUTURE) /* Flags that need to be turned off if -mno-vsx. */ @@ -120,6 +121,7 @@ /* Mask of all options to set the default isa flags based on -mcpu=. */ #define POWERPC_MASKS (OPTION_MASK_ALTIVEC\ +| OPTION_MASK_BLOCK_OPS_VECTOR_PAIR\ | OPTION_MASK_CMPB \ | OPTION_MASK_CRYPTO \ | OPTION_MASK_DFP \
gcc-wwwdocs branch master updated. 081ae01843bf8ed25ab7135123ab21d817db8fa9
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via 081ae01843bf8ed25ab7135123ab21d817db8fa9 (commit) from ced576434ed310d0afee01d88d0c56f78b4d04c5 (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log - commit 081ae01843bf8ed25ab7135123ab21d817db8fa9 Author: Gerald Pfeifer Date: Sat May 4 01:29:35 2024 +0200 gcc-14: Close as such, not diff --git a/htdocs/gcc-14/porting_to.html b/htdocs/gcc-14/porting_to.html index a20d82c2..13772080 100644 --- a/htdocs/gcc-14/porting_to.html +++ b/htdocs/gcc-14/porting_to.html @@ -514,7 +514,7 @@ be included explicitly when compiling with GCC 14: -Pragma GCC target now affects preprocessor symbols +Pragma GCC target now affects preprocessor symbols The behavior of pragma GCC target and specifically how it affects ISA --- Summary of changes: htdocs/gcc-14/porting_to.html | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) hooks/post-receive -- gcc-wwwdocs
gcc-wwwdocs branch master updated. ced576434ed310d0afee01d88d0c56f78b4d04c5
This is an automated email from the git hooks/post-receive script. It was generated because a ref change was pushed to the repository containing the project "gcc-wwwdocs". The branch, master has been updated via ced576434ed310d0afee01d88d0c56f78b4d04c5 (commit) from d63b0ce2968ddaa335a679ba4595ca582ef76d6d (commit) Those revisions listed above that are new to this repository have not appeared on any other notification email; so we list those revisions in full, below. - Log - commit ced576434ed310d0afee01d88d0c56f78b4d04c5 Author: Jonathan Wakely Date: Fri May 3 16:04:49 2024 +0100 Add caveat to GCC 14 release notes about C warnings-as-errors change diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html index 46a0266d..82906de1 100644 --- a/htdocs/gcc-14/changes.html +++ b/htdocs/gcc-14/changes.html @@ -40,6 +40,11 @@ a work-in-progress. https://gcc.gnu.org/onlinedocs/gcc/Warning-Options.html#index-Wflex-array-member-not-at-end;>-Wflex-array-member-not-at-end to identify all such cases in the source code and modify them. + C: + Certain warnings about are now errors, see + Porting to GCC 14 + for details. + https://gcc.gnu.org/onlinedocs/gcc/Instrumentation-Options.html;>-fcf-protection=[full|branch|return|none|check] is refactored, to override -fcf-protection, -fcf-protection=none needs to be added and then --- Summary of changes: htdocs/gcc-14/changes.html | 5 + 1 file changed, 5 insertions(+) hooks/post-receive -- gcc-wwwdocs
[gcc r15-140] libbacktrace: add DLLS as they are loaded
https://gcc.gnu.org/g:b69dac54ef769a33bcdca6de243c1b08e05c7881
commit r15-140-gb69dac54ef769a33bcdca6de243c1b08e05c7881
Author: Ian Lance Taylor
Date: Fri May 3 15:23:23 2024 -0700
libbacktrace: add DLLS as they are loaded
Patch from Björn Schäpers.
* pecoff.c (struct dll_notification_data): Define.
(LDR_DLL_NOTIFICATION): New typedef.
(LDR_REGISTER_FUNCTION): New typedef.
(struct dll_notification_context): Define.
(dll_notification): New static function.
(backtrace_initialize): Register DLL notification.
Diff:
---
libbacktrace/pecoff.c | 106 ++
1 file changed, 106 insertions(+)
diff --git a/libbacktrace/pecoff.c b/libbacktrace/pecoff.c
index 4f267841178..bbb59e26d7a 100644
--- a/libbacktrace/pecoff.c
+++ b/libbacktrace/pecoff.c
@@ -61,6 +61,34 @@ POSSIBILITY OF SUCH DAMAGE. */
#undef Module32Next
#endif
#endif
+
+#if defined(_ARM_)
+#define NTAPI
+#else
+#define NTAPI __stdcall
+#endif
+
+/* This is a simplified (but binary compatible) version of what Microsoft
+ defines in their documentation. */
+struct dll_notification_data
+{
+ ULONG reserved;
+ /* The name as UNICODE_STRING struct. */
+ PVOID full_dll_name;
+ PVOID base_dll_name;
+ PVOID dll_base;
+ ULONG size_of_image;
+};
+
+#define LDR_DLL_NOTIFICATION_REASON_LOADED 1
+
+typedef LONG NTSTATUS;
+typedef VOID CALLBACK (*LDR_DLL_NOTIFICATION)(ULONG,
+ struct dll_notification_data*,
+ PVOID);
+typedef NTSTATUS NTAPI (*LDR_REGISTER_FUNCTION)(ULONG,
+ LDR_DLL_NOTIFICATION, PVOID,
+ PVOID*);
#endif
/* Coff file header. */
@@ -911,6 +939,53 @@ coff_add (struct backtrace_state *state, int descriptor,
return 0;
}
+#ifdef HAVE_WINDOWS_H
+struct dll_notification_context
+{
+ struct backtrace_state *state;
+ backtrace_error_callback error_callback;
+ void *data;
+};
+
+static VOID CALLBACK
+dll_notification (ULONG reason,
+ struct dll_notification_data *notification_data,
+ PVOID context)
+{
+ char module_name[MAX_PATH];
+ int descriptor;
+ struct dll_notification_context* dll_context =
+(struct dll_notification_context*) context;
+ struct backtrace_state *state = dll_context->state;
+ void *data = dll_context->data;
+ backtrace_error_callback error_callback = dll_context->data;
+ fileline fileline;
+ int found_sym;
+ int found_dwarf;
+ HMODULE module_handle;
+
+ if (reason != LDR_DLL_NOTIFICATION_REASON_LOADED)
+return;
+
+ if (!GetModuleHandleExW ((GET_MODULE_HANDLE_EX_FLAG_FROM_ADDRESS
+ | GET_MODULE_HANDLE_EX_FLAG_UNCHANGED_REFCOUNT),
+ (wchar_t*) notification_data->dll_base,
+ _handle))
+return;
+
+ if (!GetModuleFileNameA ((HMODULE) module_handle, module_name, MAX_PATH - 1))
+return;
+
+ descriptor = backtrace_open (module_name, error_callback, data, NULL);
+
+ if (descriptor < 0)
+return;
+
+ coff_add (state, descriptor, error_callback, data, , _sym,
+ _dwarf, (uintptr_t) module_handle);
+}
+#endif /* defined(HAVE_WINDOWS_H) */
+
/* Initialize the backtrace data we need from an ELF executable. At
the ELF level, all we need to do is find the debug info
sections. */
@@ -933,6 +1008,8 @@ backtrace_initialize (struct backtrace_state *state,
#endif
#ifdef HAVE_WINDOWS_H
+ HMODULE nt_dll_handle;
+
module_handle = (uintptr_t) GetModuleHandle (NULL);
#endif
@@ -980,6 +1057,35 @@ backtrace_initialize (struct backtrace_state *state,
}
#endif
+#ifdef HAVE_WINDOWS_H
+ nt_dll_handle = GetModuleHandleW (L"ntdll.dll");
+ if (nt_dll_handle)
+{
+ LDR_REGISTER_FUNCTION register_func;
+ const char register_name[] = "LdrRegisterDllNotification";
+ register_func = (void*) GetProcAddress (nt_dll_handle,
+ register_name);
+
+ if (register_func)
+ {
+ PVOID cookie;
+ struct dll_notification_context *context
+ = backtrace_alloc (state,
+ sizeof (struct dll_notification_context),
+ error_callback, data);
+
+ if (context)
+ {
+ context->state = state;
+ context->data = data;
+ context->error_callback = error_callback;
+
+ register_func (0, _notification, context, );
+ }
+ }
+}
+#endif /* defined(HAVE_WINDOWS_H) */
+
if (!state->threaded)
{
if (found_sym)
[gcc r15-139] Fix printing COMPOUND_EXPR in .original [PR23872]
https://gcc.gnu.org/g:04f24e44fb14a22516444f70503719f3fda15d6c
commit r15-139-g04f24e44fb14a22516444f70503719f3fda15d6c
Author: Andrew Pinski
Date: Tue Apr 16 17:43:36 2024 -0700
Fix printing COMPOUND_EXPR in .original [PR23872]
Starting with the merge of the openmp branch into the trunk
(r0-73077-g953ff28998b59b), COMPOUND_EXPR started to be printed
as `expr; , expr` which is wrong. This was due to the wrong
conversion of dumping_stmts into `!(flags & TDF_SLIM)`. That is wrong
as we are not dumping stmts at this point (`!(flags & TDF_SLIM)` was always
true for this case as TDF_SLIM case was handled before hand). So switch it
to be always false.
Bootstrapped and tested on x86_64-linux-gnu with no regressions.
gcc/ChangeLog:
PR middle-end/23872
* tree-pretty-print.cc (dump_generic_node ): Fix
calls to dump_generic_node and also remove unreachable code that is
testing
`flags & TDF_SLIM`.
gcc/testsuite/ChangeLog:
* gfortran.dg/gomp/atomic-21.f90: Update testcase for the removal
of `;`.
Signed-off-by: Andrew Pinski
Diff:
---
gcc/testsuite/gfortran.dg/gomp/atomic-21.f90 | 4 ++--
gcc/tree-pretty-print.cc | 24 +++-
2 files changed, 9 insertions(+), 19 deletions(-)
diff --git a/gcc/testsuite/gfortran.dg/gomp/atomic-21.f90
b/gcc/testsuite/gfortran.dg/gomp/atomic-21.f90
index febcdbbacfb..35099294d7a 100644
--- a/gcc/testsuite/gfortran.dg/gomp/atomic-21.f90
+++ b/gcc/testsuite/gfortran.dg/gomp/atomic-21.f90
@@ -56,7 +56,7 @@ subroutine foobar()
endif
! TARGET_EXPR = #pragma omp atomic capture acq_rel
-!TARGET_EXPR = NON_LVALUE_EXPR =
*TARGET_EXPR == oo> ? pp : *TARGET_EXPR ;, if
(TARGET_EXPR )
+!TARGET_EXPR = NON_LVALUE_EXPR =
*TARGET_EXPR == oo> ? pp : *TARGET_EXPR , if
(TARGET_EXPR )
!{
! <<< Unknown tree: void_cst >>>
!}
@@ -66,7 +66,7 @@ subroutine foobar()
!};
!
! { dg-final { scan-tree-dump-times "TARGET_EXPR = #pragma omp
atomic capture acq_rel" 1 "original" } }
-! { dg-final { scan-tree-dump-times "TARGET_EXPR =
NON_LVALUE_EXPR = \\*TARGET_EXPR
== oo> \\? pp : \\*TARGET_EXPR ;, if \\(TARGET_EXPR
\\)" 1 "original" } }
+! { dg-final { scan-tree-dump-times "TARGET_EXPR =
NON_LVALUE_EXPR = \\*TARGET_EXPR
== oo> \\? pp : \\*TARGET_EXPR , if \\(TARGET_EXPR
\\)" 1 "original" } }
! { dg-final { scan-tree-dump-times "<<< Unknown tree: void_cst >>>" 1
"original" } }
! { dg-final { scan-tree-dump-times "qq = TARGET_EXPR ;" 1
"original" } }
diff --git a/gcc/tree-pretty-print.cc b/gcc/tree-pretty-print.cc
index c935a7da7d1..f9ad8562078 100644
--- a/gcc/tree-pretty-print.cc
+++ b/gcc/tree-pretty-print.cc
@@ -2856,31 +2856,21 @@ dump_generic_node (pretty_printer *pp, tree node, int
spc, dump_flags_t flags,
}
dump_generic_node (pp, TREE_OPERAND (node, 0),
- spc, flags, !(flags & TDF_SLIM));
- if (flags & TDF_SLIM)
- newline_and_indent (pp, spc);
- else
- {
- pp_comma (pp);
- pp_space (pp);
- }
+ spc, flags, false);
+ pp_comma (pp);
+ pp_space (pp);
for (tp = _OPERAND (node, 1);
TREE_CODE (*tp) == COMPOUND_EXPR;
tp = _OPERAND (*tp, 1))
{
dump_generic_node (pp, TREE_OPERAND (*tp, 0),
- spc, flags, !(flags & TDF_SLIM));
- if (flags & TDF_SLIM)
- newline_and_indent (pp, spc);
- else
- {
- pp_comma (pp);
- pp_space (pp);
- }
+ spc, flags, false);
+ pp_comma (pp);
+ pp_space (pp);
}
- dump_generic_node (pp, *tp, spc, flags, !(flags & TDF_SLIM));
+ dump_generic_node (pp, *tp, spc, flags, false);
}
break;
[gcc r14-10166] [PATCH] PR modula2/114929 for loop fails to iterate down to zero
https://gcc.gnu.org/g:d811080341adf9d805e3f79a8fd9be2e13bd9848 commit r14-10166-gd811080341adf9d805e3f79a8fd9be2e13bd9848 Author: Gaius Mulley Date: Fri May 3 22:58:11 2024 +0100 [PATCH] PR modula2/114929 for loop fails to iterate down to zero There is a bug in the for loop control code which is exposed when an unsigned type is used in the iterator variable. See gm2/pim/run/pass/testforloopzero[234].mod. The bug is in the calculation of the last iterator value. The bug fix is to avoid using negative expressions when calculating the last iterator value with a negative step value. This patch detects if e1, e2, step value are all constant, in which case the ztype is used internally and there is no overflow. If the last iterator value is held in a variable then it uses a different method to calculate the last iterator depending upon the sign of the step value. gcc/m2/ChangeLog: PR modula2/114929 * gm2-compiler/M2Quads.mod (ForLoopLastIteratorVariable): New procedure. (ForLoopLastIteratorConstant): Ditto. (ForLoopLastIterator): Ditto. (BuildForToByDo): Remove LastIterator calculation and call ForLoopLastIterator instead. (FinalValue): Replace with ... (LastIterator): ... this. gcc/testsuite/ChangeLog: PR modula2/114929 * gm2/pim/run/pass/testforloopzero.mod: New test. * gm2/pim/run/pass/testforloopzero2.mod: New test. * gm2/pim/run/pass/testforloopzero3.mod: New test. * gm2/pim/run/pass/testforloopzero4.mod: New test. (cherry picked from commit a561dc0f6c7085e102fe9e9b6abd7f2138512576) Signed-off-by: Gaius Mulley Diff: --- gcc/m2/gm2-compiler/M2Quads.mod| 191 + gcc/testsuite/gm2/pim/run/pass/testforloopzero.mod | 33 .../gm2/pim/run/pass/testforloopzero2.mod | 35 .../gm2/pim/run/pass/testforloopzero3.mod | 32 .../gm2/pim/run/pass/testforloopzero4.mod | 32 5 files changed, 289 insertions(+), 34 deletions(-) diff --git a/gcc/m2/gm2-compiler/M2Quads.mod b/gcc/m2/gm2-compiler/M2Quads.mod index 8a9a23013b2..3f414e186b2 100644 --- a/gcc/m2/gm2-compiler/M2Quads.mod +++ b/gcc/m2/gm2-compiler/M2Quads.mod @@ -4583,6 +4583,144 @@ BEGIN END BuildForLoopToRangeCheck ; +(* + ForLoopLastIteratorVariable - assigns the last value of the index variable to + symbol LastIterator. + The For Loop is regarded: + + For ident := e1 To e2 By BySym Do + + End +*) + +PROCEDURE ForLoopLastIteratorVariable (LastIterator, e1, e2, BySym, ByType: CARDINAL ; + e1tok, e2tok, bytok: CARDINAL) ; +VAR + PBType, + PositiveBy, + ElseQuad, + t, f : CARDINAL ; +BEGIN + Assert (IsVar (LastIterator)) ; + (* If By > 0 then. *) + (* q+1 if >= by0 q+3. *) + (* q+2 GotoOp q+else. *) + PushTFtok (BySym, ByType, bytok) ; (* BuildRelOp 1st parameter *) + PushT (GreaterEqualTok) ; (* 2nd parameter *) + (* 3rd parameter *) + PushZero (bytok, ByType) ; + BuildRelOp (e2tok) ; (* Choose final expression position. *) + PopBool (t, f) ; + BackPatch (t, NextQuad) ; + + (* LastIterator := ((e2-e1) DIV By) * By + e1. *) + PushTF (LastIterator, GetSType (LastIterator)) ; + PushTFtok (e2, GetSType (e2), e2tok) ; + PushT (MinusTok) ; + PushTFtok (e1, GetSType (e1), e1tok) ; + doBuildBinaryOp (TRUE, FALSE) ; + PushT (DivideTok) ; + PushTFtok (BySym, ByType, bytok) ; + doBuildBinaryOp (FALSE, FALSE) ; + PushT (TimesTok) ; + PushTFtok (BySym, ByType, bytok) ; + doBuildBinaryOp (FALSE, FALSE) ; + PushT (ArithPlusTok) ; + PushTFtok (e1, GetSType (e1), e1tok) ; + doBuildBinaryOp (FALSE, FALSE) ; + BuildForLoopToRangeCheck ; + BuildAssignmentWithoutBounds (e1tok, FALSE, FALSE) ; + GenQuad (GotoOp, NulSym, NulSym, 0) ; + ElseQuad := NextQuad-1 ; + + (* Else. *) + + BackPatch (f, NextQuad) ; + + PushTtok (MinusTok, bytok) ; + PushTFtok (BySym, ByType, bytok) ; + BuildUnaryOp ; + PopTF (PositiveBy, PBType) ; (* PositiveBy := - BySym. *) + + (* LastIterator := e1 - ((e1-e2) DIV PositiveBy) * PositiveBy. *) + PushTF (LastIterator, GetSType (LastIterator)) ; + PushTFtok (e1, GetSType (e1), e1tok) ; + PushT (MinusTok) ; + PushTFtok (e1, GetSType (e1), e1tok) ; + PushT (MinusTok) ; + PushTFtok (e2, GetSType (e2), e2tok) ; + doBuildBinaryOp (TRUE, FALSE) ; + PushT (DivideTok) ; + PushTFtok (PositiveBy, ByType, bytok) ; + doBuildBinaryOp (FALSE, FALSE) ; + PushT (TimesTok) ; + PushTFtok (PositiveBy, ByType, bytok) ; + doBuildBinaryOp
[gcc r14-10165] c++: initializer_list and EH [PR114935]
https://gcc.gnu.org/g:3b4d6b6ecd79df790bf0938dab1f51094f94d777
commit r14-10165-g3b4d6b6ecd79df790bf0938dab1f51094f94d777
Author: Jason Merrill
Date: Fri May 3 09:52:46 2024 -0400
c++: initializer_list and EH [PR114935]
When we initialize an array of a type with a non-trivial destructor, such as
the backing array for the initializer_list, we have a cleanup to destroy any
constructed elements if a later constructor throws. When the array being
created is a variable, the end of that EH region naturally coincides with
the beginning of the EH region for the cleanup for the variable as a whole.
But if the array is a temporary, or a subobject of one, the array cleanup
region lasts for the rest of the full-expression, along with the normal
cleanup for the TARGET_EXPR. As a result, when tata throws we clean it up
twice. Before r14-1705 we avoided this by disabling the array cleanup in
split_nonconstant_init, but after that we don't go through
split_nonconstant_init, so let's handle it in cp_genericize_target_expr.
PR c++/114935
gcc/cp/ChangeLog:
* cp-gimplify.cc (cp_genericize_init): Add flags parm.
(cp_genericize_init_expr): Pass nullptr.
(cp_genericize_target_expr): Handle cleanup flags.
* typeck2.cc (build_disable_temp_cleanup): Factor out of...
(split_nonconstant_init): ...here.
* cp-tree.h (build_disable_temp_cleanup): Declare.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/initlist-eh1.C: New test.
(cherry picked from commit 8f3afb83c879f1bfa722a963a07c06aaf174ef72)
Diff:
---
gcc/cp/cp-tree.h | 1 +
gcc/cp/cp-gimplify.cc | 18
gcc/cp/typeck2.cc | 34 ++-
gcc/testsuite/g++.dg/cpp0x/initlist-eh1.C | 25 +++
4 files changed, 60 insertions(+), 18 deletions(-)
diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h
index bafdf63dc63..a226a0a9fb6 100644
--- a/gcc/cp/cp-tree.h
+++ b/gcc/cp/cp-tree.h
@@ -8406,6 +8406,7 @@ extern int abstract_virtuals_error
(abstract_class_use, tree,
tsubst_flags_t =
tf_warning_or_error);
extern tree store_init_value (tree, tree, vec**, int);
+extern tree build_disable_temp_cleanup (tree);
extern tree split_nonconstant_init (tree, tree);
extern bool check_narrowing(tree, tree, tsubst_flags_t,
bool = false);
diff --git a/gcc/cp/cp-gimplify.cc b/gcc/cp/cp-gimplify.cc
index ab5acd18c99..5cbdf0ea498 100644
--- a/gcc/cp/cp-gimplify.cc
+++ b/gcc/cp/cp-gimplify.cc
@@ -1063,11 +1063,11 @@ any_non_eliding_target_exprs (tree ctor)
the result. */
static void
-cp_genericize_init (tree *replace, tree from, tree to)
+cp_genericize_init (tree *replace, tree from, tree to, vec** flags)
{
tree init = NULL_TREE;
if (TREE_CODE (from) == VEC_INIT_EXPR)
-init = expand_vec_init_expr (to, from, tf_warning_or_error);
+init = expand_vec_init_expr (to, from, tf_warning_or_error, flags);
else if (TREE_CODE (from) == CONSTRUCTOR
&& TREE_SIDE_EFFECTS (from)
&& ((flag_exceptions
@@ -1101,7 +1101,7 @@ cp_genericize_init_expr (tree *stmt_p)
/* Return gets confused if we clobber its INIT_EXPR this soon. */
&& TREE_CODE (to) != RESULT_DECL)
from = TARGET_EXPR_INITIAL (from);
- cp_genericize_init (stmt_p, from, to);
+ cp_genericize_init (stmt_p, from, to, nullptr);
}
/* For a TARGET_EXPR, change the TARGET_EXPR_INITIAL. We will need to use
@@ -1112,9 +1112,19 @@ cp_genericize_target_expr (tree *stmt_p)
{
iloc_sentinel ils = EXPR_LOCATION (*stmt_p);
tree slot = TARGET_EXPR_SLOT (*stmt_p);
+ vec *flags = make_tree_vector ();
cp_genericize_init (_EXPR_INITIAL (*stmt_p),
- TARGET_EXPR_INITIAL (*stmt_p), slot);
+ TARGET_EXPR_INITIAL (*stmt_p), slot, );
gcc_assert (!DECL_INITIAL (slot));
+ for (tree f : flags)
+{
+ /* Once initialization is complete TARGET_EXPR_CLEANUP becomes active, so
+disable any subobject cleanups. */
+ tree d = build_disable_temp_cleanup (f);
+ auto = TARGET_EXPR_INITIAL (*stmt_p);
+ r = add_stmt_to_compound (r, d);
+}
+ release_tree_vector (flags);
}
/* Similar to if (target_expr_needs_replace) replace_decl, but TP is the
diff --git a/gcc/cp/typeck2.cc b/gcc/cp/typeck2.cc
index 2985bfdf9ec..06bad4d3303 100644
--- a/gcc/cp/typeck2.cc
+++ b/gcc/cp/typeck2.cc
@@ -466,6 +466,25 @@ maybe_push_temp_cleanup (tree sub, vec **flags)
}
}
+/* F is something added to a cleanup flags vec by maybe_push_temp_cleanup or
+ build_vec_init. Return the code to disable the cleanup it controls. */
+
+tree
+build_disable_temp_cleanup (tree f)
[gcc r15-138] c++: initializer_list and EH [PR114935]
https://gcc.gnu.org/g:8f3afb83c879f1bfa722a963a07c06aaf174ef72
commit r15-138-g8f3afb83c879f1bfa722a963a07c06aaf174ef72
Author: Jason Merrill
Date: Fri May 3 09:52:46 2024 -0400
c++: initializer_list and EH [PR114935]
When we initialize an array of a type with a non-trivial destructor, such as
the backing array for the initializer_list, we have a cleanup to destroy any
constructed elements if a later constructor throws. When the array being
created is a variable, the end of that EH region naturally coincides with
the beginning of the EH region for the cleanup for the variable as a whole.
But if the array is a temporary, or a subobject of one, the array cleanup
region lasts for the rest of the full-expression, along with the normal
cleanup for the TARGET_EXPR. As a result, when tata throws we clean it up
twice. Before r14-1705 we avoided this by disabling the array cleanup in
split_nonconstant_init, but after that we don't go through
split_nonconstant_init, so let's handle it in cp_genericize_target_expr.
PR c++/114935
gcc/cp/ChangeLog:
* cp-gimplify.cc (cp_genericize_init): Add flags parm.
(cp_genericize_init_expr): Pass nullptr.
(cp_genericize_target_expr): Handle cleanup flags.
* typeck2.cc (build_disable_temp_cleanup): Factor out of...
(split_nonconstant_init): ...here.
* cp-tree.h (build_disable_temp_cleanup): Declare.
gcc/testsuite/ChangeLog:
* g++.dg/cpp0x/initlist-eh1.C: New test.
Diff:
---
gcc/cp/cp-tree.h | 1 +
gcc/cp/cp-gimplify.cc | 18
gcc/cp/typeck2.cc | 34 ++-
gcc/testsuite/g++.dg/cpp0x/initlist-eh1.C | 25 +++
4 files changed, 60 insertions(+), 18 deletions(-)
diff --git a/gcc/cp/cp-tree.h b/gcc/cp/cp-tree.h
index 1ba7054f8bc..52d6841559c 100644
--- a/gcc/cp/cp-tree.h
+++ b/gcc/cp/cp-tree.h
@@ -8411,6 +8411,7 @@ extern int abstract_virtuals_error
(abstract_class_use, tree,
tsubst_flags_t =
tf_warning_or_error);
extern tree store_init_value (tree, tree, vec**, int);
+extern tree build_disable_temp_cleanup (tree);
extern tree split_nonconstant_init (tree, tree);
extern bool check_narrowing(tree, tree, tsubst_flags_t,
bool = false);
diff --git a/gcc/cp/cp-gimplify.cc b/gcc/cp/cp-gimplify.cc
index ab5acd18c99..5cbdf0ea498 100644
--- a/gcc/cp/cp-gimplify.cc
+++ b/gcc/cp/cp-gimplify.cc
@@ -1063,11 +1063,11 @@ any_non_eliding_target_exprs (tree ctor)
the result. */
static void
-cp_genericize_init (tree *replace, tree from, tree to)
+cp_genericize_init (tree *replace, tree from, tree to, vec** flags)
{
tree init = NULL_TREE;
if (TREE_CODE (from) == VEC_INIT_EXPR)
-init = expand_vec_init_expr (to, from, tf_warning_or_error);
+init = expand_vec_init_expr (to, from, tf_warning_or_error, flags);
else if (TREE_CODE (from) == CONSTRUCTOR
&& TREE_SIDE_EFFECTS (from)
&& ((flag_exceptions
@@ -1101,7 +1101,7 @@ cp_genericize_init_expr (tree *stmt_p)
/* Return gets confused if we clobber its INIT_EXPR this soon. */
&& TREE_CODE (to) != RESULT_DECL)
from = TARGET_EXPR_INITIAL (from);
- cp_genericize_init (stmt_p, from, to);
+ cp_genericize_init (stmt_p, from, to, nullptr);
}
/* For a TARGET_EXPR, change the TARGET_EXPR_INITIAL. We will need to use
@@ -1112,9 +1112,19 @@ cp_genericize_target_expr (tree *stmt_p)
{
iloc_sentinel ils = EXPR_LOCATION (*stmt_p);
tree slot = TARGET_EXPR_SLOT (*stmt_p);
+ vec *flags = make_tree_vector ();
cp_genericize_init (_EXPR_INITIAL (*stmt_p),
- TARGET_EXPR_INITIAL (*stmt_p), slot);
+ TARGET_EXPR_INITIAL (*stmt_p), slot, );
gcc_assert (!DECL_INITIAL (slot));
+ for (tree f : flags)
+{
+ /* Once initialization is complete TARGET_EXPR_CLEANUP becomes active, so
+disable any subobject cleanups. */
+ tree d = build_disable_temp_cleanup (f);
+ auto = TARGET_EXPR_INITIAL (*stmt_p);
+ r = add_stmt_to_compound (r, d);
+}
+ release_tree_vector (flags);
}
/* Similar to if (target_expr_needs_replace) replace_decl, but TP is the
diff --git a/gcc/cp/typeck2.cc b/gcc/cp/typeck2.cc
index 2985bfdf9ec..06bad4d3303 100644
--- a/gcc/cp/typeck2.cc
+++ b/gcc/cp/typeck2.cc
@@ -466,6 +466,25 @@ maybe_push_temp_cleanup (tree sub, vec **flags)
}
}
+/* F is something added to a cleanup flags vec by maybe_push_temp_cleanup or
+ build_vec_init. Return the code to disable the cleanup it controls. */
+
+tree
+build_disable_temp_cleanup (tree f)
+{
+ tree d = f;
+ tree i = boolean_false_node;
+ if (TREE_CODE (f) ==
[gcc r15-137] PR modula2/114929 extra for loop iteration count regression tests
https://gcc.gnu.org/g:c943d7b5c40f447b12431df9ad27a47dad95026d
commit r15-137-gc943d7b5c40f447b12431df9ad27a47dad95026d
Author: Gaius Mulley
Date: Fri May 3 20:48:01 2024 +0100
PR modula2/114929 extra for loop iteration count regression tests
This patch introduces three more for loop tests checking the iteration
count using the CHAR and enumeration data types.
gcc/testsuite/ChangeLog:
PR modula2/114929
* gm2/pim/run/pass/testforloopchar.mod: New test.
* gm2/pim/run/pass/testforloopchar2.mod: New test.
* gm2/pim/run/pass/testforloopenum.mod: New test.
Signed-off-by: Gaius Mulley
Diff:
---
gcc/testsuite/gm2/pim/run/pass/testforloopchar.mod | 27 +++
.../gm2/pim/run/pass/testforloopchar2.mod | 27 +++
gcc/testsuite/gm2/pim/run/pass/testforloopenum.mod | 30 ++
3 files changed, 84 insertions(+)
diff --git a/gcc/testsuite/gm2/pim/run/pass/testforloopchar.mod
b/gcc/testsuite/gm2/pim/run/pass/testforloopchar.mod
new file mode 100644
index 000..be26ecb7149
--- /dev/null
+++ b/gcc/testsuite/gm2/pim/run/pass/testforloopchar.mod
@@ -0,0 +1,27 @@
+MODULE testforloopchar ;
+
+FROM libc IMPORT printf, exit ;
+
+PROCEDURE test ;
+VAR
+ ch : CHAR ;
+ count: CARDINAL ;
+BEGIN
+ count := 0 ;
+ FOR ch := 'a' TO 'z' DO
+ INC (count) ;
+ printf ("ch = %c, count = %d\n", ch, count)
+ END ;
+ IF count = 26
+ THEN
+ printf ("passed\n")
+ ELSE
+ printf ("failed\n") ;
+ exit (1)
+ END
+END test ;
+
+
+BEGIN
+ test
+END testforloopchar.
diff --git a/gcc/testsuite/gm2/pim/run/pass/testforloopchar2.mod
b/gcc/testsuite/gm2/pim/run/pass/testforloopchar2.mod
new file mode 100644
index 000..05478b2d5f2
--- /dev/null
+++ b/gcc/testsuite/gm2/pim/run/pass/testforloopchar2.mod
@@ -0,0 +1,27 @@
+MODULE testforloopchar2 ;
+
+FROM libc IMPORT printf, exit ;
+
+PROCEDURE test ;
+VAR
+ ch : CHAR ;
+ count: CARDINAL ;
+BEGIN
+ count := 0 ;
+ FOR ch := 'a' TO 'z' BY CHR (2) DO
+ INC (count) ;
+ printf ("ch = %c, count = %d\n", ch, count)
+ END ;
+ IF count = 13
+ THEN
+ printf ("passed\n")
+ ELSE
+ printf ("failed\n") ;
+ exit (1)
+ END
+END test ;
+
+
+BEGIN
+ test
+END testforloopchar2.
diff --git a/gcc/testsuite/gm2/pim/run/pass/testforloopenum.mod
b/gcc/testsuite/gm2/pim/run/pass/testforloopenum.mod
new file mode 100644
index 000..3855cae0012
--- /dev/null
+++ b/gcc/testsuite/gm2/pim/run/pass/testforloopenum.mod
@@ -0,0 +1,30 @@
+MODULE testforloopenum ;
+
+FROM libc IMPORT printf, exit ;
+
+TYPE
+ colour = (red, green, blue, yellow) ;
+
+PROCEDURE test ;
+VAR
+ c: colour ;
+ count: CARDINAL ;
+BEGIN
+ count := 0 ;
+ FOR c := red TO blue BY colour (2) DO
+ INC (count) ;
+ printf ("c = %d, count = %d\n", c, count)
+ END ;
+ IF count = 2
+ THEN
+ printf ("passed\n")
+ ELSE
+ printf ("failed\n") ;
+ exit (1)
+ END
+END test ;
+
+
+BEGIN
+ test
+END testforloopenum.
[gcc r15-136] c++: Implement __is_pointer built-in trait
https://gcc.gnu.org/g:cb5d904c775ed7172f8dd7565ec7f5395503d06f
commit r15-136-gcb5d904c775ed7172f8dd7565ec7f5395503d06f
Author: Ken Matsui
Date: Sun Jul 9 17:49:08 2023 -0700
c++: Implement __is_pointer built-in trait
This patch implements built-in trait for std::is_pointer.
gcc/cp/ChangeLog:
* cp-trait.def: Define __is_pointer.
* constraint.cc (diagnose_trait_expr): Handle CPTK_IS_POINTER.
* semantics.cc (trait_expr_value): Likewise.
(finish_trait_expr): Likewise.
gcc/testsuite/ChangeLog:
* g++.dg/ext/has-builtin-1.C: Test existence of __is_pointer.
Arrange the order lexically around __is_pointer.
* g++.dg/ext/is_pointer.C: New test.
Signed-off-by: Ken Matsui
Reviewed-by: Jason Merrill
Diff:
---
gcc/cp/constraint.cc | 3 ++
gcc/cp/cp-trait.def | 1 +
gcc/cp/semantics.cc | 4 +++
gcc/testsuite/g++.dg/ext/has-builtin-1.C | 9 --
gcc/testsuite/g++.dg/ext/is_pointer.C| 51
5 files changed, 65 insertions(+), 3 deletions(-)
diff --git a/gcc/cp/constraint.cc b/gcc/cp/constraint.cc
index d9caf546423..5a8aaa70fa6 100644
--- a/gcc/cp/constraint.cc
+++ b/gcc/cp/constraint.cc
@@ -3829,6 +3829,9 @@ diagnose_trait_expr (tree expr, tree args)
case CPTK_IS_POD:
inform (loc, " %qT is not a POD type", t1);
break;
+case CPTK_IS_POINTER:
+ inform (loc, " %qT is not a pointer", t1);
+ break;
case CPTK_IS_POLYMORPHIC:
inform (loc, " %qT is not a polymorphic type", t1);
break;
diff --git a/gcc/cp/cp-trait.def b/gcc/cp/cp-trait.def
index e9347453829..18e2d0f3480 100644
--- a/gcc/cp/cp-trait.def
+++ b/gcc/cp/cp-trait.def
@@ -82,6 +82,7 @@ DEFTRAIT_EXPR (IS_NOTHROW_CONVERTIBLE,
"__is_nothrow_convertible", 2)
DEFTRAIT_EXPR (IS_OBJECT, "__is_object", 1)
DEFTRAIT_EXPR (IS_POINTER_INTERCONVERTIBLE_BASE_OF,
"__is_pointer_interconvertible_base_of", 2)
DEFTRAIT_EXPR (IS_POD, "__is_pod", 1)
+DEFTRAIT_EXPR (IS_POINTER, "__is_pointer", 1)
DEFTRAIT_EXPR (IS_POLYMORPHIC, "__is_polymorphic", 1)
DEFTRAIT_EXPR (IS_REFERENCE, "__is_reference", 1)
DEFTRAIT_EXPR (IS_SAME, "__is_same", 2)
diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc
index 634a324aae7..b8c2bf8771f 100644
--- a/gcc/cp/semantics.cc
+++ b/gcc/cp/semantics.cc
@@ -12588,6 +12588,9 @@ trait_expr_value (cp_trait_kind kind, tree type1, tree
type2)
case CPTK_IS_POD:
return pod_type_p (type1);
+case CPTK_IS_POINTER:
+ return TYPE_PTR_P (type1);
+
case CPTK_IS_POLYMORPHIC:
return CLASS_TYPE_P (type1) && TYPE_POLYMORPHIC_P (type1);
@@ -12827,6 +12830,7 @@ finish_trait_expr (location_t loc, cp_trait_kind kind,
tree type1, tree type2)
case CPTK_IS_MEMBER_OBJECT_POINTER:
case CPTK_IS_MEMBER_POINTER:
case CPTK_IS_OBJECT:
+case CPTK_IS_POINTER:
case CPTK_IS_REFERENCE:
case CPTK_IS_SAME:
case CPTK_IS_SCOPED_ENUM:
diff --git a/gcc/testsuite/g++.dg/ext/has-builtin-1.C
b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
index b2e2f2f694d..4cbe6fe8cea 100644
--- a/gcc/testsuite/g++.dg/ext/has-builtin-1.C
+++ b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
@@ -119,12 +119,15 @@
#if !__has_builtin (__is_object)
# error "__has_builtin (__is_object) failed"
#endif
-#if !__has_builtin (__is_pointer_interconvertible_base_of)
-# error "__has_builtin (__is_pointer_interconvertible_base_of) failed"
-#endif
#if !__has_builtin (__is_pod)
# error "__has_builtin (__is_pod) failed"
#endif
+#if !__has_builtin (__is_pointer)
+# error "__has_builtin (__is_pointer) failed"
+#endif
+#if !__has_builtin (__is_pointer_interconvertible_base_of)
+# error "__has_builtin (__is_pointer_interconvertible_base_of) failed"
+#endif
#if !__has_builtin (__is_polymorphic)
# error "__has_builtin (__is_polymorphic) failed"
#endif
diff --git a/gcc/testsuite/g++.dg/ext/is_pointer.C
b/gcc/testsuite/g++.dg/ext/is_pointer.C
new file mode 100644
index 000..d6e39565950
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ext/is_pointer.C
@@ -0,0 +1,51 @@
+// { dg-do compile { target c++11 } }
+
+#define SA(X) static_assert((X),#X)
+
+SA(!__is_pointer(int));
+SA(__is_pointer(int*));
+SA(__is_pointer(int**));
+
+SA(__is_pointer(const int*));
+SA(__is_pointer(const int**));
+SA(__is_pointer(int* const));
+SA(__is_pointer(int** const));
+SA(__is_pointer(int* const* const));
+
+SA(__is_pointer(volatile int*));
+SA(__is_pointer(volatile int**));
+SA(__is_pointer(int* volatile));
+SA(__is_pointer(int** volatile));
+SA(__is_pointer(int* volatile* volatile));
+
+SA(__is_pointer(const volatile int*));
+SA(__is_pointer(const volatile int**));
+SA(__is_pointer(const int* volatile));
+SA(__is_pointer(volatile int* const));
+SA(__is_pointer(int* const volatile));
+SA(__is_pointer(const int** volatile));
+SA(__is_pointer(volatile int** const));
+SA(__is_pointer(int** const
[gcc r15-135] c++: Implement __is_volatile built-in trait
https://gcc.gnu.org/g:9b51b3e79e4b0533bd2b37dcf734ed4a0739af3c
commit r15-135-g9b51b3e79e4b0533bd2b37dcf734ed4a0739af3c
Author: Ken Matsui
Date: Wed Mar 22 16:26:25 2023 -0700
c++: Implement __is_volatile built-in trait
This patch implements built-in trait for std::is_volatile.
gcc/cp/ChangeLog:
* cp-trait.def: Define __is_volatile.
* constraint.cc (diagnose_trait_expr): Handle CPTK_IS_VOLATILE.
* semantics.cc (trait_expr_value): Likewise.
(finish_trait_expr): Likewise.
gcc/testsuite/ChangeLog:
* g++.dg/ext/has-builtin-1.C: Test existence of __is_volatile.
* g++.dg/ext/is_volatile.C: New test.
Signed-off-by: Ken Matsui
Reviewed-by: Jason Merrill
Diff:
---
gcc/cp/constraint.cc | 3 +++
gcc/cp/cp-trait.def | 1 +
gcc/cp/semantics.cc | 4
gcc/testsuite/g++.dg/ext/has-builtin-1.C | 3 +++
gcc/testsuite/g++.dg/ext/is_volatile.C | 20
5 files changed, 31 insertions(+)
diff --git a/gcc/cp/constraint.cc b/gcc/cp/constraint.cc
index eaf17a50877..d9caf546423 100644
--- a/gcc/cp/constraint.cc
+++ b/gcc/cp/constraint.cc
@@ -3862,6 +3862,9 @@ diagnose_trait_expr (tree expr, tree args)
case CPTK_IS_UNION:
inform (loc, " %qT is not a union", t1);
break;
+case CPTK_IS_VOLATILE:
+ inform (loc, " %qT is not a volatile type", t1);
+ break;
case CPTK_REF_CONSTRUCTS_FROM_TEMPORARY:
inform (loc, " %qT is not a reference that binds to a temporary "
"object of type %qT (direct-initialization)", t1, t2);
diff --git a/gcc/cp/cp-trait.def b/gcc/cp/cp-trait.def
index 36faed9c0b3..e9347453829 100644
--- a/gcc/cp/cp-trait.def
+++ b/gcc/cp/cp-trait.def
@@ -92,6 +92,7 @@ DEFTRAIT_EXPR (IS_TRIVIALLY_ASSIGNABLE,
"__is_trivially_assignable", 2)
DEFTRAIT_EXPR (IS_TRIVIALLY_CONSTRUCTIBLE, "__is_trivially_constructible", -1)
DEFTRAIT_EXPR (IS_TRIVIALLY_COPYABLE, "__is_trivially_copyable", 1)
DEFTRAIT_EXPR (IS_UNION, "__is_union", 1)
+DEFTRAIT_EXPR (IS_VOLATILE, "__is_volatile", 1)
DEFTRAIT_EXPR (REF_CONSTRUCTS_FROM_TEMPORARY,
"__reference_constructs_from_temporary", 2)
DEFTRAIT_EXPR (REF_CONVERTS_FROM_TEMPORARY,
"__reference_converts_from_temporary", 2)
DEFTRAIT_TYPE (REMOVE_CV, "__remove_cv", 1)
diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc
index b4cda21f682..634a324aae7 100644
--- a/gcc/cp/semantics.cc
+++ b/gcc/cp/semantics.cc
@@ -12618,6 +12618,9 @@ trait_expr_value (cp_trait_kind kind, tree type1, tree
type2)
case CPTK_IS_UNION:
return type_code1 == UNION_TYPE;
+case CPTK_IS_VOLATILE:
+ return CP_TYPE_VOLATILE_P (type1);
+
case CPTK_REF_CONSTRUCTS_FROM_TEMPORARY:
return ref_xes_from_temporary (type1, type2, /*direct_init=*/true);
@@ -12828,6 +12831,7 @@ finish_trait_expr (location_t loc, cp_trait_kind kind,
tree type1, tree type2)
case CPTK_IS_SAME:
case CPTK_IS_SCOPED_ENUM:
case CPTK_IS_UNION:
+case CPTK_IS_VOLATILE:
break;
case CPTK_IS_LAYOUT_COMPATIBLE:
diff --git a/gcc/testsuite/g++.dg/ext/has-builtin-1.C
b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
index e3640faeb96..b2e2f2f694d 100644
--- a/gcc/testsuite/g++.dg/ext/has-builtin-1.C
+++ b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
@@ -158,6 +158,9 @@
#if !__has_builtin (__is_union)
# error "__has_builtin (__is_union) failed"
#endif
+#if !__has_builtin (__is_volatile)
+# error "__has_builtin (__is_volatile) failed"
+#endif
#if !__has_builtin (__reference_constructs_from_temporary)
# error "__has_builtin (__reference_constructs_from_temporary) failed"
#endif
diff --git a/gcc/testsuite/g++.dg/ext/is_volatile.C
b/gcc/testsuite/g++.dg/ext/is_volatile.C
new file mode 100644
index 000..80a1cfc880d
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ext/is_volatile.C
@@ -0,0 +1,20 @@
+// { dg-do compile { target c++11 } }
+
+#define SA(X) static_assert((X),#X)
+
+class ClassType { };
+using cClassType = const ClassType;
+using vClassType = volatile ClassType;
+using cvClassType = const volatile ClassType;
+
+// Positive tests.
+SA(__is_volatile(volatile int));
+SA(__is_volatile(const volatile int));
+SA(__is_volatile(vClassType));
+SA(__is_volatile(cvClassType));
+
+// Negative tests.
+SA(!__is_volatile(int));
+SA(!__is_volatile(const int));
+SA(!__is_volatile(ClassType));
+SA(!__is_volatile(cClassType));
[gcc r15-134] c++: Implement __is_const built-in trait
https://gcc.gnu.org/g:7dd8c905219b8e2dfe4ec968a03623989f8f0c80
commit r15-134-g7dd8c905219b8e2dfe4ec968a03623989f8f0c80
Author: Ken Matsui
Date: Tue Mar 21 09:10:52 2023 -0700
c++: Implement __is_const built-in trait
This patch implements built-in trait for std::is_const.
gcc/cp/ChangeLog:
* cp-trait.def: Define __is_const.
* constraint.cc (diagnose_trait_expr): Handle CPTK_IS_CONST.
* semantics.cc (trait_expr_value): Likewise.
(finish_trait_expr): Likewise.
gcc/testsuite/ChangeLog:
* g++.dg/ext/has-builtin-1.C: Test existence of __is_const.
* g++.dg/ext/is_const.C: New test.
Signed-off-by: Ken Matsui
Reviewed-by: Jason Merrill
Diff:
---
gcc/cp/constraint.cc | 3 +++
gcc/cp/cp-trait.def | 1 +
gcc/cp/semantics.cc | 4
gcc/testsuite/g++.dg/ext/has-builtin-1.C | 3 +++
gcc/testsuite/g++.dg/ext/is_const.C | 20
5 files changed, 31 insertions(+)
diff --git a/gcc/cp/constraint.cc b/gcc/cp/constraint.cc
index 8a3b5d80ba7..eaf17a50877 100644
--- a/gcc/cp/constraint.cc
+++ b/gcc/cp/constraint.cc
@@ -3768,6 +3768,9 @@ diagnose_trait_expr (tree expr, tree args)
case CPTK_IS_CLASS:
inform (loc, " %qT is not a class", t1);
break;
+case CPTK_IS_CONST:
+ inform (loc, " %qT is not a const type", t1);
+ break;
case CPTK_IS_CONSTRUCTIBLE:
if (!t2)
inform (loc, " %qT is not default constructible", t1);
diff --git a/gcc/cp/cp-trait.def b/gcc/cp/cp-trait.def
index 394f006f20f..36faed9c0b3 100644
--- a/gcc/cp/cp-trait.def
+++ b/gcc/cp/cp-trait.def
@@ -64,6 +64,7 @@ DEFTRAIT_EXPR (IS_ASSIGNABLE, "__is_assignable", 2)
DEFTRAIT_EXPR (IS_BASE_OF, "__is_base_of", 2)
DEFTRAIT_EXPR (IS_BOUNDED_ARRAY, "__is_bounded_array", 1)
DEFTRAIT_EXPR (IS_CLASS, "__is_class", 1)
+DEFTRAIT_EXPR (IS_CONST, "__is_const", 1)
DEFTRAIT_EXPR (IS_CONSTRUCTIBLE, "__is_constructible", -1)
DEFTRAIT_EXPR (IS_CONVERTIBLE, "__is_convertible", 2)
DEFTRAIT_EXPR (IS_EMPTY, "__is_empty", 1)
diff --git a/gcc/cp/semantics.cc b/gcc/cp/semantics.cc
index d0fa324fe5c..b4cda21f682 100644
--- a/gcc/cp/semantics.cc
+++ b/gcc/cp/semantics.cc
@@ -12532,6 +12532,9 @@ trait_expr_value (cp_trait_kind kind, tree type1, tree
type2)
case CPTK_IS_CLASS:
return NON_UNION_CLASS_TYPE_P (type1);
+case CPTK_IS_CONST:
+ return CP_TYPE_CONST_P (type1);
+
case CPTK_IS_CONSTRUCTIBLE:
return is_xible (INIT_EXPR, type1, type2);
@@ -12814,6 +12817,7 @@ finish_trait_expr (location_t loc, cp_trait_kind kind,
tree type1, tree type2)
case CPTK_IS_ARRAY:
case CPTK_IS_BOUNDED_ARRAY:
case CPTK_IS_CLASS:
+case CPTK_IS_CONST:
case CPTK_IS_ENUM:
case CPTK_IS_FUNCTION:
case CPTK_IS_MEMBER_FUNCTION_POINTER:
diff --git a/gcc/testsuite/g++.dg/ext/has-builtin-1.C
b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
index 02b4b4d745d..e3640faeb96 100644
--- a/gcc/testsuite/g++.dg/ext/has-builtin-1.C
+++ b/gcc/testsuite/g++.dg/ext/has-builtin-1.C
@@ -71,6 +71,9 @@
#if !__has_builtin (__is_class)
# error "__has_builtin (__is_class) failed"
#endif
+#if !__has_builtin (__is_const)
+# error "__has_builtin (__is_const) failed"
+#endif
#if !__has_builtin (__is_constructible)
# error "__has_builtin (__is_constructible) failed"
#endif
diff --git a/gcc/testsuite/g++.dg/ext/is_const.C
b/gcc/testsuite/g++.dg/ext/is_const.C
new file mode 100644
index 000..8a0e8df72a9
--- /dev/null
+++ b/gcc/testsuite/g++.dg/ext/is_const.C
@@ -0,0 +1,20 @@
+// { dg-do compile { target c++11 } }
+
+#define SA(X) static_assert((X),#X)
+
+class ClassType { };
+using cClassType = const ClassType;
+using vClassType = volatile ClassType;
+using cvClassType = const volatile ClassType;
+
+// Positive tests.
+SA(__is_const(const int));
+SA(__is_const(const volatile int));
+SA(__is_const(cClassType));
+SA(__is_const(cvClassType));
+
+// Negative tests.
+SA(!__is_const(int));
+SA(!__is_const(volatile int));
+SA(!__is_const(ClassType));
+SA(!__is_const(vClassType));
[gcc r15-133] RISC-V: miscll comment fixes [NFC]
https://gcc.gnu.org/g:467ca4a195e26dba77e7f62cc1a3d45a4e541c72 commit r15-133-g467ca4a195e26dba77e7f62cc1a3d45a4e541c72 Author: Vineet Gupta Date: Tue Mar 1 03:45:19 2022 -0800 RISC-V: miscll comment fixes [NFC] gcc/ChangeLog: * config/riscv/riscv.cc: Comment updates. * config/riscv/riscv.h: Ditto. Signed-off-by: Vineet Gupta Diff: --- gcc/config/riscv/riscv.cc | 6 -- gcc/config/riscv/riscv.h | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/gcc/config/riscv/riscv.cc b/gcc/config/riscv/riscv.cc index 8ed9df8126a..44945d47fd6 100644 --- a/gcc/config/riscv/riscv.cc +++ b/gcc/config/riscv/riscv.cc @@ -1258,7 +1258,9 @@ riscv_legitimate_constant_p (machine_mode mode ATTRIBUTE_UNUSED, rtx x) return riscv_const_insns (x) > 0; } -/* Implement TARGET_CANNOT_FORCE_CONST_MEM. */ +/* Implement TARGET_CANNOT_FORCE_CONST_MEM. + Return true if X cannot (or should not) be spilled to the + constant pool. */ static bool riscv_cannot_force_const_mem (machine_mode mode ATTRIBUTE_UNUSED, rtx x) @@ -8624,7 +8626,7 @@ riscv_modes_tieable_p (machine_mode mode1, machine_mode mode2) && GET_MODE_CLASS (mode2) == MODE_FLOAT)); } -/* Implement CLASS_MAX_NREGS. */ +/* Implement TARGET_CLASS_MAX_NREGS. */ static unsigned char riscv_class_max_nregs (reg_class_t rclass, machine_mode mode) diff --git a/gcc/config/riscv/riscv.h b/gcc/config/riscv/riscv.h index 7797e67317a..58d0b09bf7d 100644 --- a/gcc/config/riscv/riscv.h +++ b/gcc/config/riscv/riscv.h @@ -315,7 +315,7 @@ ASM_MISA_SPEC - FRAME_POINTER_REGNUM - 1 vl register - 1 vtype register - - 30 unused registers for future expansion + - 28 unused registers for future expansion - 32 vector registers */ #define FIRST_PSEUDO_REGISTER 128
[gcc r15-132] docs: rtl: document GET_MODE_INNER
https://gcc.gnu.org/g:301b95494098024317c2f4603f759fadc8a868ca
commit r15-132-g301b95494098024317c2f4603f759fadc8a868ca
Author: Vineet Gupta
Date: Thu Feb 17 13:49:45 2022 -0800
docs: rtl: document GET_MODE_INNER
gcc/ChangeLog
* doc/rtl.texi: Add entry for GET_MODE_INNER.
Signed-off-by: Vineet Gupta
Diff:
---
gcc/doc/rtl.texi | 7 +++
1 file changed, 7 insertions(+)
diff --git a/gcc/doc/rtl.texi b/gcc/doc/rtl.texi
index 8ea6588cb71..aa10b5235b5 100644
--- a/gcc/doc/rtl.texi
+++ b/gcc/doc/rtl.texi
@@ -1582,6 +1582,13 @@ less than or equal to @code{HOST_BITS_PER_INT}.
@item GET_MODE_ALIGNMENT (@var{m})
Return the required alignment, in bits, for an object of mode @var{m}.
+@findex GET_MODE_INNER
+@item GET_MODE_INNER (@var{m})
+Returns the mode of the basic parts of mode @var{m}. For vector modes
+this is the mode of the vector elements. For complex modes it is the
+mode of the real and imaginary parts. For other modes it is mode @var{m}
+itself.
+
@findex GET_MODE_UNIT_SIZE
@item GET_MODE_UNIT_SIZE (@var{m})
Returns the size in bytes of the subunits of a datum of mode @var{m}.
[gcc(refs/users/meissner/heads/work165-vpair)] Add ChangeLog.vpair and update REVISION.
https://gcc.gnu.org/g:3ab2474bfd72c4a8ee21ebf3361009240e5931ec commit 3ab2474bfd72c4a8ee21ebf3361009240e5931ec Author: Michael Meissner Date: Thu May 2 14:02:24 2024 -0400 Add ChangeLog.vpair and update REVISION. 2024-05-02 Michael Meissner gcc/ * ChangeLog.vpair: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.vpair | 6 ++ gcc/REVISION| 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.vpair b/gcc/ChangeLog.vpair new file mode 100644 index 000..01a40b0cd7f --- /dev/null +++ b/gcc/ChangeLog.vpair @@ -0,0 +1,6 @@ + Branch work165-vpair, baseline + +2024-05-02 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index c1acb0df2c0..446e8bf93ed 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work165 branch +work165-vpair branch
[gcc(refs/users/meissner/heads/work165-vpair)] Merge commit 'refs/users/meissner/heads/work165-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work
https://gcc.gnu.org/g:f2cb37724efa0be05f9096502c262c35ea588de2 commit f2cb37724efa0be05f9096502c262c35ea588de2 Merge: 3ab2474bfd7 127051cce99 Author: Michael Meissner Date: Fri May 3 11:25:43 2024 -0400 Merge commit 'refs/users/meissner/heads/work165-vpair' of git+ssh://gcc.gnu.org/git/gcc into me/work165-vpair Diff:
[gcc/meissner/heads/work165-vpair] (9 commits) Merge commit 'refs/users/meissner/heads/work165-vpair' of g
The branch 'meissner/heads/work165-vpair' was updated to point to: f2cb37724ef... Merge commit 'refs/users/meissner/heads/work165-vpair' of g It previously pointed to: 127051cce99... Add ChangeLog.vpair and update REVISION. Diff: Summary of changes (added commits): --- f2cb377... Merge commit 'refs/users/meissner/heads/work165-vpair' of g 3ab2474... Add ChangeLog.vpair and update REVISION. 8b80d69... Update ChangeLog.* (*) 8f57958... Add -mcpu=future tuning support. (*) 553119d... Add -mcpu=future support. (*) 59236fd... Update ChangeLog.* (*) a545c5b... Add -mcpu=power11 tests. (*) eb2f890... Add -mcpu=power11 tuning support. (*) b5e0d81... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work165-vpair' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work165-test)] Merge commit 'refs/users/meissner/heads/work165-test' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:cc86d6a68a8a187e129b9d5e3cf19e0312cf6866 commit cc86d6a68a8a187e129b9d5e3cf19e0312cf6866 Merge: 7a47b639ae0 23c1e5caf3d Author: Michael Meissner Date: Fri May 3 11:16:41 2024 -0400 Merge commit 'refs/users/meissner/heads/work165-test' of git+ssh://gcc.gnu.org/git/gcc into me/work165-test Diff:
[gcc(refs/users/meissner/heads/work165-test)] Add ChangeLog.test and update REVISION.
https://gcc.gnu.org/g:7a47b639ae07d629c0a0cceebda6099cfc2bfdbf commit 7a47b639ae07d629c0a0cceebda6099cfc2bfdbf Author: Michael Meissner Date: Thu May 2 14:05:38 2024 -0400 Add ChangeLog.test and update REVISION. 2024-05-02 Michael Meissner gcc/ * ChangeLog.test: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.test | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.test b/gcc/ChangeLog.test new file mode 100644 index 000..6f9db439615 --- /dev/null +++ b/gcc/ChangeLog.test @@ -0,0 +1,6 @@ + Branch work165-test, baseline + +2024-05-02 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index c1acb0df2c0..7e21c32ee45 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work165 branch +work165-test branch
[gcc/meissner/heads/work165-test] (9 commits) Merge commit 'refs/users/meissner/heads/work165-test' of gi
The branch 'meissner/heads/work165-test' was updated to point to: cc86d6a68a8... Merge commit 'refs/users/meissner/heads/work165-test' of gi It previously pointed to: 23c1e5caf3d... Add ChangeLog.test and update REVISION. Diff: Summary of changes (added commits): --- cc86d6a... Merge commit 'refs/users/meissner/heads/work165-test' of gi 7a47b63... Add ChangeLog.test and update REVISION. 8b80d69... Update ChangeLog.* (*) 8f57958... Add -mcpu=future tuning support. (*) 553119d... Add -mcpu=future support. (*) 59236fd... Update ChangeLog.* (*) a545c5b... Add -mcpu=power11 tests. (*) eb2f890... Add -mcpu=power11 tuning support. (*) b5e0d81... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work165-test' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work165-tar)] Merge commit 'refs/users/meissner/heads/work165-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work16
https://gcc.gnu.org/g:bf16499088b120a4cb7f9d4b87135b548b8907dc commit bf16499088b120a4cb7f9d4b87135b548b8907dc Merge: 34ad78eca5a 7922492691a Author: Michael Meissner Date: Fri May 3 11:15:20 2024 -0400 Merge commit 'refs/users/meissner/heads/work165-tar' of git+ssh://gcc.gnu.org/git/gcc into me/work165-tar Diff:
[gcc(refs/users/meissner/heads/work165-tar)] Add ChangeLog.tar and update REVISION.
https://gcc.gnu.org/g:34ad78eca5af6d4123109ce2940a3d083dbd5d41 commit 34ad78eca5af6d4123109ce2940a3d083dbd5d41 Author: Michael Meissner Date: Thu May 2 14:03:29 2024 -0400 Add ChangeLog.tar and update REVISION. 2024-05-02 Michael Meissner gcc/ * ChangeLog.tar: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.tar | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.tar b/gcc/ChangeLog.tar new file mode 100644 index 000..26f27bb12ae --- /dev/null +++ b/gcc/ChangeLog.tar @@ -0,0 +1,6 @@ + Branch work165-tar, baseline + +2024-05-02 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index c1acb0df2c0..057e8867862 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work165 branch +work165-tar branch
[gcc/meissner/heads/work165-tar] (9 commits) Merge commit 'refs/users/meissner/heads/work165-tar' of git
The branch 'meissner/heads/work165-tar' was updated to point to: bf16499088b... Merge commit 'refs/users/meissner/heads/work165-tar' of git It previously pointed to: 7922492691a... Add ChangeLog.tar and update REVISION. Diff: Summary of changes (added commits): --- bf16499... Merge commit 'refs/users/meissner/heads/work165-tar' of git 34ad78e... Add ChangeLog.tar and update REVISION. 8b80d69... Update ChangeLog.* (*) 8f57958... Add -mcpu=future tuning support. (*) 553119d... Add -mcpu=future support. (*) 59236fd... Update ChangeLog.* (*) a545c5b... Add -mcpu=power11 tests. (*) eb2f890... Add -mcpu=power11 tuning support. (*) b5e0d81... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work165-tar' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work165-dmf)] Add ChangeLog.dmf and update REVISION.
https://gcc.gnu.org/g:e31a001c546fb798951e7ad0a28429de1b98543f commit e31a001c546fb798951e7ad0a28429de1b98543f Author: Michael Meissner Date: Thu May 2 14:01:24 2024 -0400 Add ChangeLog.dmf and update REVISION. 2024-05-02 Michael Meissner gcc/ * ChangeLog.dmf: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.dmf | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.dmf b/gcc/ChangeLog.dmf new file mode 100644 index 000..d94e03e767e --- /dev/null +++ b/gcc/ChangeLog.dmf @@ -0,0 +1,6 @@ + Branch work165-dmf, baseline + +2024-05-02 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index c1acb0df2c0..84e8cdcc4ef 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work165 branch +work165-dmf branch
[gcc(refs/users/meissner/heads/work165-dmf)] Merge commit 'refs/users/meissner/heads/work165-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work16
https://gcc.gnu.org/g:cbea57ffeba74e6e757ca01c85e2d0e618bc3859 commit cbea57ffeba74e6e757ca01c85e2d0e618bc3859 Merge: e31a001c546 9c86f644695 Author: Michael Meissner Date: Fri May 3 11:13:50 2024 -0400 Merge commit 'refs/users/meissner/heads/work165-dmf' of git+ssh://gcc.gnu.org/git/gcc into me/work165-dmf Diff:
[gcc/meissner/heads/work165-dmf] (9 commits) Merge commit 'refs/users/meissner/heads/work165-dmf' of git
The branch 'meissner/heads/work165-dmf' was updated to point to: cbea57ffeba... Merge commit 'refs/users/meissner/heads/work165-dmf' of git It previously pointed to: 9c86f644695... Add ChangeLog.dmf and update REVISION. Diff: Summary of changes (added commits): --- cbea57f... Merge commit 'refs/users/meissner/heads/work165-dmf' of git e31a001... Add ChangeLog.dmf and update REVISION. 8b80d69... Update ChangeLog.* (*) 8f57958... Add -mcpu=future tuning support. (*) 553119d... Add -mcpu=future support. (*) 59236fd... Update ChangeLog.* (*) a545c5b... Add -mcpu=power11 tests. (*) eb2f890... Add -mcpu=power11 tuning support. (*) b5e0d81... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work165-dmf' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc(refs/users/meissner/heads/work165-bugs)] Merge commit 'refs/users/meissner/heads/work165-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work1
https://gcc.gnu.org/g:fe62f8b6607a7aa4abfc02a61749f12c1b7352c7 commit fe62f8b6607a7aa4abfc02a61749f12c1b7352c7 Merge: 808ff741c17 2b46c7250c1 Author: Michael Meissner Date: Fri May 3 11:12:07 2024 -0400 Merge commit 'refs/users/meissner/heads/work165-bugs' of git+ssh://gcc.gnu.org/git/gcc into me/work165-bugs Diff:
[gcc(refs/users/meissner/heads/work165-bugs)] Add ChangeLog.bugs and update REVISION.
https://gcc.gnu.org/g:808ff741c1713611ece75c2cd17e5f06df902aaf commit 808ff741c1713611ece75c2cd17e5f06df902aaf Author: Michael Meissner Date: Thu May 2 14:04:30 2024 -0400 Add ChangeLog.bugs and update REVISION. 2024-05-02 Michael Meissner gcc/ * ChangeLog.bugs: New file for branch. * REVISION: Update. Diff: --- gcc/ChangeLog.bugs | 6 ++ gcc/REVISION | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/gcc/ChangeLog.bugs b/gcc/ChangeLog.bugs new file mode 100644 index 000..bbfddc4b438 --- /dev/null +++ b/gcc/ChangeLog.bugs @@ -0,0 +1,6 @@ + Branch work165-bugs, baseline + +2024-05-02 Michael Meissner + + Clone branch + diff --git a/gcc/REVISION b/gcc/REVISION index c1acb0df2c0..2d5ce10c39a 100644 --- a/gcc/REVISION +++ b/gcc/REVISION @@ -1 +1 @@ -work165 branch +work165-bugs branch
[gcc/meissner/heads/work165-bugs] (9 commits) Merge commit 'refs/users/meissner/heads/work165-bugs' of gi
The branch 'meissner/heads/work165-bugs' was updated to point to: fe62f8b6607... Merge commit 'refs/users/meissner/heads/work165-bugs' of gi It previously pointed to: 2b46c7250c1... Add ChangeLog.bugs and update REVISION. Diff: Summary of changes (added commits): --- fe62f8b... Merge commit 'refs/users/meissner/heads/work165-bugs' of gi 808ff74... Add ChangeLog.bugs and update REVISION. 8b80d69... Update ChangeLog.* (*) 8f57958... Add -mcpu=future tuning support. (*) 553119d... Add -mcpu=future support. (*) 59236fd... Update ChangeLog.* (*) a545c5b... Add -mcpu=power11 tests. (*) eb2f890... Add -mcpu=power11 tuning support. (*) b5e0d81... Add -mcpu=power11 support. (*) (*) This commit already exists in another branch. Because the reference `refs/users/meissner/heads/work165-bugs' matches your hooks.email-new-commits-only configuration, no separate email is sent for this commit.
[gcc r14-10164] Revert "tree-optimization/114921 - _Float16 -> __bf16 isn't noop"
https://gcc.gnu.org/g:db447ec808e997bd13a849d9b3076792afb888cb commit r14-10164-gdb447ec808e997bd13a849d9b3076792afb888cb Author: Richard Biener Date: Fri May 3 16:03:14 2024 +0200 Revert "tree-optimization/114921 - _Float16 -> __bf16 isn't noop" This reverts commit fa7e05d90bb672b58424ddbe37a05a0fd0949b35. Diff: --- gcc/tree-vect-stmts.cc | 19 --- 1 file changed, 8 insertions(+), 11 deletions(-) diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc index 7e571968a59..f8d8636b139 100644 --- a/gcc/tree-vect-stmts.cc +++ b/gcc/tree-vect-stmts.cc @@ -5955,17 +5955,14 @@ vectorizable_assignment (vec_info *vinfo, if (!vectype_in) vectype_in = get_vectype_for_scalar_type (vinfo, TREE_TYPE (op), slp_node); - /* We can handle VIEW_CONVERT conversions that do not change the number - of elements or the vector size or other conversions when the component - mode keeps the same. */ - if (!vectype_in - || maybe_ne (TYPE_VECTOR_SUBPARTS (vectype_in), nunits) - || (code == VIEW_CONVERT_EXPR - && maybe_ne (GET_MODE_SIZE (TYPE_MODE (vectype)), - GET_MODE_SIZE (TYPE_MODE (vectype_in - || (CONVERT_EXPR_CODE_P (code) - && (TYPE_MODE (TREE_TYPE (vectype)) - != TYPE_MODE (TREE_TYPE (vectype_in) + /* We can handle NOP_EXPR conversions that do not change the number + of elements or the vector size. */ + if ((CONVERT_EXPR_CODE_P (code) + || code == VIEW_CONVERT_EXPR) + && (!vectype_in + || maybe_ne (TYPE_VECTOR_SUBPARTS (vectype_in), nunits) + || maybe_ne (GET_MODE_SIZE (TYPE_MODE (vectype)), + GET_MODE_SIZE (TYPE_MODE (vectype_in) return false; if (VECTOR_BOOLEAN_TYPE_P (vectype) != VECTOR_BOOLEAN_TYPE_P (vectype_in))
[gcc r13-8683] tree-optimization/114736 - SLP DFS walk issue
https://gcc.gnu.org/g:0624852a3ea684f6b9dabea864bcb45e31304728
commit r13-8683-g0624852a3ea684f6b9dabea864bcb45e31304728
Author: Richard Biener
Date: Tue Apr 16 11:33:48 2024 +0200
tree-optimization/114736 - SLP DFS walk issue
The following fixes a DFS walk issue when identifying to be ignored
latch edges. We have (bogus) SLP_TREE_REPRESENTATIVEs for VEC_PERM
nodes so those have to be explicitly ignored as possibly being PHIs.
PR tree-optimization/114736
* tree-vect-slp.cc (vect_optimize_slp_pass::is_cfg_latch_edge):
Do not consider VEC_PERM_EXPRs as PHI use.
* gfortran.dg/vect/pr114736.f90: New testcase.
(cherry picked from commit f949481a1f7ab973608a4ffcc0e342ab5a74e8e4)
Diff:
---
gcc/testsuite/gfortran.dg/vect/pr114736.f90 | 14 ++
gcc/tree-vect-slp.cc| 3 ++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gfortran.dg/vect/pr114736.f90
b/gcc/testsuite/gfortran.dg/vect/pr114736.f90
new file mode 100644
index 000..cdbfb6f415a
--- /dev/null
+++ b/gcc/testsuite/gfortran.dg/vect/pr114736.f90
@@ -0,0 +1,14 @@
+! { dg-do compile }
+! { dg-additional-options "-O3" }
+
+SUBROUTINE MY_ROUTINE (N, A, B )
+IMPLICIT NONE
+INTEGER, INTENT(IN):: N
+COMPLEX, INTENT(IN):: A(N)
+COMPLEX, INTENT(OUT) :: B(N)
+INTEGER :: II
+B(:) = (1.,0.)
+DO II = 1, N-1
+B(II) = A(N-II+1) / A(N-II)
+ENDDO
+END SUBROUTINE MY_ROUTINE
diff --git a/gcc/tree-vect-slp.cc b/gcc/tree-vect-slp.cc
index e4d3cb89e6f..a72dd787a34 100644
--- a/gcc/tree-vect-slp.cc
+++ b/gcc/tree-vect-slp.cc
@@ -4126,7 +4126,8 @@ vect_optimize_slp_pass::is_cfg_latch_edge (graph_edge *ud)
{
slp_tree use = m_vertices[ud->src].node;
slp_tree def = m_vertices[ud->dest].node;
- if (SLP_TREE_DEF_TYPE (use) != vect_internal_def
+ if ((SLP_TREE_DEF_TYPE (use) != vect_internal_def
+ || SLP_TREE_CODE (use) == VEC_PERM_EXPR)
|| SLP_TREE_DEF_TYPE (def) != vect_internal_def)
return false;
[gcc r13-8684] tree-optimization/114749 - reset partial vector decision for no-SLP retry
https://gcc.gnu.org/g:704b15e277a8792ac4cd6008ee08bec4b047a3e6 commit r13-8684-g704b15e277a8792ac4cd6008ee08bec4b047a3e6 Author: Richard Biener Date: Wed Apr 17 10:40:04 2024 +0200 tree-optimization/114749 - reset partial vector decision for no-SLP retry The following makes sure to reset LOOP_VINFO_USING_PARTIAL_VECTORS_P to its default of false when re-trying without SLP as otherwise analysis may run into bogus asserts. PR tree-optimization/114749 * tree-vect-loop.cc (vect_analyze_loop_2): Reset LOOP_VINFO_USING_PARTIAL_VECTORS_P when re-trying without SLP. (cherry picked from commit bf2b5231312e1cea45732cb8df6ffa2b2c9115b6) Diff: --- gcc/tree-vect-loop.cc | 1 + 1 file changed, 1 insertion(+) diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc index 73caeb283e3..8bb2e3ff1c8 100644 --- a/gcc/tree-vect-loop.cc +++ b/gcc/tree-vect-loop.cc @@ -2957,6 +2957,7 @@ again: LOOP_VINFO_VERSIONING_THRESHOLD (loop_vinfo) = 0; LOOP_VINFO_CAN_USE_PARTIAL_VECTORS_P (loop_vinfo) = saved_can_use_partial_vectors_p; + LOOP_VINFO_USING_PARTIAL_VECTORS_P (loop_vinfo) = false; goto start_over; }
[gcc r13-8681] lto/114655 - -flto=4 at link time doesn't override -flto=auto at compile time
https://gcc.gnu.org/g:d040606257a579f120271dcd2af62a3458a7856e
commit r13-8681-gd040606257a579f120271dcd2af62a3458a7856e
Author: Richard Biener
Date: Tue Apr 9 14:25:57 2024 +0200
lto/114655 - -flto=4 at link time doesn't override -flto=auto at compile
time
The following adjusts -flto option processing in lto-wrapper to have
link-time -flto override any compile time setting.
PR lto/114655
* lto-wrapper.cc (merge_flto_options): Add force argument.
(merge_and_complain): Do not force here.
(run_gcc): But here to make the link-time -flto option override
any compile-time one.
(cherry picked from commit 32fb04adae90a0ea68e64e8fc3cb04b613b2e9f3)
Diff:
---
gcc/lto-wrapper.cc | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/gcc/lto-wrapper.cc b/gcc/lto-wrapper.cc
index 5186d040ce0..ce4b3f29a86 100644
--- a/gcc/lto-wrapper.cc
+++ b/gcc/lto-wrapper.cc
@@ -218,15 +218,18 @@ find_option (vec ,
cl_decoded_option *option)
return find_option (options, option->opt_index);
}
-/* Merge -flto FOPTION into vector of DECODED_OPTIONS. */
+/* Merge -flto FOPTION into vector of DECODED_OPTIONS. If FORCE is true
+ then FOPTION overrides previous settings. */
static void
merge_flto_options (vec _options,
- cl_decoded_option *foption)
+ cl_decoded_option *foption, bool force)
{
int existing_opt = find_option (decoded_options, foption);
if (existing_opt == -1)
decoded_options.safe_push (*foption);
+ else if (force)
+decoded_options[existing_opt].arg = foption->arg;
else
{
if (strcmp (foption->arg, decoded_options[existing_opt].arg) != 0)
@@ -493,7 +496,7 @@ merge_and_complain (vec _options,
break;
case OPT_flto_:
- merge_flto_options (decoded_options, foption);
+ merge_flto_options (decoded_options, foption, false);
break;
}
}
@@ -1549,8 +1552,8 @@ run_gcc (unsigned argc, char *argv[])
break;
case OPT_flto_:
- /* Merge linker -flto= option with what we have in IL files. */
- merge_flto_options (fdecoded_options, option);
+ /* Override IL file settings with a linker -flto= option. */
+ merge_flto_options (fdecoded_options, option, true);
if (strcmp (option->arg, "jobserver") == 0)
jobserver_requested = true;
break;
[gcc r13-8682] gcov-profile/114715 - missing coverage for switch
https://gcc.gnu.org/g:5a3cc62dbb45185dd1ca32caec80d57a320ec5a0
commit r13-8682-g5a3cc62dbb45185dd1ca32caec80d57a320ec5a0
Author: Richard Biener
Date: Mon Apr 15 11:09:17 2024 +0200
gcov-profile/114715 - missing coverage for switch
The following avoids missing coverage for the line of a switch statement
which happens when gimplification emits a BIND_EXPR wrapping the switch
as that prevents us from setting locations on the containing statements
via annotate_all_with_location. Instead set the location of the GIMPLE
switch directly.
PR gcov-profile/114715
* gimplify.cc (gimplify_switch_expr): Set the location of the
GIMPLE switch.
* gcc.misc-tests/gcov-24.c: New testcase.
(cherry picked from commit 9d573f71e80e9f6f4aac912fc8fc128aa2697e3a)
Diff:
---
gcc/gimplify.cc| 1 +
gcc/testsuite/gcc.misc-tests/gcov-24.c | 30 ++
2 files changed, 31 insertions(+)
diff --git a/gcc/gimplify.cc b/gcc/gimplify.cc
index afaff18ef15..f855252475f 100644
--- a/gcc/gimplify.cc
+++ b/gcc/gimplify.cc
@@ -2764,6 +2764,7 @@ gimplify_switch_expr (tree *expr_p, gimple_seq *pre_p)
switch_stmt = gimple_build_switch (SWITCH_COND (switch_expr),
default_case, labels);
+ gimple_set_location (switch_stmt, EXPR_LOCATION (switch_expr));
/* For the benefit of -Wimplicit-fallthrough, if switch_body_seq
ends with a GIMPLE_LABEL holding SWITCH_BREAK_LABEL_P LABEL_DECL,
wrap the GIMPLE_SWITCH up to that GIMPLE_LABEL into a GIMPLE_BIND,
diff --git a/gcc/testsuite/gcc.misc-tests/gcov-24.c
b/gcc/testsuite/gcc.misc-tests/gcov-24.c
new file mode 100644
index 000..395099bd7ae
--- /dev/null
+++ b/gcc/testsuite/gcc.misc-tests/gcov-24.c
@@ -0,0 +1,30 @@
+/* { dg-options "-fprofile-arcs -ftest-coverage" } */
+/* { dg-do run { target native } } */
+
+int main()
+{
+ int a = 1;
+ int b = 2;
+ int c = -3;
+ switch(a) /* count(1) */
+{
+case 1: /* count(1) */
+c = 3;
+switch(b) { /* count(1) */
+ case 1: /* count(#) */
+ c = 4;
+ break;
+ case 2: /* count(1) */
+ c = 5;
+ break;
+}
+break;
+case 2: /* count(#) */
+c = 6;
+break;
+default: /* count(#) */
+break;
+}
+}
+
+/* { dg-final { run-gcov gcov-24.c } } */
[gcc r13-8680] tree-optimization/114733 - neg induction fails for 1 element vectors
https://gcc.gnu.org/g:b3f9f10e03c570074a517dcfe9df8d3eeddd6aca
commit r13-8680-gb3f9f10e03c570074a517dcfe9df8d3eeddd6aca
Author: Richard Biener
Date: Tue Apr 16 10:46:03 2024 +0200
tree-optimization/114733 - neg induction fails for 1 element vectors
The neg induction vectorization code isn't prepared to deal with
single element vectors.
PR tree-optimization/114733
* tree-vect-loop.cc (vectorizable_nonlinear_induction): Reject
neg induction vectorization of single element vectors.
* gcc.dg/vect/pr114733.c: New testcase.
(cherry picked from commit 45a41ace55d0ffb1097e374868242329788ec82a)
Diff:
---
gcc/testsuite/gcc.dg/vect/pr114733.c | 20
gcc/tree-vect-loop.cc| 2 ++
2 files changed, 22 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/vect/pr114733.c
b/gcc/testsuite/gcc.dg/vect/pr114733.c
new file mode 100644
index 000..219cbf20469
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/pr114733.c
@@ -0,0 +1,20 @@
+/* { dg-additional-options "-O3" } */
+
+#include "tree-vect.h"
+
+long b = 1;
+signed char c;
+int d[25];
+
+int main()
+{
+ check_vect ();
+ for (signed char g = 0; g < 8; g += 1)
+for (short h = 0; h < 25; h += 2) {
+ b *= -1;
+ c ^= d[h];
+}
+ if (b != 1)
+abort ();
+ return 0;
+}
diff --git a/gcc/tree-vect-loop.cc b/gcc/tree-vect-loop.cc
index 31ced32126e..73caeb283e3 100644
--- a/gcc/tree-vect-loop.cc
+++ b/gcc/tree-vect-loop.cc
@@ -8944,6 +8944,8 @@ vectorizable_nonlinear_induction (loop_vec_info
loop_vinfo,
switch (induction_type)
{
case vect_step_op_neg:
+ if (maybe_eq (TYPE_VECTOR_SUBPARTS (vectype), 1u))
+ return false;
if (TREE_CODE (init_expr) != INTEGER_CST
&& TREE_CODE (init_expr) != REAL_CST)
{
[gcc r13-8679] tree-optimization/114485 - neg induction with partial vectors
https://gcc.gnu.org/g:a676581ddc49a6ead8edced7bb4b92aeceebde56
commit r13-8679-ga676581ddc49a6ead8edced7bb4b92aeceebde56
Author: Richard Biener
Date: Thu Apr 4 10:00:51 2024 +0200
tree-optimization/114485 - neg induction with partial vectors
We can't use vect_update_ivs_after_vectorizer for partial vectors,
the following fixes vect_can_peel_nonlinear_iv_p accordingly.
PR tree-optimization/114485
* tree-vect-loop-manip.cc (vect_can_peel_nonlinear_iv_p):
vect_step_op_neg isn't OK for partial vectors but only
for unknown niter.
* gcc.dg/vect/pr114485.c: New testcase.
(cherry picked from commit 85621f98d245004a6c9787dde21e0acc17ab2c50)
Diff:
---
gcc/testsuite/gcc.dg/vect/pr114485.c | 18 ++
gcc/tree-vect-loop-manip.cc | 17 ++---
2 files changed, 28 insertions(+), 7 deletions(-)
diff --git a/gcc/testsuite/gcc.dg/vect/pr114485.c
b/gcc/testsuite/gcc.dg/vect/pr114485.c
new file mode 100644
index 000..6536806e350
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/pr114485.c
@@ -0,0 +1,18 @@
+#include "tree-vect.h"
+
+int b, c = 8, d;
+int e[23];
+int main()
+{
+ check_vect ();
+
+ int *h = e;
+ for (int i = 1; i < b + 21; i += 2)
+{
+ c *= -1;
+ d = h[i] ? i : 0;
+}
+ if (c != 8)
+abort ();
+ return 0;
+}
diff --git a/gcc/tree-vect-loop-manip.cc b/gcc/tree-vect-loop-manip.cc
index 767b19b15a1..9049a4b01e4 100644
--- a/gcc/tree-vect-loop-manip.cc
+++ b/gcc/tree-vect-loop-manip.cc
@@ -1401,17 +1401,20 @@ vect_can_peel_nonlinear_iv_p (loop_vec_info loop_vinfo,
For shift, when shift mount >= precision, there would be UD.
For mult, don't known how to generate
init_expr * pow (step, niters) for variable niters.
- For neg, it should be ok, since niters of vectorized main loop
- will always be multiple of 2. */
- if ((!LOOP_VINFO_NITERS_KNOWN_P (loop_vinfo)
- || !LOOP_VINFO_VECT_FACTOR (loop_vinfo).is_constant ())
- && induction_type != vect_step_op_neg)
+ For neg unknown niters are ok, since niters of vectorized main loop
+ will always be multiple of 2.
+ See also PR113163, PR114196 and PR114485. */
+ if (!LOOP_VINFO_VECT_FACTOR (loop_vinfo).is_constant ()
+ || LOOP_VINFO_USING_PARTIAL_VECTORS_P (loop_vinfo)
+ || (!LOOP_VINFO_NITERS_KNOWN_P (loop_vinfo)
+ && induction_type != vect_step_op_neg))
{
if (dump_enabled_p ())
dump_printf_loc (MSG_MISSED_OPTIMIZATION, vect_location,
"Peeling for epilogue is not supported"
-" for nonlinear induction except neg"
-" when iteration count is unknown.\n");
+" for this nonlinear induction"
+" when iteration count is unknown or"
+" when using partial vectorization.\n");
return false;
}
[gcc r14-10163] libstdc++: Update powerpc-linux-gnu baseline_symbols
https://gcc.gnu.org/g:d7c06a80b54486117a72fb2e7b007ad1838d6d0e commit r14-10163-gd7c06a80b54486117a72fb2e7b007ad1838d6d0e Author: Andreas Schwab Date: Sat Feb 3 14:00:41 2024 +0100 libstdc++: Update powerpc-linux-gnu baseline_symbols * config/abi/post/powerpc-linux-gnu/baseline_symbols.txt: Update. * config/abi/post/powerpc64-linux-gnu/32/baseline_symbols.txt: Update. Diff: --- .../post/powerpc-linux-gnu/baseline_symbols.txt| 98 ++ .../powerpc64-linux-gnu/32/baseline_symbols.txt| 98 ++ 2 files changed, 196 insertions(+) diff --git a/libstdc++-v3/config/abi/post/powerpc-linux-gnu/baseline_symbols.txt b/libstdc++-v3/config/abi/post/powerpc-linux-gnu/baseline_symbols.txt index 0209003243a..c38386543b6 100644 --- a/libstdc++-v3/config/abi/post/powerpc-linux-gnu/baseline_symbols.txt +++ b/libstdc++-v3/config/abi/post/powerpc-linux-gnu/baseline_symbols.txt @@ -497,7 +497,12 @@ FUNC:_ZNKSt11__timepunctIwE7_M_daysEPPKw@@GLIBCXX_3.4 FUNC:_ZNKSt11__timepunctIwE8_M_am_pmEPPKw@@GLIBCXX_3.4 FUNC:_ZNKSt11__timepunctIwE9_M_monthsEPPKw@@GLIBCXX_3.4 FUNC:_ZNKSt11logic_error4whatEv@@GLIBCXX_3.4 +FUNC:_ZNKSt12__basic_fileIcE13native_handleEv@@GLIBCXX_3.4.33 FUNC:_ZNKSt12__basic_fileIcE7is_openEv@@GLIBCXX_3.4 +FUNC:_ZNKSt12__shared_ptrINSt10filesystem28recursive_directory_iterator10_Dir_stackELN9__gnu_cxx12_Lock_policyE2EEcvbEv@@GLIBCXX_3.4.31 +FUNC:_ZNKSt12__shared_ptrINSt10filesystem4_DirELN9__gnu_cxx12_Lock_policyE2EEcvbEv@@GLIBCXX_3.4.31 +FUNC:_ZNKSt12__shared_ptrINSt10filesystem7__cxx1128recursive_directory_iterator10_Dir_stackELN9__gnu_cxx12_Lock_policyE2EEcvbEv@@GLIBCXX_3.4.31 +FUNC:_ZNKSt12__shared_ptrINSt10filesystem7__cxx114_DirELN9__gnu_cxx12_Lock_policyE2EEcvbEv@@GLIBCXX_3.4.31 FUNC:_ZNKSt12bad_weak_ptr4whatEv@@GLIBCXX_3.4.15 FUNC:_ZNKSt12future_error4whatEv@@GLIBCXX_3.4.14 FUNC:_ZNKSt12strstreambuf6pcountEv@@GLIBCXX_3.4 @@ -810,6 +815,13 @@ FUNC:_ZNKSt5ctypeIwE8do_widenEPKcS2_Pw@@GLIBCXX_3.4 FUNC:_ZNKSt5ctypeIwE8do_widenEc@@GLIBCXX_3.4 FUNC:_ZNKSt5ctypeIwE9do_narrowEPKwS2_cPc@@GLIBCXX_3.4 FUNC:_ZNKSt5ctypeIwE9do_narrowEwc@@GLIBCXX_3.4 +FUNC:_ZNKSt6chrono4tzdb11locate_zoneESt17basic_string_viewIcSt11char_traitsIcEE@@GLIBCXX_3.4.31 +FUNC:_ZNKSt6chrono4tzdb12current_zoneEv@@GLIBCXX_3.4.31 +FUNC:_ZNKSt6chrono9time_zone15_M_get_sys_infoENS_10time_pointINS_3_V212system_clockENS_8durationIxSt5ratioILx1ELx1EE@@GLIBCXX_3.4.31 +FUNC:_ZNKSt6chrono9time_zone17_M_get_local_infoENS_10time_pointINS_7local_tENS_8durationIxSt5ratioILx1ELx1EE@@GLIBCXX_3.4.31 +FUNC:_ZNKSt6chrono9tzdb_list14const_iteratordeEv@@GLIBCXX_3.4.31 +FUNC:_ZNKSt6chrono9tzdb_list5beginEv@@GLIBCXX_3.4.31 +FUNC:_ZNKSt6chrono9tzdb_list5frontEv@@GLIBCXX_3.4.31 FUNC:_ZNKSt6locale2id5_M_idEv@@GLIBCXX_3.4 FUNC:_ZNKSt6locale4nameB5cxx11Ev@@GLIBCXX_3.4.21 FUNC:_ZNKSt6locale4nameEv@@GLIBCXX_3.4 @@ -3285,9 +3297,18 @@ FUNC:_ZNSt6__norm15_List_node_base7_M_hookEPS0_@@GLIBCXX_3.4.14 FUNC:_ZNSt6__norm15_List_node_base7reverseEv@@GLIBCXX_3.4.9 FUNC:_ZNSt6__norm15_List_node_base8transferEPS0_S1_@@GLIBCXX_3.4.9 FUNC:_ZNSt6__norm15_List_node_base9_M_unhookEv@@GLIBCXX_3.4.14 +FUNC:_ZNSt6chrono11locate_zoneESt17basic_string_viewIcSt11char_traitsIcEE@@GLIBCXX_3.4.31 +FUNC:_ZNSt6chrono11reload_tzdbEv@@GLIBCXX_3.4.31 +FUNC:_ZNSt6chrono12current_zoneEv@@GLIBCXX_3.4.31 FUNC:_ZNSt6chrono12system_clock3nowEv@@GLIBCXX_3.4.11 +FUNC:_ZNSt6chrono13get_tzdb_listEv@@GLIBCXX_3.4.31 +FUNC:_ZNSt6chrono14remote_versionB5cxx11Ev@@GLIBCXX_3.4.31 FUNC:_ZNSt6chrono3_V212steady_clock3nowEv@@GLIBCXX_3.4.19 FUNC:_ZNSt6chrono3_V212system_clock3nowEv@@GLIBCXX_3.4.19 +FUNC:_ZNSt6chrono8get_tzdbEv@@GLIBCXX_3.4.31 +FUNC:_ZNSt6chrono9tzdb_list11erase_afterENS0_14const_iteratorE@@GLIBCXX_3.4.31 +FUNC:_ZNSt6chrono9tzdb_list14const_iteratorppEi@@GLIBCXX_3.4.31 +FUNC:_ZNSt6chrono9tzdb_list14const_iteratorppEv@@GLIBCXX_3.4.31 FUNC:_ZNSt6gslice8_IndexerC1EjRKSt8valarrayIjES4_@@GLIBCXX_3.4 FUNC:_ZNSt6gslice8_IndexerC2EjRKSt8valarrayIjES4_@@GLIBCXX_3.4 FUNC:_ZNSt6locale11_M_coalesceERKS_S1_i@@GLIBCXX_3.4 @@ -3384,6 +3405,7 @@ FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@@GLIBCX FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEjjPKcj@@GLIBCXX_3.4.21 FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_S_compareEjj@@GLIBCXX_3.4.21 FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_capacityEj@@GLIBCXX_3.4.21 +FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_S_allocateERS3_j@@GLIBCXX_3.4.32 FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderC1EPcOS3_@@GLIBCXX_3.4.23 FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderC1EPcRKS3_@@GLIBCXX_3.4.21 FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderC2EPcOS3_@@GLIBCXX_3.4.23 @@ -3403,6 +3425,7 @@ FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13_S_copy_charsEPcPKcS
[gcc r15-131] testsuite: fix analyzer C++ failures on Solaris [PR111475]
https://gcc.gnu.org/g:5219414f3cde3c1037e289a6654cd722cfa75dea commit r15-131-g5219414f3cde3c1037e289a6654cd722cfa75dea Author: David Malcolm Date: Fri May 3 09:05:29 2024 -0400 testsuite: fix analyzer C++ failures on Solaris [PR111475] As part of PR analyzer/96395, these patches moved testcases from gcc.dg/analyzer to c-c++-common/analyzer: - r14-3503-g55f6a7d949abc7 - r14-3823-g50b5199cff6908 - r14-6564-gae034b9106fbdd Unfortunately this led to numerous g++ testsuite failures on Solaris, tracked as PR analyzer/111475. Almost all of the failures are due to standard library differences where including a C standard library on C++ e.g. leads to the plain symbols referencing the symbols "std::" via a "using" declaration, whereas I had written the code expecting them to use symbols in the root namespace. The analyzer has special-case handling of many functions by name. This patch generalizes such handling to also match against functions in "std::" for all of the cases I found in the testsuite (via manual inspection of the preprocessed test cases against Solaris headers). This fixes cases where the analyzer was failing to "know about" the behavior of such functions. Other such failures are due to "std::" prefixes appearing in names of functions in the output, leading to mismatches against expected output. The patch adds regexes to some cases, and moves some other cases back from c-c++-common to gcc.dg where the dg-multiline syntax isn't expressive enough. Various "fd-*.c" failures relate to Solaris's socket-handling functions not being marked with "noexcept", where due to PR analyzer/97111 we mishandle the exception-handling edges in the CFG, leading to leak false positives. The patch works around this by adding -fno-exceptions to these cases, pending a proper fix for PR analyzer/97111. gcc/analyzer/ChangeLog: PR analyzer/111475 * analyzer.cc (is_special_named_call_p): Add "look_in_std" param. (is_std_function_p): Make non-static. * analyzer.h (is_special_named_call_p): Add optional "look_in_std" param. (is_std_function_p): New decl. * engine.cc (stmt_requires_new_enode_p): Look for both "signal" and "std::signal". * kf.cc (register_known_functions): Add various "std::" copies of the known functions. * known-function-manager.cc (known_function_manager::~known_function_manager): Clean up m_std_ns_map_id_to_kf. (known_function_manager::add_std_ns): New. (known_function_manager::get_match): Also look for known "std::" functions. (known_function_manager::get_by_identifier_in_std_ns): New. * known-function-manager.h (known_function_manager::add_std_ns): New decl. (known_function_manager::get_by_identifier_in_std_ns): New decl. (known_function_manager::m_std_ns_map_id_to_kf): New field. * sm-file.cc (register_known_file_functions): Add various "std::" copies of the known functions. * sm-malloc.cc (malloc_state_machine::on_stmt): Handle "std::realloc". * sm-signal.cc (signal_unsafe_p): Consider "std::" copies of the functions as also being async-signal-unsafe. (signal_state_machine::on_stmt): Consider "std::signal". gcc/testsuite/ChangeLog: PR analyzer/111475 * c-c++-common/analyzer/fd-glibc-byte-stream-socket.c: Add -fno-exceptions for now. * c-c++-common/analyzer/fd-manpage-getaddrinfo-client.c: Likewise. * c-c++-common/analyzer/fd-mappage-getaddrinfo-server.c: Rename to... * c-c++-common/analyzer/fd-manpage-getaddrinfo-server.c: ...this, and add -fno-exceptions for now. * c-c++-common/analyzer/fd-socket-meaning.c: Add -fno-exceptions for now. * c-c++-common/analyzer/fd-symbolic-socket.c: Likewise. * c-c++-common/analyzer/flexible-array-member-1.c: Use regexp to handle C vs C++ differences in spelling of function name, which could have a "std::" prefix on some targets. * c-c++-common/analyzer/pr106539.c: Likewise. * c-c++-common/analyzer/malloc-ipa-8-unchecked.c: Move back to... * gcc.dg/analyzer/malloc-ipa-8-unchecked.c: ...here, dropping attempt to generalize output for C vs C++. * c-c++-common/analyzer/signal-4a.c: Move back to... * gcc.dg/analyzer/signal-4a.c: ...here, dropping attempt to generalize output for C vs C++. * c-c++-common/analyzer/signal-4b.c: Move back to... * gcc.dg/analyzer/signal-4b.c: ...here, dropping attempt to generalize
[gcc r14-10162] RISC-V: Add testcase for pr114734
https://gcc.gnu.org/g:796319476e4fd6813e8319061bc3a8f19b355e35
commit r14-10162-g796319476e4fd6813e8319061bc3a8f19b355e35
Author: Patrick O'Neill
Date: Tue Apr 30 13:26:45 2024 -0700
RISC-V: Add testcase for pr114734
gcc/testsuite/ChangeLog:
PR middle-end/114734
* gcc.target/riscv/rvv/autovec/pr114734.c: New test.
Signed-off-by: Patrick O'Neill
(cherry picked from commit ff4dc8b10a421cdb0c56f7f8c238609de4f9fbe2)
Diff:
---
.../gcc.target/riscv/rvv/autovec/pr114734.c| 25 ++
1 file changed, 25 insertions(+)
diff --git a/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
new file mode 100644
index 000..b605d992aa1
--- /dev/null
+++ b/gcc/testsuite/gcc.target/riscv/rvv/autovec/pr114734.c
@@ -0,0 +1,25 @@
+/* { dg-do run } */
+/* { dg-require-effective-target riscv_v } */
+/* { dg-options { -march=rv64gcv_zvl256b -mabi=lp64d -fwhole-program -O3
-mrvv-vector-bits=zvl } } */
+
+int f[18];
+int g[18];
+int h[18][18][18];
+int a[324];
+long b[18];
+int *i = g;
+int (*j)[18][18] = h;
+int z;
+int main() {
+ for (int m = 0; m < 18; ++m)
+f[m] = 3;
+ for (int m = 0; m < 18; m += 1)
+for (int n = 0; n < 18; n += 3) {
+ a[m * 8 + n] = j[m][m][0] ? i[n] : 0;
+ b[n] = f[n] ? -i[m] : 0;
+}
+ for (long n = 0; n < 8; ++n)
+z = a[n];
+ if (b[15] != 0)
+__builtin_abort();
+}
[gcc r14-10161] middle-end/114734 - wrong code with expand_call_mem_ref
https://gcc.gnu.org/g:5c42872b2a08a742f061809c7650e0c62dd7a9f3
commit r14-10161-g5c42872b2a08a742f061809c7650e0c62dd7a9f3
Author: Richard Biener
Date: Fri Apr 26 15:47:13 2024 +0200
middle-end/114734 - wrong code with expand_call_mem_ref
When expand_call_mem_ref looks at the definition of the address
argument to eventually expand a _MEM_REF argument together
with a masked load it fails to honor constraints imposed by SSA
coalescing decisions. The following fixes this.
PR middle-end/114734
* internal-fn.cc (expand_call_mem_ref): Use
get_gimple_for_ssa_name to get at the def stmt of the address
argument to honor SSA coalescing constraints.
(cherry picked from commit 4d3a5618de5a949c61605f545f90e81bc502)
Diff:
---
gcc/internal-fn.cc | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/gcc/internal-fn.cc b/gcc/internal-fn.cc
index 2c764441cde..0a7053c2286 100644
--- a/gcc/internal-fn.cc
+++ b/gcc/internal-fn.cc
@@ -53,6 +53,8 @@ along with GCC; see the file COPYING3. If not see
#include "rtl-iter.h"
#include "gimple-range.h"
#include "fold-const-call.h"
+#include "tree-ssa-live.h"
+#include "tree-outof-ssa.h"
/* For lang_hooks.types.type_for_mode. */
#include "langhooks.h"
@@ -2964,8 +2966,8 @@ expand_call_mem_ref (tree type, gcall *stmt, int index)
tree tmp = addr;
if (TREE_CODE (tmp) == SSA_NAME)
{
- gimple *def = SSA_NAME_DEF_STMT (tmp);
- if (gimple_assign_single_p (def))
+ gimple *def = get_gimple_for_ssa_name (tmp);
+ if (def && gimple_assign_single_p (def))
tmp = gimple_assign_rhs1 (def);
}
[gcc r14-10160] cfgrtl: Fix MEM_EXPR update in duplicate_insn_chain [PR114924]
https://gcc.gnu.org/g:242fbc0df6c23115c47d256e66fba6a770265c5d commit r14-10160-g242fbc0df6c23115c47d256e66fba6a770265c5d Author: Alex Coplan Date: Fri May 3 09:23:59 2024 +0100 cfgrtl: Fix MEM_EXPR update in duplicate_insn_chain [PR114924] The PR shows that when cfgrtl.cc:duplicate_insn_chain attempts to update the MR_DEPENDENCE_CLIQUE information for a MEM_EXPR we can end up accidentally dropping (e.g.) an ARRAY_REF from the MEM_EXPR and end up replacing it with the underlying MEM_REF. This leads to an inconsistency in the MEM_EXPR information, and could lead to wrong code. While the walk down to the MEM_REF is necessary to update MR_DEPENDENCE_CLIQUE, we should use the outer tree expression for the MEM_EXPR. This patch does that. gcc/ChangeLog: PR rtl-optimization/114924 * cfgrtl.cc (duplicate_insn_chain): When updating MEM_EXPRs, don't strip (e.g.) ARRAY_REFs from the final MEM_EXPR. (cherry picked from commit fe40d525619eee9c2821126390df75068df4773a) Diff: --- gcc/cfgrtl.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/cfgrtl.cc b/gcc/cfgrtl.cc index 304c429c99b..a5dc3512159 100644 --- a/gcc/cfgrtl.cc +++ b/gcc/cfgrtl.cc @@ -4432,12 +4432,13 @@ duplicate_insn_chain (rtx_insn *from, rtx_insn *to, since MEM_EXPR is shared so make a copy and walk to the subtree again. */ tree new_expr = unshare_expr (MEM_EXPR (*iter)); + tree orig_new_expr = new_expr; if (TREE_CODE (new_expr) == WITH_SIZE_EXPR) new_expr = TREE_OPERAND (new_expr, 0); while (handled_component_p (new_expr)) new_expr = TREE_OPERAND (new_expr, 0); MR_DEPENDENCE_CLIQUE (new_expr) = newc; - set_mem_expr (const_cast (*iter), new_expr); + set_mem_expr (const_cast (*iter), orig_new_expr); } } }
[gcc r15-130] Add default bitmap obstack allocation check
https://gcc.gnu.org/g:a2e9032deaf9dbcff329d650f61e36c6a5aa1fc4
commit r15-130-ga2e9032deaf9dbcff329d650f61e36c6a5aa1fc4
Author: Richard Biener
Date: Fri Apr 5 11:02:46 2024 +0200
Add default bitmap obstack allocation check
The following adds a check that the global bitmap obstack is initialized
when allocating a bitmap from it.
* bitmap.cc (bitmap_alloc): When using the global bitmap obstack
assert that is initialized.
Diff:
---
gcc/bitmap.cc | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/gcc/bitmap.cc b/gcc/bitmap.cc
index 459e32c1ad1..0905cde696f 100644
--- a/gcc/bitmap.cc
+++ b/gcc/bitmap.cc
@@ -781,7 +781,10 @@ bitmap_alloc (bitmap_obstack *bit_obstack MEM_STAT_DECL)
bitmap map;
if (!bit_obstack)
-bit_obstack = _default_obstack;
+{
+ gcc_assert (bitmap_default_obstack_depth > 0);
+ bit_obstack = _default_obstack;
+}
map = bit_obstack->heads;
if (map)
bit_obstack->heads = (class bitmap_head *) map->first;
[gcc r15-129] Silence two instances of -Wcalloc-transposed-args
https://gcc.gnu.org/g:c5245c869f0468ddb67c6d996219bd443610673c
commit r15-129-gc5245c869f0468ddb67c6d996219bd443610673c
Author: Peter Damianov
Date: Fri May 3 01:02:35 2024 -0700
Silence two instances of -Wcalloc-transposed-args
libgcc/
* libgcov-util.c (tag_counters): Swap order of arguments to xcalloc.
(topen_to_memory_representation): Likewise.
Signed-off-by: Peter Damianov
Diff:
---
libgcc/libgcov-util.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/libgcc/libgcov-util.c b/libgcc/libgcov-util.c
index ba4b90a480d..f443408c4ab 100644
--- a/libgcc/libgcov-util.c
+++ b/libgcc/libgcov-util.c
@@ -211,8 +211,8 @@ tag_counters (unsigned tag, int length)
gcc_assert (k_ctrs[tag_ix].num == 0);
k_ctrs[tag_ix].num = n_counts;
- k_ctrs[tag_ix].values = values = (gcov_type *) xcalloc (sizeof (gcov_type),
- n_counts);
+ k_ctrs[tag_ix].values = values = (gcov_type *) xcalloc (n_counts,
+ sizeof (gcov_type));
gcc_assert (values);
if (length > 0)
@@ -526,7 +526,7 @@ topn_to_memory_representation (struct gcov_ctr_info *info)
if (n > 0)
{
struct gcov_kvp *tuples
- = (struct gcov_kvp *)xcalloc (sizeof (struct gcov_kvp), n);
+ = (struct gcov_kvp *)xcalloc (n, sizeof (struct gcov_kvp));
for (unsigned i = 0; i < n - 1; i++)
tuples[i].next = [i + 1];
for (unsigned i = 0; i < n; i++)
[gcc r15-128] libstdc++: Update powerpc-linux-gnu baseline_symbols
https://gcc.gnu.org/g:212d93f4b3a2b63817b7b32efa1d910e5720ddc6 commit r15-128-g212d93f4b3a2b63817b7b32efa1d910e5720ddc6 Author: Andreas Schwab Date: Sat Feb 3 14:00:41 2024 +0100 libstdc++: Update powerpc-linux-gnu baseline_symbols * config/abi/post/powerpc-linux-gnu/baseline_symbols.txt: Update. * config/abi/post/powerpc64-linux-gnu/32/baseline_symbols.txt: Update. Diff: --- .../post/powerpc-linux-gnu/baseline_symbols.txt| 98 ++ .../powerpc64-linux-gnu/32/baseline_symbols.txt| 98 ++ 2 files changed, 196 insertions(+) diff --git a/libstdc++-v3/config/abi/post/powerpc-linux-gnu/baseline_symbols.txt b/libstdc++-v3/config/abi/post/powerpc-linux-gnu/baseline_symbols.txt index 0209003243a..c38386543b6 100644 --- a/libstdc++-v3/config/abi/post/powerpc-linux-gnu/baseline_symbols.txt +++ b/libstdc++-v3/config/abi/post/powerpc-linux-gnu/baseline_symbols.txt @@ -497,7 +497,12 @@ FUNC:_ZNKSt11__timepunctIwE7_M_daysEPPKw@@GLIBCXX_3.4 FUNC:_ZNKSt11__timepunctIwE8_M_am_pmEPPKw@@GLIBCXX_3.4 FUNC:_ZNKSt11__timepunctIwE9_M_monthsEPPKw@@GLIBCXX_3.4 FUNC:_ZNKSt11logic_error4whatEv@@GLIBCXX_3.4 +FUNC:_ZNKSt12__basic_fileIcE13native_handleEv@@GLIBCXX_3.4.33 FUNC:_ZNKSt12__basic_fileIcE7is_openEv@@GLIBCXX_3.4 +FUNC:_ZNKSt12__shared_ptrINSt10filesystem28recursive_directory_iterator10_Dir_stackELN9__gnu_cxx12_Lock_policyE2EEcvbEv@@GLIBCXX_3.4.31 +FUNC:_ZNKSt12__shared_ptrINSt10filesystem4_DirELN9__gnu_cxx12_Lock_policyE2EEcvbEv@@GLIBCXX_3.4.31 +FUNC:_ZNKSt12__shared_ptrINSt10filesystem7__cxx1128recursive_directory_iterator10_Dir_stackELN9__gnu_cxx12_Lock_policyE2EEcvbEv@@GLIBCXX_3.4.31 +FUNC:_ZNKSt12__shared_ptrINSt10filesystem7__cxx114_DirELN9__gnu_cxx12_Lock_policyE2EEcvbEv@@GLIBCXX_3.4.31 FUNC:_ZNKSt12bad_weak_ptr4whatEv@@GLIBCXX_3.4.15 FUNC:_ZNKSt12future_error4whatEv@@GLIBCXX_3.4.14 FUNC:_ZNKSt12strstreambuf6pcountEv@@GLIBCXX_3.4 @@ -810,6 +815,13 @@ FUNC:_ZNKSt5ctypeIwE8do_widenEPKcS2_Pw@@GLIBCXX_3.4 FUNC:_ZNKSt5ctypeIwE8do_widenEc@@GLIBCXX_3.4 FUNC:_ZNKSt5ctypeIwE9do_narrowEPKwS2_cPc@@GLIBCXX_3.4 FUNC:_ZNKSt5ctypeIwE9do_narrowEwc@@GLIBCXX_3.4 +FUNC:_ZNKSt6chrono4tzdb11locate_zoneESt17basic_string_viewIcSt11char_traitsIcEE@@GLIBCXX_3.4.31 +FUNC:_ZNKSt6chrono4tzdb12current_zoneEv@@GLIBCXX_3.4.31 +FUNC:_ZNKSt6chrono9time_zone15_M_get_sys_infoENS_10time_pointINS_3_V212system_clockENS_8durationIxSt5ratioILx1ELx1EE@@GLIBCXX_3.4.31 +FUNC:_ZNKSt6chrono9time_zone17_M_get_local_infoENS_10time_pointINS_7local_tENS_8durationIxSt5ratioILx1ELx1EE@@GLIBCXX_3.4.31 +FUNC:_ZNKSt6chrono9tzdb_list14const_iteratordeEv@@GLIBCXX_3.4.31 +FUNC:_ZNKSt6chrono9tzdb_list5beginEv@@GLIBCXX_3.4.31 +FUNC:_ZNKSt6chrono9tzdb_list5frontEv@@GLIBCXX_3.4.31 FUNC:_ZNKSt6locale2id5_M_idEv@@GLIBCXX_3.4 FUNC:_ZNKSt6locale4nameB5cxx11Ev@@GLIBCXX_3.4.21 FUNC:_ZNKSt6locale4nameEv@@GLIBCXX_3.4 @@ -3285,9 +3297,18 @@ FUNC:_ZNSt6__norm15_List_node_base7_M_hookEPS0_@@GLIBCXX_3.4.14 FUNC:_ZNSt6__norm15_List_node_base7reverseEv@@GLIBCXX_3.4.9 FUNC:_ZNSt6__norm15_List_node_base8transferEPS0_S1_@@GLIBCXX_3.4.9 FUNC:_ZNSt6__norm15_List_node_base9_M_unhookEv@@GLIBCXX_3.4.14 +FUNC:_ZNSt6chrono11locate_zoneESt17basic_string_viewIcSt11char_traitsIcEE@@GLIBCXX_3.4.31 +FUNC:_ZNSt6chrono11reload_tzdbEv@@GLIBCXX_3.4.31 +FUNC:_ZNSt6chrono12current_zoneEv@@GLIBCXX_3.4.31 FUNC:_ZNSt6chrono12system_clock3nowEv@@GLIBCXX_3.4.11 +FUNC:_ZNSt6chrono13get_tzdb_listEv@@GLIBCXX_3.4.31 +FUNC:_ZNSt6chrono14remote_versionB5cxx11Ev@@GLIBCXX_3.4.31 FUNC:_ZNSt6chrono3_V212steady_clock3nowEv@@GLIBCXX_3.4.19 FUNC:_ZNSt6chrono3_V212system_clock3nowEv@@GLIBCXX_3.4.19 +FUNC:_ZNSt6chrono8get_tzdbEv@@GLIBCXX_3.4.31 +FUNC:_ZNSt6chrono9tzdb_list11erase_afterENS0_14const_iteratorE@@GLIBCXX_3.4.31 +FUNC:_ZNSt6chrono9tzdb_list14const_iteratorppEi@@GLIBCXX_3.4.31 +FUNC:_ZNSt6chrono9tzdb_list14const_iteratorppEv@@GLIBCXX_3.4.31 FUNC:_ZNSt6gslice8_IndexerC1EjRKSt8valarrayIjES4_@@GLIBCXX_3.4 FUNC:_ZNSt6gslice8_IndexerC2EjRKSt8valarrayIjES4_@@GLIBCXX_3.4 FUNC:_ZNSt6locale11_M_coalesceERKS_S1_i@@GLIBCXX_3.4 @@ -3384,6 +3405,7 @@ FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_disposeEv@@GLIBCX FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_M_replaceEjjPKcj@@GLIBCXX_3.4.21 FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE10_S_compareEjj@@GLIBCXX_3.4.21 FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_M_capacityEj@@GLIBCXX_3.4.21 +FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE11_S_allocateERS3_j@@GLIBCXX_3.4.32 FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderC1EPcOS3_@@GLIBCXX_3.4.23 FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderC1EPcRKS3_@@GLIBCXX_3.4.21 FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE12_Alloc_hiderC2EPcOS3_@@GLIBCXX_3.4.23 @@ -3403,6 +3425,7 @@ FUNC:_ZNSt7__cxx1112basic_stringIcSt11char_traitsIcESaIcEE13_S_copy_charsEPcPKcS
[gcc r15-127] Avoid changing type in the type_hash_canon hash
https://gcc.gnu.org/g:7a212ac678e13e0df5da2d090144b246a1262b64
commit r15-127-g7a212ac678e13e0df5da2d090144b246a1262b64
Author: Richard Biener
Date: Fri May 3 11:48:07 2024 +0200
Avoid changing type in the type_hash_canon hash
When building a type and type_hash_canon returns an existing type
avoid changing it, in particular its TYPE_CANONICAL.
PR middle-end/114931
* tree.cc (build_array_type_1): Return early when type_hash_canon
returned an older existing type.
(build_function_type): Likewise.
(build_method_type_directly): Likewise.
(build_offset_type): Likewise.
Diff:
---
gcc/tree.cc | 12
1 file changed, 12 insertions(+)
diff --git a/gcc/tree.cc b/gcc/tree.cc
index 83f3bf306af..780662549fe 100644
--- a/gcc/tree.cc
+++ b/gcc/tree.cc
@@ -7352,7 +7352,10 @@ build_array_type_1 (tree elt_type, tree index_type, bool
typeless_storage,
if (shared)
{
hashval_t hash = type_hash_canon_hash (t);
+ tree probe_type = t;
t = type_hash_canon (hash, t);
+ if (t != probe_type)
+ return t;
}
if (TYPE_CANONICAL (t) == t && set_canonical)
@@ -7509,7 +7512,10 @@ build_function_type (tree value_type, tree arg_types,
/* If we already have such a type, use the old one. */
hashval_t hash = type_hash_canon_hash (t);
+ tree probe_type = t;
t = type_hash_canon (hash, t);
+ if (t != probe_type)
+return t;
/* Set up the canonical type. */
any_structural_p = TYPE_STRUCTURAL_EQUALITY_P (value_type);
@@ -7663,7 +7669,10 @@ build_method_type_directly (tree basetype,
/* If we already have such a type, use the old one. */
hashval_t hash = type_hash_canon_hash (t);
+ tree probe_type = t;
t = type_hash_canon (hash, t);
+ if (t != probe_type)
+return t;
/* Set up the canonical type. */
any_structural_p
@@ -7720,7 +7729,10 @@ build_offset_type (tree basetype, tree type)
/* If we already have such a type, use the old one. */
hashval_t hash = type_hash_canon_hash (t);
+ tree probe_type = t;
t = type_hash_canon (hash, t);
+ if (t != probe_type)
+return t;
if (!COMPLETE_TYPE_P (t))
layout_type (t);
[gcc r13-8678] ifcvt: Don't lower bitfields with non-constant offsets [PR 111882]
https://gcc.gnu.org/g:4950f6bcd3cce9deb630b76af42cd6d6968ba03f
commit r13-8678-g4950f6bcd3cce9deb630b76af42cd6d6968ba03f
Author: Andre Vieira
Date: Fri Oct 20 17:02:32 2023 +0100
ifcvt: Don't lower bitfields with non-constant offsets [PR 111882]
This patch stops lowering of bitfields by ifcvt when they have non-constant
offsets as we are not likely to be able to do anything useful with those
during
vectorization. That also fixes the issue reported in PR 111882, which was
being caused by an offset with a side-effect being lowered, but constants
have
no side-effects so we will no longer run into that problem.
gcc/ChangeLog:
PR tree-optimization/111882
* tree-if-conv.cc (get_bitfield_rep): Return NULL_TREE for bitfields
with non-constant offsets.
gcc/testsuite/ChangeLog:
* gcc.dg/vect/pr111882.c: New test.
(cherry picked from commit 24cf1f600b8ad34c68a51f48884e72d01f729893)
Diff:
---
gcc/testsuite/gcc.dg/vect/pr111882.c | 15 +++
gcc/tree-if-conv.cc | 12 +++-
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/gcc/testsuite/gcc.dg/vect/pr111882.c
b/gcc/testsuite/gcc.dg/vect/pr111882.c
new file mode 100644
index 000..024ad57b693
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/vect/pr111882.c
@@ -0,0 +1,15 @@
+/* { dg-do compile } */
+/* { dg-additional-options { -fdump-tree-ifcvt-all } } */
+
+static void __attribute__((noipa)) f(int n) {
+ int i, j;
+ struct S { char d[n]; int a; int b : 17; int c : 12; };
+ struct S A[100][];
+ for (i = 0; i < 100; i++) {
+asm volatile("" : : "g"([0][0]) : "memory");
+for (j = 0; j < ; j++) A[i][j].b = 2;
+ }
+}
+void g(void) { f(1); }
+
+/* { dg-final { scan-tree-dump-not "Bitfield OK to lower" "ifcvt" } } */
diff --git a/gcc/tree-if-conv.cc b/gcc/tree-if-conv.cc
index a19450f533d..fddc4a890c6 100644
--- a/gcc/tree-if-conv.cc
+++ b/gcc/tree-if-conv.cc
@@ -3330,6 +3330,7 @@ get_bitfield_rep (gassign *stmt, bool write, tree *bitpos,
: gimple_assign_rhs1 (stmt);
tree field_decl = TREE_OPERAND (comp_ref, 1);
+ tree ref_offset = component_ref_field_offset (comp_ref);
tree rep_decl = DECL_BIT_FIELD_REPRESENTATIVE (field_decl);
/* Bail out if the representative is not a suitable type for a scalar
@@ -3344,6 +3345,15 @@ get_bitfield_rep (gassign *stmt, bool write, tree
*bitpos,
if (compare_tree_int (DECL_SIZE (field_decl), bf_prec) != 0)
return NULL_TREE;
+ if (TREE_CODE (DECL_FIELD_OFFSET (rep_decl)) != INTEGER_CST
+ || TREE_CODE (ref_offset) != INTEGER_CST)
+{
+ if (dump_file && (dump_flags & TDF_DETAILS))
+ fprintf (dump_file, "\t Bitfield NOT OK to lower,"
+ " offset is non-constant.\n");
+ return NULL_TREE;
+}
+
if (struct_expr)
*struct_expr = TREE_OPERAND (comp_ref, 0);
@@ -3364,7 +3374,7 @@ get_bitfield_rep (gassign *stmt, bool write, tree *bitpos,
the structure and the container from the number of bits from the start
of the structure and the actual bitfield member. */
tree bf_pos = fold_build2 (MULT_EXPR, bitsizetype,
-DECL_FIELD_OFFSET (field_decl),
+ref_offset,
build_int_cst (bitsizetype, BITS_PER_UNIT));
bf_pos = fold_build2 (PLUS_EXPR, bitsizetype, bf_pos,
DECL_FIELD_BIT_OFFSET (field_decl));
gcc-wwwdocs branch master updated. d63b0ce2968ddaa335a679ba4595ca582ef76d6d
This is an automated email from the git hooks/post-receive script. It was
generated because a ref change was pushed to the repository containing
the project "gcc-wwwdocs".
The branch, master has been updated
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from d2323d3efa30008ed05519a398eb7fe1e9b446d3 (commit)
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not appeared on any other notification email; so we list those
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- Log -
commit d63b0ce2968ddaa335a679ba4595ca582ef76d6d
Author: Martin Jambor
Date: Fri May 3 11:53:43 2024 +0200
List znver5 in the GCC 14 changes document
diff --git a/htdocs/gcc-14/changes.html b/htdocs/gcc-14/changes.html
index 8dfbf7dc..46a0266d 100644
--- a/htdocs/gcc-14/changes.html
+++ b/htdocs/gcc-14/changes.html
@@ -954,6 +954,12 @@ __asm (".global __flmap_lock" "\n\t"
-fsanitize=hwaddress will enable -mlam=u57
by default.
+ GCC now supports AMD CPUs based on the znver5 core via
+-march=znver5. In addition to the ISA extensions
+enabled on a znver4 core, this switch further enables the
+AVX512VP2INTERSECT, AVXVNNI, MOVDIR64B, MOVDIRI, and PREFETCHI ISA
+extensions.
+
MCore
---
Summary of changes:
htdocs/gcc-14/changes.html | 6 ++
1 file changed, 6 insertions(+)
hooks/post-receive
--
gcc-wwwdocs
[gcc r15-126] cfgrtl: Fix MEM_EXPR update in duplicate_insn_chain [PR114924]
https://gcc.gnu.org/g:fe40d525619eee9c2821126390df75068df4773a commit r15-126-gfe40d525619eee9c2821126390df75068df4773a Author: Alex Coplan Date: Fri May 3 09:23:59 2024 +0100 cfgrtl: Fix MEM_EXPR update in duplicate_insn_chain [PR114924] The PR shows that when cfgrtl.cc:duplicate_insn_chain attempts to update the MR_DEPENDENCE_CLIQUE information for a MEM_EXPR we can end up accidentally dropping (e.g.) an ARRAY_REF from the MEM_EXPR and end up replacing it with the underlying MEM_REF. This leads to an inconsistency in the MEM_EXPR information, and could lead to wrong code. While the walk down to the MEM_REF is necessary to update MR_DEPENDENCE_CLIQUE, we should use the outer tree expression for the MEM_EXPR. This patch does that. gcc/ChangeLog: PR rtl-optimization/114924 * cfgrtl.cc (duplicate_insn_chain): When updating MEM_EXPRs, don't strip (e.g.) ARRAY_REFs from the final MEM_EXPR. Diff: --- gcc/cfgrtl.cc | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/gcc/cfgrtl.cc b/gcc/cfgrtl.cc index 304c429c99b..a5dc3512159 100644 --- a/gcc/cfgrtl.cc +++ b/gcc/cfgrtl.cc @@ -4432,12 +4432,13 @@ duplicate_insn_chain (rtx_insn *from, rtx_insn *to, since MEM_EXPR is shared so make a copy and walk to the subtree again. */ tree new_expr = unshare_expr (MEM_EXPR (*iter)); + tree orig_new_expr = new_expr; if (TREE_CODE (new_expr) == WITH_SIZE_EXPR) new_expr = TREE_OPERAND (new_expr, 0); while (handled_component_p (new_expr)) new_expr = TREE_OPERAND (new_expr, 0); MR_DEPENDENCE_CLIQUE (new_expr) = newc; - set_mem_expr (const_cast (*iter), new_expr); + set_mem_expr (const_cast (*iter), orig_new_expr); } } }
[gcc r15-125] tree-inline: Add __builtin_stack_{save, restore} pair about inline calls with calls to alloca [PR1135
https://gcc.gnu.org/g:7117e1f6bf6de25c1ff26c4d7abcc79b407ca221
commit r15-125-g7117e1f6bf6de25c1ff26c4d7abcc79b407ca221
Author: Jakub Jelinek
Date: Fri May 3 09:44:30 2024 +0200
tree-inline: Add __builtin_stack_{save,restore} pair about inline calls
with calls to alloca [PR113596]
The following patch adds save_NNN = __builtin_stack_save (); ...
__builtin_stack_restore (save_NNN);
pair around inline calls which call alloca (alloca calls because of
VLA vars are ignored in that decision).
The patch doesn't change anything on whether we try to inline such calls or
not, it just fixes the behavior when we inline them despite those checks.
The stack save/restore restores the behavior that alloca acquired regions
are freed at the end of the containing call.
2024-05-03 Jakub Jelinek
PR middle-end/113596
* tree-inline.cc (expand_call_inline): Emit __builtin_stack_save
and __builtin_stack_restore calls around inlined functions which
call alloca.
* gcc.dg/pr113596.c: New test.
* gcc.dg/tree-ssa/pr113596.c: New test.
Diff:
---
gcc/testsuite/gcc.dg/pr113596.c | 24 +
gcc/testsuite/gcc.dg/tree-ssa/pr113596.c | 37
gcc/tree-inline.cc | 34 +
3 files changed, 95 insertions(+)
diff --git a/gcc/testsuite/gcc.dg/pr113596.c b/gcc/testsuite/gcc.dg/pr113596.c
new file mode 100644
index 000..19e0ab6dc46
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/pr113596.c
@@ -0,0 +1,24 @@
+/* PR middle-end/113596 */
+/* { dg-do run } */
+/* { dg-options "-O2" } */
+
+__attribute__((noipa)) void
+bar (char *p, int n)
+{
+ p[0] = 1;
+ p[n - 1] = 2;
+}
+
+static inline __attribute__((always_inline)) void
+foo (int n)
+{
+ char *p = __builtin_alloca (n);
+ bar (p, n);
+}
+
+int
+main ()
+{
+ for (int i = 2; i < 8192; ++i)
+foo (i);
+}
diff --git a/gcc/testsuite/gcc.dg/tree-ssa/pr113596.c
b/gcc/testsuite/gcc.dg/tree-ssa/pr113596.c
new file mode 100644
index 000..37626850628
--- /dev/null
+++ b/gcc/testsuite/gcc.dg/tree-ssa/pr113596.c
@@ -0,0 +1,37 @@
+/* PR middle-end/113596 */
+/* { dg-do compile } */
+/* { dg-options "-O2 -fdump-tree-einline" } */
+/* { dg-final { scan-tree-dump-times "__builtin_stack_save \\\(" 3 "einline" }
} */
+/* { dg-final { scan-tree-dump-times "__builtin_stack_restore \\\(" 3
"einline" } } */
+
+void baz (char *p, int n);
+volatile int v;
+
+static inline __attribute__((always_inline)) void
+foo (int n)
+{
+ ++v;
+ {
+char *p = __builtin_alloca (n);
+baz (p, n);
+ }
+ ++v;
+}
+
+static inline __attribute__((always_inline)) void
+bar (int n)
+{
+ ++v;
+ {
+char p[n];
+baz (p, n);
+ }
+ ++v;
+}
+
+void
+qux (int n)
+{
+ foo (n);
+ bar (n);
+}
diff --git a/gcc/tree-inline.cc b/gcc/tree-inline.cc
index 238afb7de80..b9fe2099d4f 100644
--- a/gcc/tree-inline.cc
+++ b/gcc/tree-inline.cc
@@ -4794,6 +4794,7 @@ expand_call_inline (basic_block bb, gimple *stmt,
copy_body_data *id,
use_operand_p use;
gimple *simtenter_stmt = NULL;
vec *simtvars_save;
+ tree save_stack = NULL_TREE;
/* The gimplifier uses input_location in too many places, such as
internal_get_tmp_var (). */
@@ -5042,6 +5043,28 @@ expand_call_inline (basic_block bb, gimple *stmt,
copy_body_data *id,
GSI_NEW_STMT);
}
+ /* If function to be inlined calls alloca, wrap the inlined function
+ in between save_stack = __builtin_stack_save (); and
+ __builtin_stack_restore (save_stack); calls. */
+ if (id->src_cfun->calls_alloca && !gimple_call_noreturn_p (stmt))
+/* Don't do this for VLA allocations though, just for user alloca
+ calls. */
+for (struct cgraph_edge *e = id->src_node->callees; e; e = e->next_callee)
+ if (gimple_maybe_alloca_call_p (e->call_stmt)
+ && !gimple_call_alloca_for_var_p (e->call_stmt))
+ {
+ tree fn = builtin_decl_implicit (BUILT_IN_STACK_SAVE);
+ gcall *call = gimple_build_call (fn, 0);
+ save_stack = make_ssa_name (ptr_type_node);
+ gimple_call_set_lhs (call, save_stack);
+ gimple_stmt_iterator si = gsi_last_bb (bb);
+ gsi_insert_after (, call, GSI_NEW_STMT);
+ struct cgraph_node *dest = cgraph_node::get_create (fn);
+ id->dst_node->create_edge (dest, call, bb->count)->inline_failed
+ = CIF_BODY_NOT_AVAILABLE;
+ break;
+ }
+
if (DECL_INITIAL (fn))
{
if (gimple_block (stmt))
@@ -5165,6 +5188,17 @@ expand_call_inline (basic_block bb, gimple *stmt,
copy_body_data *id,
}
}
+ if (save_stack)
+{
+ tree fn = builtin_decl_implicit (BUILT_IN_STACK_RESTORE);
+ gcall *call = gimple_build_call (fn, 1, save_stack);
+ gsi_insert_before (_gsi, call, GSI_SAME_STMT);
+ struct cgraph_node *dest = cgraph_node::get_create
[gcc r14-10159] tree-optimization/114921 - _Float16 -> __bf16 isn't noop
https://gcc.gnu.org/g:fa7e05d90bb672b58424ddbe37a05a0fd0949b35 commit r14-10159-gfa7e05d90bb672b58424ddbe37a05a0fd0949b35 Author: Richard Biener Date: Thu May 2 13:55:15 2024 +0200 tree-optimization/114921 - _Float16 -> __bf16 isn't noop The vectorizer handles a _Float16 to __bf16 conversion through vectorizable_assignment, thinking it's a noop. The following fixes this by requiring the same vector component mode when checking for CONVERT_EXPR_CODE_P, being stricter than for VIEW_CONVERT_EXPR. PR tree-optimization/114921 * tree-vect-stmts.cc (vectorizable_assignment): Require same vector component modes for input and output for CONVERT_EXPR_CODE_P. (cherry picked from commit 87e35da16df74cd1c4729a55d94e7bc592487f48) Diff: --- gcc/tree-vect-stmts.cc | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc index f8d8636b139..7e571968a59 100644 --- a/gcc/tree-vect-stmts.cc +++ b/gcc/tree-vect-stmts.cc @@ -5955,14 +5955,17 @@ vectorizable_assignment (vec_info *vinfo, if (!vectype_in) vectype_in = get_vectype_for_scalar_type (vinfo, TREE_TYPE (op), slp_node); - /* We can handle NOP_EXPR conversions that do not change the number - of elements or the vector size. */ - if ((CONVERT_EXPR_CODE_P (code) - || code == VIEW_CONVERT_EXPR) - && (!vectype_in - || maybe_ne (TYPE_VECTOR_SUBPARTS (vectype_in), nunits) - || maybe_ne (GET_MODE_SIZE (TYPE_MODE (vectype)), - GET_MODE_SIZE (TYPE_MODE (vectype_in) + /* We can handle VIEW_CONVERT conversions that do not change the number + of elements or the vector size or other conversions when the component + mode keeps the same. */ + if (!vectype_in + || maybe_ne (TYPE_VECTOR_SUBPARTS (vectype_in), nunits) + || (code == VIEW_CONVERT_EXPR + && maybe_ne (GET_MODE_SIZE (TYPE_MODE (vectype)), + GET_MODE_SIZE (TYPE_MODE (vectype_in + || (CONVERT_EXPR_CODE_P (code) + && (TYPE_MODE (TREE_TYPE (vectype)) + != TYPE_MODE (TREE_TYPE (vectype_in) return false; if (VECTOR_BOOLEAN_TYPE_P (vectype) != VECTOR_BOOLEAN_TYPE_P (vectype_in))
[gcc r15-124] tree-optimization/114921 - _Float16 -> __bf16 isn't noop
https://gcc.gnu.org/g:87e35da16df74cd1c4729a55d94e7bc592487f48 commit r15-124-g87e35da16df74cd1c4729a55d94e7bc592487f48 Author: Richard Biener Date: Thu May 2 13:55:15 2024 +0200 tree-optimization/114921 - _Float16 -> __bf16 isn't noop The vectorizer handles a _Float16 to __bf16 conversion through vectorizable_assignment, thinking it's a noop. The following fixes this by requiring the same vector component mode when checking for CONVERT_EXPR_CODE_P, being stricter than for VIEW_CONVERT_EXPR. PR tree-optimization/114921 * tree-vect-stmts.cc (vectorizable_assignment): Require same vector component modes for input and output for CONVERT_EXPR_CODE_P. Diff: --- gcc/tree-vect-stmts.cc | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/gcc/tree-vect-stmts.cc b/gcc/tree-vect-stmts.cc index f8d8636b139..7e571968a59 100644 --- a/gcc/tree-vect-stmts.cc +++ b/gcc/tree-vect-stmts.cc @@ -5955,14 +5955,17 @@ vectorizable_assignment (vec_info *vinfo, if (!vectype_in) vectype_in = get_vectype_for_scalar_type (vinfo, TREE_TYPE (op), slp_node); - /* We can handle NOP_EXPR conversions that do not change the number - of elements or the vector size. */ - if ((CONVERT_EXPR_CODE_P (code) - || code == VIEW_CONVERT_EXPR) - && (!vectype_in - || maybe_ne (TYPE_VECTOR_SUBPARTS (vectype_in), nunits) - || maybe_ne (GET_MODE_SIZE (TYPE_MODE (vectype)), - GET_MODE_SIZE (TYPE_MODE (vectype_in) + /* We can handle VIEW_CONVERT conversions that do not change the number + of elements or the vector size or other conversions when the component + mode keeps the same. */ + if (!vectype_in + || maybe_ne (TYPE_VECTOR_SUBPARTS (vectype_in), nunits) + || (code == VIEW_CONVERT_EXPR + && maybe_ne (GET_MODE_SIZE (TYPE_MODE (vectype)), + GET_MODE_SIZE (TYPE_MODE (vectype_in + || (CONVERT_EXPR_CODE_P (code) + && (TYPE_MODE (TREE_TYPE (vectype)) + != TYPE_MODE (TREE_TYPE (vectype_in) return false; if (VECTOR_BOOLEAN_TYPE_P (vectype) != VECTOR_BOOLEAN_TYPE_P (vectype_in))
