https://gcc.gnu.org/g:70c202710f25f02a52d560b5fa814f0b42d5ad4c
commit 70c202710f25f02a52d560b5fa814f0b42d5ad4c
Author: Michael Meissner <meiss...@linux.ibm.com>
Date: Fri May 3 22:04:58 2024 -0400
Add support for -mtar
2024-05-03 Michael Meissner <meiss...@linux.ibm.com>
gcc/
* config/rs6000/constraints.md (h constraint): Add tar register to
documentation.
(wt constraint): New constraint.
* config/rs6000/rs6000-cpus.def (ISA_2_7_MASKS_SERVER): Add -mtar.
(POWERPC_MASKS): Likewise.
* config/rs6000/rs6000.cc (rs6000_reg_names): Add new tar register.
(alt_reg_names): Likewise.
(rs6000_debug_reg_global): Likewise.
(rs6000_init_hard_regno_mode_ok): Likewise.
(rs6000_option_override_internal): Likewise.
(rs6000_conditional_register_usage): Likewise.
(print_operand): Likewise.
(rs6000_debugger_regno): Likewise.
(rs6000_opt_masks): Likewise.
* config/rs6000/rs6000.h (FIRST_PSEUDO_REGISTER): Likewise.
(FiXED_REGISTERS): Likewise.
(CALL_REALLY_USED_REGISTERS): Likewise.
(REG_ALLOC_ORDER): Likewise.
(reg_class): Add new TAR_REGS register class.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
(r6000_reg_class_enum): Add RS6000_CONSTRAINT_wt.
(REG_NAMES): Add tar register.
* config/rs6000/rs6000.md (TAR_REGNO): New constant.
(mov<mode>_internal): Add support for tar register.
(movcc_<mode>): Likewise.
(movsf_hardfloat): Likewise.
(movsd_hardfloat): Likewise.
(mov<mode>_softfloat): Likewise.
(mov<mode>_hardfloat64): Likewise.
(mov<mode>_softfloat64): Likewise.
(@tablejump<mode>_insn_normal); Likewise.
(@tablejump<mode>_insn_nospec); Likewise.
* config/rs6000/rs6000.opt (-mtar): New option.
* doc/invoke.texi (RS/6000 options): Document -mtar.
* lra-constraints.md (lra_constraints): Print out insn that we can't
generate reloads for.
Diff:
---
gcc/config/rs6000/constraints.md | 5 ++++-
gcc/config/rs6000/rs6000-cpus.def | 4 +++-
gcc/config/rs6000/rs6000.cc | 41 +++++++++++++++++++++++++++++++++------
gcc/config/rs6000/rs6000.h | 31 +++++++++++++++++------------
gcc/config/rs6000/rs6000.md | 23 +++++++++++-----------
gcc/config/rs6000/rs6000.opt | 4 ++++
gcc/doc/invoke.texi | 12 ++++++++++--
gcc/lra-constraints.cc | 9 ++++++---
8 files changed, 93 insertions(+), 36 deletions(-)
diff --git a/gcc/config/rs6000/constraints.md b/gcc/config/rs6000/constraints.md
index 369a7b75042..14f0465d7ae 100644
--- a/gcc/config/rs6000/constraints.md
+++ b/gcc/config/rs6000/constraints.md
@@ -57,7 +57,7 @@
"@internal A compatibility alias for @code{wa}.")
(define_register_constraint "h" "SPECIAL_REGS"
- "@internal A special register (@code{vrsave}, @code{ctr}, or @code{lr}).")
+ "@internal A special register (@code{vrsave}, @code{ctr}, @code{lr} or
@code{tar}).")
(define_register_constraint "c" "CTR_REGS"
"The count register, @code{ctr}.")
@@ -91,6 +91,9 @@
"@internal Like @code{r}, if @option{-mpowerpc64} is used; otherwise,
@code{NO_REGS}.")
+(define_register_constraint "wt" "rs6000_constraints[RS6000_CONSTRAINT_wt]"
+ "The tar register, @code{tar}.")
+
(define_register_constraint "wx" "rs6000_constraints[RS6000_CONSTRAINT_wx]"
"@internal Like @code{d}, if @option{-mpowerpc-gfxopt} is used; otherwise,
@code{NO_REGS}.")
diff --git a/gcc/config/rs6000/rs6000-cpus.def
b/gcc/config/rs6000/rs6000-cpus.def
index d625dbeb91f..29a5398b16d 100644
--- a/gcc/config/rs6000/rs6000-cpus.def
+++ b/gcc/config/rs6000/rs6000-cpus.def
@@ -52,7 +52,8 @@
| OPTION_MASK_CRYPTO \
| OPTION_MASK_EFFICIENT_UNALIGNED_VSX \
| OPTION_MASK_QUAD_MEMORY \
- | OPTION_MASK_QUAD_MEMORY_ATOMIC)
+ | OPTION_MASK_QUAD_MEMORY_ATOMIC \
+ | OPTION_MASK_TAR)
/* ISA masks setting fusion options. */
#define OTHER_FUSION_MASKS (OPTION_MASK_P8_FUSION \
@@ -158,6 +159,7 @@
| OPTION_MASK_RECIP_PRECISION \
| OPTION_MASK_SOFT_FLOAT \
| OPTION_MASK_STRICT_ALIGN_OPTIONAL \
+ | OPTION_MASK_TAR \
| OPTION_MASK_VSX)
#endif
diff --git a/gcc/config/rs6000/rs6000.cc b/gcc/config/rs6000/rs6000.cc
index 5bb66dca81d..463d27fa61b 100644
--- a/gcc/config/rs6000/rs6000.cc
+++ b/gcc/config/rs6000/rs6000.cc
@@ -1224,8 +1224,8 @@ char rs6000_reg_names[][8] =
"lr", "ctr", "ca", "ap",
/* cr0..cr7 */
"0", "1", "2", "3", "4", "5", "6", "7",
- /* vrsave vscr sfp */
- "vrsave", "vscr", "sfp",
+ /* vrsave vscr sfp, tar */
+ "vrsave", "vscr", "sfp", "tar",
};
#ifdef TARGET_REGNAMES
@@ -1250,8 +1250,8 @@ static const char alt_reg_names[][8] =
"lr", "ctr", "ca", "ap",
/* cr0..cr7 */
"%cr0", "%cr1", "%cr2", "%cr3", "%cr4", "%cr5", "%cr6", "%cr7",
- /* vrsave vscr sfp */
- "vrsave", "vscr", "sfp",
+ /* vrsave vscr sfp, tar */
+ "vrsave", "vscr", "sfp", "tar"
};
#endif
@@ -2304,6 +2304,7 @@ rs6000_debug_reg_global (void)
"vs");
rs6000_debug_reg_print (LR_REGNO, LR_REGNO, "lr");
rs6000_debug_reg_print (CTR_REGNO, CTR_REGNO, "ctr");
+ rs6000_debug_reg_print (TAR_REGNO, TAR_REGNO, "tar");
rs6000_debug_reg_print (CR0_REGNO, CR7_REGNO, "cr");
rs6000_debug_reg_print (CA_REGNO, CA_REGNO, "ca");
rs6000_debug_reg_print (VRSAVE_REGNO, VRSAVE_REGNO, "vrsave");
@@ -2320,6 +2321,7 @@ rs6000_debug_reg_global (void)
"wa reg_class = %s\n"
"we reg_class = %s\n"
"wr reg_class = %s\n"
+ "wt reg_class = %s\n"
"wx reg_class = %s\n"
"wA reg_class = %s\n"
"\n",
@@ -2328,6 +2330,7 @@ rs6000_debug_reg_global (void)
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wa]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_we]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wr]],
+ reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wt]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wx]],
reg_class_names[rs6000_constraints[RS6000_CONSTRAINT_wA]]);
@@ -2778,6 +2781,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
rs6000_regno_regclass[LR_REGNO] = LINK_REGS;
rs6000_regno_regclass[CTR_REGNO] = CTR_REGS;
+ rs6000_regno_regclass[TAR_REGNO] = TAR_REGS;
rs6000_regno_regclass[CA_REGNO] = NO_REGS;
rs6000_regno_regclass[VRSAVE_REGNO] = VRSAVE_REGS;
rs6000_regno_regclass[VSCR_REGNO] = VRSAVE_REGS;
@@ -2797,6 +2801,7 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
reg_class_to_reg_type[(int)VSCR_REGS] = SPR_REG_TYPE;
reg_class_to_reg_type[(int)LINK_REGS] = SPR_REG_TYPE;
reg_class_to_reg_type[(int)CTR_REGS] = SPR_REG_TYPE;
+ reg_class_to_reg_type[(int)TAR_REGS] = SPR_REG_TYPE;
reg_class_to_reg_type[(int)LINK_OR_CTR_REGS] = SPR_REG_TYPE;
reg_class_to_reg_type[(int)CR_REGS] = CR_REG_TYPE;
reg_class_to_reg_type[(int)CR0_REGS] = CR_REG_TYPE;
@@ -2986,6 +2991,10 @@ rs6000_init_hard_regno_mode_ok (bool global_init_p)
if (TARGET_DIRECT_MOVE_128)
rs6000_constraints[RS6000_CONSTRAINT_we] = VSX_REGS;
+ /* Power9 adds a TAR register that can hold the target of a jump. */
+ if (TARGET_TAR)
+ rs6000_constraints[RS6000_CONSTRAINT_wt] = TAR_REGS;
+
/* Set up the reload helper and direct move functions. */
if (TARGET_VSX || TARGET_ALTIVEC)
{
@@ -4336,6 +4345,15 @@ rs6000_option_override_internal (bool global_init_p)
SUB3TARGET_OVERRIDE_OPTIONS;
#endif
+ /* TAR register was introduced in power9. */
+ if (TARGET_TAR && !TARGET_P9_MISC)
+ {
+ if ((rs6000_isa_flags_explicit & OPTION_MASK_TAR) != 0)
+ error ("%qs requires at least %qs", "-mtar", "-mcpu=power9");
+
+ rs6000_isa_flags &= ~OPTION_MASK_TAR;
+ }
+
/* If the ABI has support for PC-relative relocations, enable it by default.
This test depends on the sub-target tests above setting the code model to
medium for ELF v2 systems. */
@@ -10207,6 +10225,9 @@ rs6000_conditional_register_usage (void)
for (i = FIRST_ALTIVEC_REGNO + 20; i < FIRST_ALTIVEC_REGNO + 32; ++i)
fixed_regs[i] = call_used_regs[i] = 1;
}
+
+ if (TARGET_TAR)
+ fixed_regs[TAR_REGNO] = 0;
}
@@ -14355,10 +14376,13 @@ print_operand (FILE *file, rtx x, int code)
if (GET_CODE (x) == UNSPEC && XINT (x, 1) == UNSPEC_PLTSEQ)
x = XVECEXP (x, 0, 0);
if (!REG_P (x) || (REGNO (x) != LR_REGNO
- && REGNO (x) != CTR_REGNO))
+ && REGNO (x) != CTR_REGNO
+ && REGNO (x) != TAR_REGNO))
output_operand_lossage ("invalid %%T value");
else if (REGNO (x) == LR_REGNO)
fputs ("lr", file);
+ else if (REGNO (x) == TAR_REGNO)
+ fputs ("tar", file);
else
fputs ("ctr", file);
return;
@@ -24184,6 +24208,8 @@ rs6000_debugger_regno (unsigned int regno, unsigned int
format)
return 108;
if (regno == CTR_REGNO)
return 109;
+ if (regno == TAR_REGNO)
+ return 111;
if (regno == CA_REGNO)
return 101; /* XER */
/* Special handling for CR for .debug_frame: rs6000_emit_prologue has
@@ -24201,7 +24227,7 @@ rs6000_debugger_regno (unsigned int regno, unsigned int
format)
/* These do not make much sense. */
if (regno == FRAME_POINTER_REGNUM)
- return 111;
+ return FIRST_PSEUDO_REGISTER;
if (regno == ARG_POINTER_REGNUM)
return 67;
if (regno == 64)
@@ -24224,6 +24250,8 @@ rs6000_debugger_regno (unsigned int regno, unsigned int
format)
return 65;
if (regno == CTR_REGNO)
return 66;
+ if (regno == TAR_REGNO)
+ return 111;
if (regno == CA_REGNO)
return 76; /* XER */
if (CR_REGNO_P (regno))
@@ -24486,6 +24514,7 @@ static struct rs6000_opt_mask const rs6000_opt_masks[] =
{ "recip-precision", OPTION_MASK_RECIP_PRECISION, false, true },
{ "save-toc-indirect", OPTION_MASK_SAVE_TOC_INDIRECT, false, true },
{ "string", 0, false, true },
+ { "tar", OPTION_MASK_TAR, false, true },
{ "update", OPTION_MASK_NO_UPDATE, true , true },
{ "vsx", OPTION_MASK_VSX, false, true },
#ifdef OPTION_MASK_64BIT
diff --git a/gcc/config/rs6000/rs6000.h b/gcc/config/rs6000/rs6000.h
index 2e60a0395ad..ae9aff95195 100644
--- a/gcc/config/rs6000/rs6000.h
+++ b/gcc/config/rs6000/rs6000.h
@@ -788,7 +788,7 @@ enum data_align { align_abi, align_opt, align_both };
Another pseudo (not included in DWARF_FRAME_REGISTERS) is soft frame
pointer, which is eventually eliminated in favor of SP or FP. */
-#define FIRST_PSEUDO_REGISTER 111
+#define FIRST_PSEUDO_REGISTER 112
/* Use standard DWARF numbering for DWARF debugging information. */
#define DEBUGGER_REGNO(REGNO) rs6000_debugger_regno ((REGNO), 0)
@@ -824,8 +824,8 @@ enum data_align { align_abi, align_opt, align_both };
0, 0, 1, 1, \
/* cr0..cr7 */ \
0, 0, 0, 0, 0, 0, 0, 0, \
- /* vrsave vscr sfp */ \
- 1, 1, 1 \
+ /* vrsave vscr sfp, tar */ \
+ 1, 1, 1, 1 \
}
/* Like `CALL_USED_REGISTERS' except this macro doesn't require that
@@ -848,8 +848,8 @@ enum data_align { align_abi, align_opt, align_both };
1, 1, 1, 1, \
/* cr0..cr7 */ \
1, 1, 0, 0, 0, 1, 1, 1, \
- /* vrsave vscr sfp */ \
- 0, 0, 0 \
+ /* vrsave vscr sfp, tar */ \
+ 0, 0, 0, 1 \
}
#define TOTAL_ALTIVEC_REGS (LAST_ALTIVEC_REGNO - FIRST_ALTIVEC_REGNO + 1)
@@ -878,6 +878,7 @@ enum data_align { align_abi, align_opt, align_both };
r0 (not saved; cannot be base reg)
r31 - r13 (saved; order given to save least number)
r12 (not saved; if used for DImode or DFmode would use r13)
+ tar (not saved; tar is preferred over ctr or lr)
ctr (not saved; when we have the choice ctr is better)
lr (saved)
r1, r2, ap, ca (fixed)
@@ -920,7 +921,7 @@ enum data_align { align_abi, align_opt, align_both };
3, EARLY_R12 11, 0, \
31, 30, 29, 28, 27, 26, 25, 24, 23, 22, 21, 20, 19, \
18, 17, 16, 15, 14, 13, LATE_R12 \
- 97, 96, \
+ 111, 97, 96, \
1, MAYBE_R2_FIXED 99, 98, \
/* AltiVec registers. */ \
64, 65, \
@@ -1095,6 +1096,7 @@ enum reg_class
GEN_OR_VSX_REGS,
LINK_REGS,
CTR_REGS,
+ TAR_REGS,
LINK_OR_CTR_REGS,
SPECIAL_REGS,
SPEC_OR_GEN_REGS,
@@ -1124,6 +1126,7 @@ enum reg_class
"GEN_OR_VSX_REGS", \
"LINK_REGS", \
"CTR_REGS", \
+ "TAR_REGS", \
"LINK_OR_CTR_REGS", \
"SPECIAL_REGS", \
"SPEC_OR_GEN_REGS", \
@@ -1164,22 +1167,24 @@ enum reg_class
{ 0x00000000, 0x00000000, 0x00000000, 0x00000001 }, \
/* CTR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000002 }, \
+ /* TAR_REGS. */ \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00008000 }, \
/* LINK_OR_CTR_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00000003 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00008003 }, \
/* SPECIAL_REGS. */ \
- { 0x00000000, 0x00000000, 0x00000000, 0x00001003 }, \
+ { 0x00000000, 0x00000000, 0x00000000, 0x00009003 }, \
/* SPEC_OR_GEN_REGS. */ \
- { 0xffffffff, 0x00000000, 0x00000000, 0x0000500b }, \
+ { 0xffffffff, 0x00000000, 0x00000000, 0x0000d00b }, \
/* CR0_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000010 }, \
/* CR_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000ff0 }, \
/* NON_FLOAT_REGS. */ \
- { 0xffffffff, 0x00000000, 0x00000000, 0x00004ffb }, \
+ { 0xffffffff, 0x00000000, 0x00000000, 0x0000cffb }, \
/* CA_REGS. */ \
{ 0x00000000, 0x00000000, 0x00000000, 0x00000004 }, \
/* ALL_REGS. */ \
- { 0xffffffff, 0xffffffff, 0xffffffff, 0x00007fff } \
+ { 0xffffffff, 0xffffffff, 0xffffffff, 0x0000ffff } \
}
/* The same information, inverted:
@@ -1201,6 +1206,7 @@ enum r6000_reg_class_enum {
RS6000_CONSTRAINT_wa, /* Any VSX register */
RS6000_CONSTRAINT_we, /* VSX register if ISA 3.0 vector. */
RS6000_CONSTRAINT_wr, /* GPR register if 64-bit */
+ RS6000_CONSTRAINT_wt, /* TAR register. */
RS6000_CONSTRAINT_wx, /* FPR register for STFIWX */
RS6000_CONSTRAINT_wA, /* BASE_REGS if 64-bit. */
RS6000_CONSTRAINT_MAX
@@ -2079,7 +2085,8 @@ extern char rs6000_reg_names[][8]; /* register
names (0 vs. %r0). */
&rs6000_reg_names[108][0], /* vrsave */ \
&rs6000_reg_names[109][0], /* vscr */ \
\
- &rs6000_reg_names[110][0] /* sfp */ \
+ &rs6000_reg_names[110][0], /* sfp */ \
+ &rs6000_reg_names[111][0] /* tar */ \
}
/* Table of additional register names to use in user input. */
diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index 41a5b86d3c6..5897da7d38d 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -51,6 +51,7 @@
(VRSAVE_REGNO 108)
(VSCR_REGNO 109)
(FRAME_POINTER_REGNUM 110)
+ (TAR_REGNO 111)
])
;;
@@ -8072,7 +8073,7 @@
[(set (match_operand:QHI 0 "nonimmediate_operand"
"=r, r, wa, m, ?Z, r,
wa, wa, wa, v, ?v, r,
- wa, r, *c*l, *h")
+ wa, r, *wt*c*l, *h")
(match_operand:QHI 1 "input_operand"
"r, m, ?Z, r, wa, i,
wa, O, wM, wB, wS, wa,
@@ -8123,9 +8124,9 @@
(define_insn "*movcc_<mode>"
[(set (match_operand:CC_any 0 "nonimmediate_operand"
- "=y,x,?y,y,r,r,r,r, r,*c*l,r,m")
+ "=y,x,?y,y,r,r,r,r, r,*wt*c*l,r,m")
(match_operand:CC_any 1 "general_operand"
- " y,r, r,O,x,y,r,I,*h, r,m,r"))]
+ " y,r, r,O,x,y,r,I,*h, r,m,r"))]
"register_operand (operands[0], <MODE>mode)
|| register_operand (operands[1], <MODE>mode)"
"@
@@ -8213,7 +8214,7 @@
[(set (match_operand:SF 0 "nonimmediate_operand"
"=!r, f, v, wa, m, wY,
Z, m, wa, !r, f, wa,
- !r, *c*l, !r, *h, wa")
+ !r, *wt*c*l, !r, *h, wa")
(match_operand:SF 1 "input_operand"
"m, m, wY, Z, f, v,
wa, r, j, j, f, wa,
@@ -8259,7 +8260,7 @@
(define_insn "movsd_hardfloat"
[(set (match_operand:SD 0 "nonimmediate_operand"
"=!r, d, m, ?Z, ?d, ?r,
- f, !r, *c*l, !r, *h")
+ f, !r, *wt*c*l, !r, *h")
(match_operand:SD 1 "input_operand"
"m, ?Z, r, wx, r, d,
f, r, r, *h, 0"))]
@@ -8289,7 +8290,7 @@
;; LIS G-const. F/n-const NOP
(define_insn "*mov<mode>_softfloat"
[(set (match_operand:FMOVE32 0 "nonimmediate_operand"
- "=r, *c*l, r, r, m, r,
+ "=r, *wt*c*l, r, r, m, r,
r, r, r, *h")
(match_operand:FMOVE32 1 "input_operand"
@@ -8603,7 +8604,7 @@
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
"=m, d, d, <f64_p9>, wY,
<f64_av>, Z, <f64_vsx>, <f64_vsx>, !r,
- YZ, r, !r, *c*l, !r,
+ YZ, r, !r, *wt*c*l, !r,
*h, r, <f64_dm>, wa")
(match_operand:FMOVE64 1 "input_operand"
"d, m, d, wY, <f64_p9>,
@@ -8655,7 +8656,7 @@
(define_insn "*mov<mode>_softfloat64"
[(set (match_operand:FMOVE64 0 "nonimmediate_operand"
- "=Y, r, r, *c*l, r, r,
+ "=Y, r, r, *wt*c*l,r, r,
r, r, *h")
(match_operand:FMOVE64 1 "input_operand"
@@ -13617,7 +13618,7 @@
(define_insn "@tablejump<mode>_insn_normal"
[(set (pc)
- (match_operand:P 0 "register_operand" "c,*l"))
+ (match_operand:P 0 "register_operand" "wt,c,*l"))
(use (label_ref (match_operand 1)))]
"rs6000_speculate_indirect_jumps"
"b%T0"
@@ -13625,9 +13626,9 @@
(define_insn "@tablejump<mode>_insn_nospec"
[(set (pc)
- (match_operand:P 0 "register_operand" "c,*l"))
+ (match_operand:P 0 "register_operand" "wt,c,*l"))
(use (label_ref (match_operand 1)))
- (clobber (match_operand:CC 2 "cc_reg_operand" "=y,y"))]
+ (clobber (match_operand:CC 2 "cc_reg_operand" "=y,y,y"))]
"!rs6000_speculate_indirect_jumps"
"crset %E2\;beq%T0- %2\;b $"
[(set_attr "type" "jmpreg")
diff --git a/gcc/config/rs6000/rs6000.opt b/gcc/config/rs6000/rs6000.opt
index 70fd7080bc5..6e3fd1d0767 100644
--- a/gcc/config/rs6000/rs6000.opt
+++ b/gcc/config/rs6000/rs6000.opt
@@ -607,6 +607,10 @@ mmma
Target Mask(MMA) Var(rs6000_isa_flags)
Generate (do not generate) MMA instructions.
+mtar
+Target Mask(TAR) Var(rs6000_isa_flags)
+Generate (do not generate) code using the TAR register.
+
mrelative-jumptables
Target Undocumented Var(rs6000_relative_jumptables) Init(1) Save
diff --git a/gcc/doc/invoke.texi b/gcc/doc/invoke.texi
index 64e47803d2f..c0903d67615 100644
--- a/gcc/doc/invoke.texi
+++ b/gcc/doc/invoke.texi
@@ -1332,7 +1332,7 @@ See RS/6000 and PowerPC Options.
-mstack-protector-guard=@var{guard} -mstack-protector-guard-reg=@var{reg}
-mstack-protector-guard-offset=@var{offset} -mprefixed -mno-prefixed
-mpcrel -mno-pcrel -mmma -mno-mmma -mrop-protect -mno-rop-protect
--mprivileged -mno-privileged}
+-mprivileged -mno-privileged -mtar -mno-tar}
@emph{RX Options}
@gccoptlist{-m64bit-doubles -m32bit-doubles -fpu -nofpu
@@ -31351,7 +31351,7 @@ following options:
-mcrypto -mhtm -mpower8-fusion
-mquad-memory -mquad-memory-atomic -mfloat128
-mfloat128-hardware -mprefixed -mpcrel -mmma
--mrop-protect}
+-mrop-protect -mtar}
The particular options set for any particular CPU varies between
compiler versions, depending on what setting seems to produce optimal
@@ -32354,6 +32354,14 @@ Generate (do not generate) ROP protection instructions
when the target
processor supports them. Currently this option disables the shrink-wrap
optimization (@option{-fshrink-wrap}).
+@opindex mtar
+@opindex mno-tar
+@item -mtar
+@itemx -mno-tar
+Generate (do not generate) code that uses the @code{TAR} register.
+The @option{-mtar} option requires that the option
+@option{-mcpu=power9} (or later) is enabled.
+
@opindex mprivileged
@opindex mno-privileged
@item -mprivileged
diff --git a/gcc/lra-constraints.cc b/gcc/lra-constraints.cc
index 10e3d4e4097..4e72aa2d078 100644
--- a/gcc/lra-constraints.cc
+++ b/gcc/lra-constraints.cc
@@ -5346,9 +5346,12 @@ lra_constraints (bool first_p)
continue;
}
if (new_insns_num > MAX_RELOAD_INSNS_NUMBER)
- internal_error
- ("maximum number of generated reload insns per insn achieved (%d)",
- MAX_RELOAD_INSNS_NUMBER);
+ {
+ debug_rtx (curr_insn);
+ internal_error
+ ("maximum number of generated reload insns per insn achieved (%d)",
+ MAX_RELOAD_INSNS_NUMBER);
+ }
new_insns_num++;
if (DEBUG_INSN_P (curr_insn))
{
