[PATCH v2 1/3] drm/xe/display: Preparations for preallocating dpt bo
The DPT bo should not be allocated when pinning, but in advance when
creating the framebuffer. Split allocation from bo pinning and GGTT
insertion.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 159 +++--
1 file changed, 123 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c
b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 3e1ae37c4c8b..5a8d6857fb89 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -77,47 +77,130 @@ write_dpt_remapped(struct xe_bo *bo, struct iosys_map
*map, u32 *dpt_ofs,
*dpt_ofs = ALIGN(*dpt_ofs, 4096);
}
-static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
- const struct i915_gtt_view *view,
- struct i915_vma *vma)
+static struct xe_bo *xe_fb_dpt_alloc(struct intel_framebuffer *fb)
{
struct xe_device *xe = to_xe_device(fb->base.dev);
struct xe_tile *tile0 = xe_device_get_root_tile(xe);
- struct xe_ggtt *ggtt = tile0->mem.ggtt;
struct xe_bo *bo = intel_fb_obj(>base), *dpt;
u32 dpt_size, size = bo->ttm.base.size;
- if (view->type == I915_GTT_VIEW_NORMAL)
+ if (!intel_fb_needs_pot_stride_remap(fb))
dpt_size = ALIGN(size / XE_PAGE_SIZE * 8, XE_PAGE_SIZE);
- else if (view->type == I915_GTT_VIEW_REMAPPED)
- dpt_size =
ALIGN(intel_remapped_info_size(>remapped_view.gtt.remapped) * 8,
-XE_PAGE_SIZE);
else
- /* display uses 4K tiles instead of bytes here, convert to
entries.. */
- dpt_size = ALIGN(intel_rotation_info_size(>rotated) * 8,
+ dpt_size =
ALIGN(intel_remapped_info_size(>remapped_view.gtt.remapped) * 8,
XE_PAGE_SIZE);
if (IS_DGFX(xe))
- dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
- ttm_bo_type_kernel,
- XE_BO_FLAG_VRAM0 |
- XE_BO_FLAG_GGTT |
- XE_BO_FLAG_PAGETABLE);
- else
- dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
- ttm_bo_type_kernel,
- XE_BO_FLAG_STOLEN |
- XE_BO_FLAG_GGTT |
- XE_BO_FLAG_PAGETABLE);
+ return xe_bo_create(xe, tile0, NULL, dpt_size,
+ ttm_bo_type_kernel,
+ XE_BO_FLAG_NEEDS_CPU_ACCESS |
+ XE_BO_FLAG_VRAM0 |
+ XE_BO_FLAG_PAGETABLE);
+
+ dpt = xe_bo_create(xe, tile0, NULL, dpt_size,
+ ttm_bo_type_kernel,
+ XE_BO_FLAG_NEEDS_CPU_ACCESS |
+ XE_BO_FLAG_STOLEN |
+ XE_BO_FLAG_PAGETABLE);
if (IS_ERR(dpt))
- dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
- ttm_bo_type_kernel,
- XE_BO_FLAG_SYSTEM |
- XE_BO_FLAG_GGTT |
- XE_BO_FLAG_PAGETABLE);
+ dpt = xe_bo_create(xe, tile0, NULL, dpt_size,
+ ttm_bo_type_kernel,
+ XE_BO_FLAG_NEEDS_CPU_ACCESS |
+ XE_BO_FLAG_SYSTEM |
+ XE_BO_FLAG_PAGETABLE);
+
+ return dpt;
+}
+
+static void xe_fb_dpt_free(struct i915_vma *vma)
+{
+ xe_bo_put(vma->dpt);
+ vma->dpt = NULL;
+}
+
+static int xe_fb_dpt_map_ggtt(struct xe_bo *dpt)
+{
+ struct xe_device *xe = xe_bo_device(dpt);
+ struct xe_tile *tile0 = xe_device_get_root_tile(xe);
+ struct xe_ggtt *ggtt = tile0->mem.ggtt;
+ u64 start = 0, end = U64_MAX;
+ u64 alignment = XE_PAGE_SIZE;
+ int err;
+
+ if (dpt->flags & XE_BO_FLAG_INTERNAL_64K)
+ alignment = SZ_64K;
+
+ if (XE_WARN_ON(dpt->ggtt_node.size))
+ return -EINVAL;
+
+ xe_pm_runtime_get_noresume(xe);
+ err = mutex_lock_interruptible(>lock);
+ if (err)
+ goto out_put;
+
+ err = drm_mm_insert_node_in_range(>mm, >ggtt_node, dpt->size,
+ alignment, 0, start, end, 0);
+ if (!err)
+ xe_ggtt_map_bo(ggtt, dpt);
+ mutex_unlock(>lock);
+
+out_put:
+ xe_pm_runtime_put(xe);
+ return err;
+}
+
+static int
+xe_fb_dpt_alloc_pinned(struct i915_vma *vma, struct intel_framebuffer *fb)
+{
+ struct xe_bo *dpt;
+ int err;
+
+ dpt = xe_fb_dpt_alloc(fb);
[PATCH v2 1/3] drm/xe/display: Preparations for preallocating dpt bo
The DPT bo should not be allocated when pinning, but in advance when
creating the framebuffer. Split allocation from bo pinning and GGTT
insertion.
Signed-off-by: Maarten Lankhorst
---
drivers/gpu/drm/xe/display/xe_fb_pin.c | 159 +++--
1 file changed, 123 insertions(+), 36 deletions(-)
diff --git a/drivers/gpu/drm/xe/display/xe_fb_pin.c
b/drivers/gpu/drm/xe/display/xe_fb_pin.c
index 3e1ae37c4c8b..5a8d6857fb89 100644
--- a/drivers/gpu/drm/xe/display/xe_fb_pin.c
+++ b/drivers/gpu/drm/xe/display/xe_fb_pin.c
@@ -77,47 +77,130 @@ write_dpt_remapped(struct xe_bo *bo, struct iosys_map
*map, u32 *dpt_ofs,
*dpt_ofs = ALIGN(*dpt_ofs, 4096);
}
-static int __xe_pin_fb_vma_dpt(struct intel_framebuffer *fb,
- const struct i915_gtt_view *view,
- struct i915_vma *vma)
+static struct xe_bo *xe_fb_dpt_alloc(struct intel_framebuffer *fb)
{
struct xe_device *xe = to_xe_device(fb->base.dev);
struct xe_tile *tile0 = xe_device_get_root_tile(xe);
- struct xe_ggtt *ggtt = tile0->mem.ggtt;
struct xe_bo *bo = intel_fb_obj(>base), *dpt;
u32 dpt_size, size = bo->ttm.base.size;
- if (view->type == I915_GTT_VIEW_NORMAL)
+ if (!intel_fb_needs_pot_stride_remap(fb))
dpt_size = ALIGN(size / XE_PAGE_SIZE * 8, XE_PAGE_SIZE);
- else if (view->type == I915_GTT_VIEW_REMAPPED)
- dpt_size =
ALIGN(intel_remapped_info_size(>remapped_view.gtt.remapped) * 8,
-XE_PAGE_SIZE);
else
- /* display uses 4K tiles instead of bytes here, convert to
entries.. */
- dpt_size = ALIGN(intel_rotation_info_size(>rotated) * 8,
+ dpt_size =
ALIGN(intel_remapped_info_size(>remapped_view.gtt.remapped) * 8,
XE_PAGE_SIZE);
if (IS_DGFX(xe))
- dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
- ttm_bo_type_kernel,
- XE_BO_FLAG_VRAM0 |
- XE_BO_FLAG_GGTT |
- XE_BO_FLAG_PAGETABLE);
- else
- dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
- ttm_bo_type_kernel,
- XE_BO_FLAG_STOLEN |
- XE_BO_FLAG_GGTT |
- XE_BO_FLAG_PAGETABLE);
+ return xe_bo_create(xe, tile0, NULL, dpt_size,
+ ttm_bo_type_kernel,
+ XE_BO_FLAG_NEEDS_CPU_ACCESS |
+ XE_BO_FLAG_VRAM0 |
+ XE_BO_FLAG_PAGETABLE);
+
+ dpt = xe_bo_create(xe, tile0, NULL, dpt_size,
+ ttm_bo_type_kernel,
+ XE_BO_FLAG_NEEDS_CPU_ACCESS |
+ XE_BO_FLAG_STOLEN |
+ XE_BO_FLAG_PAGETABLE);
if (IS_ERR(dpt))
- dpt = xe_bo_create_pin_map(xe, tile0, NULL, dpt_size,
- ttm_bo_type_kernel,
- XE_BO_FLAG_SYSTEM |
- XE_BO_FLAG_GGTT |
- XE_BO_FLAG_PAGETABLE);
+ dpt = xe_bo_create(xe, tile0, NULL, dpt_size,
+ ttm_bo_type_kernel,
+ XE_BO_FLAG_NEEDS_CPU_ACCESS |
+ XE_BO_FLAG_SYSTEM |
+ XE_BO_FLAG_PAGETABLE);
+
+ return dpt;
+}
+
+static void xe_fb_dpt_free(struct i915_vma *vma)
+{
+ xe_bo_put(vma->dpt);
+ vma->dpt = NULL;
+}
+
+static int xe_fb_dpt_map_ggtt(struct xe_bo *dpt)
+{
+ struct xe_device *xe = xe_bo_device(dpt);
+ struct xe_tile *tile0 = xe_device_get_root_tile(xe);
+ struct xe_ggtt *ggtt = tile0->mem.ggtt;
+ u64 start = 0, end = U64_MAX;
+ u64 alignment = XE_PAGE_SIZE;
+ int err;
+
+ if (dpt->flags & XE_BO_FLAG_INTERNAL_64K)
+ alignment = SZ_64K;
+
+ if (XE_WARN_ON(dpt->ggtt_node.size))
+ return -EINVAL;
+
+ xe_pm_runtime_get_noresume(xe);
+ err = mutex_lock_interruptible(>lock);
+ if (err)
+ goto out_put;
+
+ err = drm_mm_insert_node_in_range(>mm, >ggtt_node, dpt->size,
+ alignment, 0, start, end, 0);
+ if (!err)
+ xe_ggtt_map_bo(ggtt, dpt);
+ mutex_unlock(>lock);
+
+out_put:
+ xe_pm_runtime_put(xe);
+ return err;
+}
+
+static int
+xe_fb_dpt_alloc_pinned(struct i915_vma *vma, struct intel_framebuffer *fb)
+{
+ struct xe_bo *dpt;
+ int err;
+
+ dpt = xe_fb_dpt_alloc(fb);
