RE: Re: [PATCH] clk: imx8mp: Remove the none exist pcie clocks

2021-03-31 Thread Richard Zhu 

> -Original Message-
> From: Stephen Boyd 
> Sent: Wednesday, March 31, 2021 10:17 AM
> To: Richard Zhu ; Abel Vesa ;
> Jacky Bai ; shawn...@kernel.org
> Cc: dl-linux-imx ; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; linux-...@vger.kernel.org; Richard Zhu
> 
> Subject: Re: [PATCH] clk: imx8mp: Remove the none exist pcie clocks
> Quoting Richard Zhu (2021-03-15 01:17:47)
> > In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external
> > OSC or internal system PLL. It is configured in the IOMUX_GPR14
> > register directly, and can't be contolled by CCM at all.
> > Remove the PCIE PHY clock from clock driver to clean up codes.
> > There is only one PCIe in i.MX8MP, remove the none exist second PCIe
> > related clocks.
> > Remove the none exsits clocks IDs together.
> >
> > Signed-off-by: Richard Zhu 
> > Reviewed-by: Jason Liu 
> > ---
> 
> Any Fixes tag?
[Richard Zhu] Hi Stephen: 
The codes are changed refer to the RM document updates.
It doesn't fix a bug introduced from previous commit.

Best Regards
Richard Zhu

Re: [PATCH] clk: imx8mp: Remove the none exist pcie clocks

2021-03-30 Thread Stephen Boyd 
Quoting Richard Zhu (2021-03-15 01:17:47)
> In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external
> OSC or internal system PLL. It is configured in the IOMUX_GPR14 register
> directly, and can't be contolled by CCM at all.
> Remove the PCIE PHY clock from clock driver to clean up codes.
> There is only one PCIe in i.MX8MP, remove the none exist second PCIe
> related clocks.
> Remove the none exsits clocks IDs together.
> 
> Signed-off-by: Richard Zhu 
> Reviewed-by: Jason Liu 
> ---

Any Fixes tag?

Re: [PATCH] clk: imx8mp: Remove the none exist pcie clocks

2021-03-30 Thread Abel Vesa 
On 21-03-15 16:17:47, Richard Zhu wrote:
> In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external
> OSC or internal system PLL. It is configured in the IOMUX_GPR14 register
> directly, and can't be contolled by CCM at all.
> Remove the PCIE PHY clock from clock driver to clean up codes.
> There is only one PCIe in i.MX8MP, remove the none exist second PCIe
> related clocks.
> Remove the none exsits clocks IDs together.
> 
> Signed-off-by: Richard Zhu 
> Reviewed-by: Jason Liu 

Applied, thanks.

> ---
>  drivers/clk/imx/clk-imx8mp.c | 15 ---
>  include/dt-bindings/clock/imx8mp-clock.h |  3 ---
>  2 files changed, 18 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index 2f4e1d674e1c..afbeb6bf1909 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -152,10 +152,6 @@ static const char * const imx8mp_can2_sels[] = 
> {"osc_24m", "sys_pll2_200m", "sys
>   "sys_pll1_160m", 
> "sys_pll1_800m", "sys_pll3_out",
>   "sys_pll2_250m", 
> "audio_pll2_out", };
>  
> -static const char * const imx8mp_pcie_phy_sels[] = {"osc_24m", 
> "sys_pll2_100m", "sys_pll2_500m",
> - "clk_ext1", "clk_ext2", 
> "clk_ext3",
> - "clk_ext4", 
> "sys_pll1_400m", };
> -
>  static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", 
> "sys_pll2_200m", "sys_pll2_50m",
>   "sys_pll3_out", 
> "sys_pll2_100m", "sys_pll1_80m",
>   "sys_pll1_160m", 
> "sys_pll1_200m", };
> @@ -380,14 +376,6 @@ static const char * const imx8mp_memrepair_sels[] = 
> {"osc_24m", "sys_pll2_100m",
>   "sys_pll1_800m", 
> "sys_pll2_1000m", "sys_pll3_out",
>   "clk_ext3", 
> "audio_pll2_out", };
>  
> -static const char * const imx8mp_pcie2_ctrl_sels[] = {"osc_24m", 
> "sys_pll2_250m", "sys_pll2_200m",
> -   "sys_pll1_266m", 
> "sys_pll1_800m", "sys_pll2_500m",
> -   "sys_pll2_333m", 
> "sys_pll3_out", };
> -
> -static const char * const imx8mp_pcie2_phy_sels[] = {"osc_24m", 
> "sys_pll2_100m", "sys_pll2_500m",
> -  "clk_ext1", "clk_ext2", 
> "clk_ext3",
> -  "clk_ext4", 
> "sys_pll1_400m", };
> -
>  static const char * const imx8mp_media_mipi_test_byte_sels[] = {"osc_24m", 
> "sys_pll2_200m", "sys_pll2_50m",
>   "sys_pll3_out", 
> "sys_pll2_100m",
>   "sys_pll1_80m", 
> "sys_pll1_160m",
> @@ -585,7 +573,6 @@ static int imx8mp_clocks_probe(struct platform_device 
> *pdev)
>   hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", 
> imx8mp_vpu_g2_sels, ccm_base + 0xa180);
>   hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, 
> ccm_base + 0xa200);
>   hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, 
> ccm_base + 0xa280);
> - hws[IMX8MP_CLK_PCIE_PHY] = imx8m_clk_hw_composite("pcie_phy", 
> imx8mp_pcie_phy_sels, ccm_base + 0xa380);
>   hws[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_hw_composite("pcie_aux", 
> imx8mp_pcie_aux_sels, ccm_base + 0xa400);
>   hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, 
> ccm_base + 0xa480);
>   hws[IMX8MP_CLK_I2C6] = imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels, 
> ccm_base + 0xa500);
> @@ -643,8 +630,6 @@ static int imx8mp_clocks_probe(struct platform_device 
> *pdev)
>   hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = 
> imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base 
> + 0xbe80);
>   hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", 
> imx8mp_media_ldb_sels, ccm_base + 0xbf00);
>   hws[IMX8MP_CLK_MEMREPAIR] = 
> imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base 
> + 0xbf80);
> - hws[IMX8MP_CLK_PCIE2_CTRL] = imx8m_clk_hw_composite("pcie2_ctrl", 
> imx8mp_pcie2_ctrl_sels, ccm_base + 0xc000);
> - hws[IMX8MP_CLK_PCIE2_PHY] = imx8m_clk_hw_composite("pcie2_phy", 
> imx8mp_pcie2_phy_sels, ccm_base + 0xc080);
>   hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = 
> imx8m_clk_hw_composite("media_mipi_test_byte", 
> imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100);
>   hws[IMX8MP_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", 
> imx8mp_ecspi3_sels, ccm_base + 0xc180);
>   hws[IMX8MP_CLK_PDM] = imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, 
> ccm_base + 0xc200);
> diff --git a/include/dt-bindings/clock/imx8mp-clock.h 
> b/include/dt-bindings/clock/imx8mp-clock.h
>

[PATCH] clk: imx8mp: Remove the none exist pcie clocks

2021-03-15 Thread Richard Zhu 
In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external
OSC or internal system PLL. It is configured in the IOMUX_GPR14 register
directly, and can't be contolled by CCM at all.
Remove the PCIE PHY clock from clock driver to clean up codes.
There is only one PCIe in i.MX8MP, remove the none exist second PCIe
related clocks.
Remove the none exsits clocks IDs together.

Signed-off-by: Richard Zhu 
Reviewed-by: Jason Liu 
---
 drivers/clk/imx/clk-imx8mp.c | 15 ---
 include/dt-bindings/clock/imx8mp-clock.h |  3 ---
 2 files changed, 18 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 2f4e1d674e1c..afbeb6bf1909 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -152,10 +152,6 @@ static const char * const imx8mp_can2_sels[] = {"osc_24m", 
"sys_pll2_200m", "sys
"sys_pll1_160m", 
"sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", 
"audio_pll2_out", };
 
-static const char * const imx8mp_pcie_phy_sels[] = {"osc_24m", 
"sys_pll2_100m", "sys_pll2_500m",
-   "clk_ext1", "clk_ext2", 
"clk_ext3",
-   "clk_ext4", 
"sys_pll1_400m", };
-
 static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", 
"sys_pll2_200m", "sys_pll2_50m",
"sys_pll3_out", 
"sys_pll2_100m", "sys_pll1_80m",
"sys_pll1_160m", 
"sys_pll1_200m", };
@@ -380,14 +376,6 @@ static const char * const imx8mp_memrepair_sels[] = 
{"osc_24m", "sys_pll2_100m",
"sys_pll1_800m", 
"sys_pll2_1000m", "sys_pll3_out",
"clk_ext3", 
"audio_pll2_out", };
 
-static const char * const imx8mp_pcie2_ctrl_sels[] = {"osc_24m", 
"sys_pll2_250m", "sys_pll2_200m",
- "sys_pll1_266m", 
"sys_pll1_800m", "sys_pll2_500m",
- "sys_pll2_333m", 
"sys_pll3_out", };
-
-static const char * const imx8mp_pcie2_phy_sels[] = {"osc_24m", 
"sys_pll2_100m", "sys_pll2_500m",
-"clk_ext1", "clk_ext2", 
"clk_ext3",
-"clk_ext4", 
"sys_pll1_400m", };
-
 static const char * const imx8mp_media_mipi_test_byte_sels[] = {"osc_24m", 
"sys_pll2_200m", "sys_pll2_50m",
"sys_pll3_out", 
"sys_pll2_100m",
"sys_pll1_80m", 
"sys_pll1_160m",
@@ -585,7 +573,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", 
imx8mp_vpu_g2_sels, ccm_base + 0xa180);
hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, 
ccm_base + 0xa200);
hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, 
ccm_base + 0xa280);
-   hws[IMX8MP_CLK_PCIE_PHY] = imx8m_clk_hw_composite("pcie_phy", 
imx8mp_pcie_phy_sels, ccm_base + 0xa380);
hws[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_hw_composite("pcie_aux", 
imx8mp_pcie_aux_sels, ccm_base + 0xa400);
hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, 
ccm_base + 0xa480);
hws[IMX8MP_CLK_I2C6] = imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels, 
ccm_base + 0xa500);
@@ -643,8 +630,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = 
imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 
0xbe80);
hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", 
imx8mp_media_ldb_sels, ccm_base + 0xbf00);
hws[IMX8MP_CLK_MEMREPAIR] = 
imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base + 
0xbf80);
-   hws[IMX8MP_CLK_PCIE2_CTRL] = imx8m_clk_hw_composite("pcie2_ctrl", 
imx8mp_pcie2_ctrl_sels, ccm_base + 0xc000);
-   hws[IMX8MP_CLK_PCIE2_PHY] = imx8m_clk_hw_composite("pcie2_phy", 
imx8mp_pcie2_phy_sels, ccm_base + 0xc080);
hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = 
imx8m_clk_hw_composite("media_mipi_test_byte", 
imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100);
hws[IMX8MP_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", 
imx8mp_ecspi3_sels, ccm_base + 0xc180);
hws[IMX8MP_CLK_PDM] = imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, 
ccm_base + 0xc200);
diff --git a/include/dt-bindings/clock/imx8mp-clock.h 
b/include/dt-bindings/clock/imx8mp-clock.h
index e8d68fbb6e3f..43927a1b9e94 100644
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -125,7 +125,6 @@
 #define IMX8MP_CLK_CAN1116

Re: [PATCH] clk: imx8mp: Remove the none exist pcie clocks

2021-03-15 Thread Abel Vesa 
On 21-03-15 15:39:24, Richard Zhu wrote:
> In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external
> OSC or internal system PLL. It is configured in the IOMUX_GPR14 register
> directly, and can't be contolled by CCM at all.
> Remove the PCIE PHY clock from clock driver to clean up codes.
> There is only one PCIe in i.MX8MP, remove the none exist second PCIe
> related clocks.
> Remove the none exsits clocks IDs together.
> 

Please resend both patches and add linux-...@vger.kernel.org to cc.

> Signed-off-by: Richard Zhu 
> Reviewed-by: Jason Liu 
> ---
>  drivers/clk/imx/clk-imx8mp.c | 15 ---
>  include/dt-bindings/clock/imx8mp-clock.h |  3 ---
>  2 files changed, 18 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index 2f4e1d674e1c..afbeb6bf1909 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -152,10 +152,6 @@ static const char * const imx8mp_can2_sels[] = 
> {"osc_24m", "sys_pll2_200m", "sys
>   "sys_pll1_160m", 
> "sys_pll1_800m", "sys_pll3_out",
>   "sys_pll2_250m", 
> "audio_pll2_out", };
>  
> -static const char * const imx8mp_pcie_phy_sels[] = {"osc_24m", 
> "sys_pll2_100m", "sys_pll2_500m",
> - "clk_ext1", "clk_ext2", 
> "clk_ext3",
> - "clk_ext4", 
> "sys_pll1_400m", };
> -
>  static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", 
> "sys_pll2_200m", "sys_pll2_50m",
>   "sys_pll3_out", 
> "sys_pll2_100m", "sys_pll1_80m",
>   "sys_pll1_160m", 
> "sys_pll1_200m", };
> @@ -380,14 +376,6 @@ static const char * const imx8mp_memrepair_sels[] = 
> {"osc_24m", "sys_pll2_100m",
>   "sys_pll1_800m", 
> "sys_pll2_1000m", "sys_pll3_out",
>   "clk_ext3", 
> "audio_pll2_out", };
>  
> -static const char * const imx8mp_pcie2_ctrl_sels[] = {"osc_24m", 
> "sys_pll2_250m", "sys_pll2_200m",
> -   "sys_pll1_266m", 
> "sys_pll1_800m", "sys_pll2_500m",
> -   "sys_pll2_333m", 
> "sys_pll3_out", };
> -
> -static const char * const imx8mp_pcie2_phy_sels[] = {"osc_24m", 
> "sys_pll2_100m", "sys_pll2_500m",
> -  "clk_ext1", "clk_ext2", 
> "clk_ext3",
> -  "clk_ext4", 
> "sys_pll1_400m", };
> -
>  static const char * const imx8mp_media_mipi_test_byte_sels[] = {"osc_24m", 
> "sys_pll2_200m", "sys_pll2_50m",
>   "sys_pll3_out", 
> "sys_pll2_100m",
>   "sys_pll1_80m", 
> "sys_pll1_160m",
> @@ -585,7 +573,6 @@ static int imx8mp_clocks_probe(struct platform_device 
> *pdev)
>   hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", 
> imx8mp_vpu_g2_sels, ccm_base + 0xa180);
>   hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, 
> ccm_base + 0xa200);
>   hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, 
> ccm_base + 0xa280);
> - hws[IMX8MP_CLK_PCIE_PHY] = imx8m_clk_hw_composite("pcie_phy", 
> imx8mp_pcie_phy_sels, ccm_base + 0xa380);
>   hws[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_hw_composite("pcie_aux", 
> imx8mp_pcie_aux_sels, ccm_base + 0xa400);
>   hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, 
> ccm_base + 0xa480);
>   hws[IMX8MP_CLK_I2C6] = imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels, 
> ccm_base + 0xa500);
> @@ -643,8 +630,6 @@ static int imx8mp_clocks_probe(struct platform_device 
> *pdev)
>   hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = 
> imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base 
> + 0xbe80);
>   hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", 
> imx8mp_media_ldb_sels, ccm_base + 0xbf00);
>   hws[IMX8MP_CLK_MEMREPAIR] = 
> imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base 
> + 0xbf80);
> - hws[IMX8MP_CLK_PCIE2_CTRL] = imx8m_clk_hw_composite("pcie2_ctrl", 
> imx8mp_pcie2_ctrl_sels, ccm_base + 0xc000);
> - hws[IMX8MP_CLK_PCIE2_PHY] = imx8m_clk_hw_composite("pcie2_phy", 
> imx8mp_pcie2_phy_sels, ccm_base + 0xc080);
>   hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = 
> imx8m_clk_hw_composite("media_mipi_test_byte", 
> imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100);
>   hws[IMX8MP_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", 
> imx8mp_ecspi3_sels, ccm_base + 0xc180);
>   hws[IMX8MP_CLK_PDM] = imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, 
> ccm_base + 0xc200);
> diff --git a/include/dt-bindings/clock/imx8mp-clock.h

[PATCH] clk: imx8mp: Remove the none exist pcie clocks

2021-03-15 Thread Richard Zhu 
In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external
OSC or internal system PLL. It is configured in the IOMUX_GPR14 register
directly, and can't be contolled by CCM at all.
Remove the PCIE PHY clock from clock driver to clean up codes.
There is only one PCIe in i.MX8MP, remove the none exist second PCIe
related clocks.
Remove the none exsits clocks IDs together.

Signed-off-by: Richard Zhu 
Reviewed-by: Jason Liu 
---
 drivers/clk/imx/clk-imx8mp.c | 15 ---
 include/dt-bindings/clock/imx8mp-clock.h |  3 ---
 2 files changed, 18 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 2f4e1d674e1c..afbeb6bf1909 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -152,10 +152,6 @@ static const char * const imx8mp_can2_sels[] = {"osc_24m", 
"sys_pll2_200m", "sys
"sys_pll1_160m", 
"sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", 
"audio_pll2_out", };
 
-static const char * const imx8mp_pcie_phy_sels[] = {"osc_24m", 
"sys_pll2_100m", "sys_pll2_500m",
-   "clk_ext1", "clk_ext2", 
"clk_ext3",
-   "clk_ext4", 
"sys_pll1_400m", };
-
 static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", 
"sys_pll2_200m", "sys_pll2_50m",
"sys_pll3_out", 
"sys_pll2_100m", "sys_pll1_80m",
"sys_pll1_160m", 
"sys_pll1_200m", };
@@ -380,14 +376,6 @@ static const char * const imx8mp_memrepair_sels[] = 
{"osc_24m", "sys_pll2_100m",
"sys_pll1_800m", 
"sys_pll2_1000m", "sys_pll3_out",
"clk_ext3", 
"audio_pll2_out", };
 
-static const char * const imx8mp_pcie2_ctrl_sels[] = {"osc_24m", 
"sys_pll2_250m", "sys_pll2_200m",
- "sys_pll1_266m", 
"sys_pll1_800m", "sys_pll2_500m",
- "sys_pll2_333m", 
"sys_pll3_out", };
-
-static const char * const imx8mp_pcie2_phy_sels[] = {"osc_24m", 
"sys_pll2_100m", "sys_pll2_500m",
-"clk_ext1", "clk_ext2", 
"clk_ext3",
-"clk_ext4", 
"sys_pll1_400m", };
-
 static const char * const imx8mp_media_mipi_test_byte_sels[] = {"osc_24m", 
"sys_pll2_200m", "sys_pll2_50m",
"sys_pll3_out", 
"sys_pll2_100m",
"sys_pll1_80m", 
"sys_pll1_160m",
@@ -585,7 +573,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", 
imx8mp_vpu_g2_sels, ccm_base + 0xa180);
hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, 
ccm_base + 0xa200);
hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, 
ccm_base + 0xa280);
-   hws[IMX8MP_CLK_PCIE_PHY] = imx8m_clk_hw_composite("pcie_phy", 
imx8mp_pcie_phy_sels, ccm_base + 0xa380);
hws[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_hw_composite("pcie_aux", 
imx8mp_pcie_aux_sels, ccm_base + 0xa400);
hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, 
ccm_base + 0xa480);
hws[IMX8MP_CLK_I2C6] = imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels, 
ccm_base + 0xa500);
@@ -643,8 +630,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = 
imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 
0xbe80);
hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", 
imx8mp_media_ldb_sels, ccm_base + 0xbf00);
hws[IMX8MP_CLK_MEMREPAIR] = 
imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base + 
0xbf80);
-   hws[IMX8MP_CLK_PCIE2_CTRL] = imx8m_clk_hw_composite("pcie2_ctrl", 
imx8mp_pcie2_ctrl_sels, ccm_base + 0xc000);
-   hws[IMX8MP_CLK_PCIE2_PHY] = imx8m_clk_hw_composite("pcie2_phy", 
imx8mp_pcie2_phy_sels, ccm_base + 0xc080);
hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = 
imx8m_clk_hw_composite("media_mipi_test_byte", 
imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100);
hws[IMX8MP_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", 
imx8mp_ecspi3_sels, ccm_base + 0xc180);
hws[IMX8MP_CLK_PDM] = imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, 
ccm_base + 0xc200);
diff --git a/include/dt-bindings/clock/imx8mp-clock.h 
b/include/dt-bindings/clock/imx8mp-clock.h
index e8d68fbb6e3f..43927a1b9e94 100644
--- a/include/dt-bindings/clock/imx8mp-clock.h
+++ b/include/dt-bindings/clock/imx8mp-clock.h
@@ -125,7 +125,6 @@
 #define IMX8MP_CLK_CAN1116

RE: [PATCH] clk: imx8mp: Remove the none exist pcie clocks

2021-02-17 Thread Richard Zhu 

> -Original Message-
> From: Jacky Bai 
> Sent: Thursday, February 18, 2021 2:11 PM
> To: Richard Zhu ; shawn...@kernel.org
> Cc: dl-linux-imx ; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; Richard Zhu 
> Subject: RE: [PATCH] clk: imx8mp: Remove the none exist pcie clocks
> 
> > -Original Message-
> > From: Richard Zhu [mailto:hongxing@nxp.com]
> > Sent: Thursday, February 18, 2021 1:54 PM
> > To: shawn...@kernel.org; Jacky Bai 
> > Cc: dl-linux-imx ;
> > linux-arm-ker...@lists.infradead.org;
> > linux-kernel@vger.kernel.org; Richard Zhu 
> > Subject: [PATCH] clk: imx8mp: Remove the none exist pcie clocks
> >
> > In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external
> > OSC or internal system PLL. It is configured in the IOMUX_GPR14
> > register directly, and can't be contolled by CCM at all.
> > Remove the PCIE PHY clock from clock driver to clean up codes.
> > There is only one PCIe in i.MX8MP, remove the none exist second PCIe
> > related clocks.
> >
> 
> As Shawn suggested before, it is better to remove the corresponding clock ID
> in include/dt-bindings/clock/imx8mp-clock.h
> 
[Richard Zhu] Thanks for reminding.
Is it fine to leave the holes in the ID definitions in the header file if they 
are removed?

Best Regards
Richard Zhu
> BR
> Jacky Bai
> 
> > Signed-off-by: Richard Zhu 
> > Reviewed-by: Jason Liu 
> > ---
> >  drivers/clk/imx/clk-imx8mp.c | 15 ---
> >  1 file changed, 15 deletions(-)
> >
> > diff --git a/drivers/clk/imx/clk-imx8mp.c
> > b/drivers/clk/imx/clk-imx8mp.c index 2f4e1d674e1c..afbeb6bf1909 100644
> > --- a/drivers/clk/imx/clk-imx8mp.c
> > +++ b/drivers/clk/imx/clk-imx8mp.c
> > @@ -152,10 +152,6 @@ static const char * const imx8mp_can2_sels[] =
> > {"osc_24m", "sys_pll2_200m", "sys
> > "sys_pll1_160m", 
> > "sys_pll1_800m",
> "sys_pll3_out",
> > "sys_pll2_250m", 
> > "audio_pll2_out", };
> >
> > -static const char * const imx8mp_pcie_phy_sels[] = {"osc_24m",
> > "sys_pll2_100m", "sys_pll2_500m",
> > -   "clk_ext1", "clk_ext2", 
> > "clk_ext3",
> > -   "clk_ext4", 
> > "sys_pll1_400m", };
> > -
> >  static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m",
> > "sys_pll2_200m", "sys_pll2_50m",
> > "sys_pll3_out", 
> > "sys_pll2_100m",
> "sys_pll1_80m",
> > "sys_pll1_160m", 
> > "sys_pll1_200m", }; @@
> > -380,14 +376,6 @@ static const char * const imx8mp_memrepair_sels[] =
> > {"osc_24m", "sys_pll2_100m",
> > "sys_pll1_800m", 
> > "sys_pll2_1000m",
> "sys_pll3_out",
> > "clk_ext3", 
> > "audio_pll2_out", };
> >
> > -static const char * const imx8mp_pcie2_ctrl_sels[] = {"osc_24m",
> > "sys_pll2_250m", "sys_pll2_200m",
> > - "sys_pll1_266m", 
> > "sys_pll1_800m",
> > "sys_pll2_500m",
> > - "sys_pll2_333m", 
> > "sys_pll3_out", };
> > -
> > -static const char * const imx8mp_pcie2_phy_sels[] = {"osc_24m",
> > "sys_pll2_100m", "sys_pll2_500m",
> > -"clk_ext1", "clk_ext2", 
> > "clk_ext3",
> > -"clk_ext4", 
> > "sys_pll1_400m", };
> > -
> >  static const char * const imx8mp_media_mipi_test_byte_sels[] =
> > {"osc_24m", "sys_pll2_200m", "sys_pll2_50m",
> > "sys_pll3_out", 
> > "sys_pll2_100m",
> > "sys_pll1_80m", 
> > "sys_pll1_160m", @@
> > -585,7 +573,6 @@ static int imx8mp_clocks_probe(struct p

RE: [PATCH] clk: imx8mp: Remove the none exist pcie clocks

2021-02-17 Thread Jacky Bai 
> -Original Message-
> From: Richard Zhu
> Sent: Thursday, February 18, 2021 2:19 PM
> To: Jacky Bai ; shawn...@kernel.org
> Cc: dl-linux-imx ; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org
> Subject: RE: [PATCH] clk: imx8mp: Remove the none exist pcie clocks
> 
> 
> > -Original Message-
> > From: Jacky Bai 
> > Sent: Thursday, February 18, 2021 2:11 PM
> > To: Richard Zhu ; shawn...@kernel.org
> > Cc: dl-linux-imx ;
> > linux-arm-ker...@lists.infradead.org;
> > linux-kernel@vger.kernel.org; Richard Zhu 
> > Subject: RE: [PATCH] clk: imx8mp: Remove the none exist pcie clocks
> >
> > > -Original Message-
> > > From: Richard Zhu [mailto:hongxing@nxp.com]
> > > Sent: Thursday, February 18, 2021 1:54 PM
> > > To: shawn...@kernel.org; Jacky Bai 
> > > Cc: dl-linux-imx ;
> > > linux-arm-ker...@lists.infradead.org;
> > > linux-kernel@vger.kernel.org; Richard Zhu 
> > > Subject: [PATCH] clk: imx8mp: Remove the none exist pcie clocks
> > >
> > > In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from
> > > external OSC or internal system PLL. It is configured in the
> > > IOMUX_GPR14 register directly, and can't be contolled by CCM at all.
> > > Remove the PCIE PHY clock from clock driver to clean up codes.
> > > There is only one PCIe in i.MX8MP, remove the none exist second PCIe
> > > related clocks.
> > >
> >
> > As Shawn suggested before, it is better to remove the corresponding
> > clock ID in include/dt-bindings/clock/imx8mp-clock.h
> >
> [Richard Zhu] Thanks for reminding.
> Is it fine to leave the holes in the ID definitions in the header file if 
> they are
> removed?
> 

I think it is fine, need Shawn comments more.

> Best Regards
> Richard Zhu
> > BR
> > Jacky Bai
> >
> > > Signed-off-by: Richard Zhu 
> > > Reviewed-by: Jason Liu 
> > > ---
> > >  drivers/clk/imx/clk-imx8mp.c | 15 ---
> > >  1 file changed, 15 deletions(-)
> > >
> > > diff --git a/drivers/clk/imx/clk-imx8mp.c
> > > b/drivers/clk/imx/clk-imx8mp.c index 2f4e1d674e1c..afbeb6bf1909
> > > 100644
> > > --- a/drivers/clk/imx/clk-imx8mp.c
> > > +++ b/drivers/clk/imx/clk-imx8mp.c
> > > @@ -152,10 +152,6 @@ static const char * const imx8mp_can2_sels[] =
> > > {"osc_24m", "sys_pll2_200m", "sys
> > >   "sys_pll1_160m", 
> > > "sys_pll1_800m",
> > "sys_pll3_out",
> > >   "sys_pll2_250m", 
> > > "audio_pll2_out", };
> > >
> > > -static const char * const imx8mp_pcie_phy_sels[] = {"osc_24m",
> > > "sys_pll2_100m", "sys_pll2_500m",
> > > - "clk_ext1", "clk_ext2", 
> > > "clk_ext3",
> > > - "clk_ext4", 
> > > "sys_pll1_400m", };
> > > -
> > >  static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m",
> > > "sys_pll2_200m", "sys_pll2_50m",
> > >   "sys_pll3_out", 
> > > "sys_pll2_100m",
> > "sys_pll1_80m",
> > >   "sys_pll1_160m", 
> > > "sys_pll1_200m", };
> @@
> > > -380,14 +376,6 @@ static const char * const imx8mp_memrepair_sels[]
> > > = {"osc_24m", "sys_pll2_100m",
> > >   "sys_pll1_800m", 
> > > "sys_pll2_1000m",
> > "sys_pll3_out",
> > >   "clk_ext3", 
> > > "audio_pll2_out", };
> > >
> > > -static const char * const imx8mp_pcie2_ctrl_sels[] = {"osc_24m",
> > > "sys_pll2_250m", "sys_pll2_200m",
> > > -   "sys_pll1_266m", 
> > > "sys_pll1_800m",
> > > "sys_pll2_500m",
> > > -   "sys_pll2_333m", 
> > > "sys_pll3_out", };
> > > -
> > > -static const char * const imx8mp_pcie2_phy_sels[] = {"osc_24m",
> > >

RE: [PATCH] clk: imx8mp: Remove the none exist pcie clocks

2021-02-17 Thread Jacky Bai 
> -Original Message-
> From: Richard Zhu [mailto:hongxing@nxp.com]
> Sent: Thursday, February 18, 2021 1:54 PM
> To: shawn...@kernel.org; Jacky Bai 
> Cc: dl-linux-imx ; linux-arm-ker...@lists.infradead.org;
> linux-kernel@vger.kernel.org; Richard Zhu 
> Subject: [PATCH] clk: imx8mp: Remove the none exist pcie clocks
> 
> In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external OSC
> or internal system PLL. It is configured in the IOMUX_GPR14 register directly,
> and can't be contolled by CCM at all.
> Remove the PCIE PHY clock from clock driver to clean up codes.
> There is only one PCIe in i.MX8MP, remove the none exist second PCIe related
> clocks.
> 

As Shawn suggested before, it is better to remove the corresponding clock ID in 
include/dt-bindings/clock/imx8mp-clock.h

BR
Jacky Bai

> Signed-off-by: Richard Zhu 
> Reviewed-by: Jason Liu 
> ---
>  drivers/clk/imx/clk-imx8mp.c | 15 ---
>  1 file changed, 15 deletions(-)
> 
> diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
> index 2f4e1d674e1c..afbeb6bf1909 100644
> --- a/drivers/clk/imx/clk-imx8mp.c
> +++ b/drivers/clk/imx/clk-imx8mp.c
> @@ -152,10 +152,6 @@ static const char * const imx8mp_can2_sels[] =
> {"osc_24m", "sys_pll2_200m", "sys
>   "sys_pll1_160m", 
> "sys_pll1_800m",
> "sys_pll3_out",
>   "sys_pll2_250m", 
> "audio_pll2_out", };
> 
> -static const char * const imx8mp_pcie_phy_sels[] = {"osc_24m",
> "sys_pll2_100m", "sys_pll2_500m",
> - "clk_ext1", "clk_ext2", 
> "clk_ext3",
> - "clk_ext4", 
> "sys_pll1_400m", };
> -
>  static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m",
> "sys_pll2_200m", "sys_pll2_50m",
>   "sys_pll3_out", 
> "sys_pll2_100m",
> "sys_pll1_80m",
>   "sys_pll1_160m", 
> "sys_pll1_200m", }; @@
> -380,14 +376,6 @@ static const char * const imx8mp_memrepair_sels[] =
> {"osc_24m", "sys_pll2_100m",
>   "sys_pll1_800m", 
> "sys_pll2_1000m",
> "sys_pll3_out",
>   "clk_ext3", 
> "audio_pll2_out", };
> 
> -static const char * const imx8mp_pcie2_ctrl_sels[] = {"osc_24m",
> "sys_pll2_250m", "sys_pll2_200m",
> -   "sys_pll1_266m", 
> "sys_pll1_800m",
> "sys_pll2_500m",
> -   "sys_pll2_333m", 
> "sys_pll3_out", };
> -
> -static const char * const imx8mp_pcie2_phy_sels[] = {"osc_24m",
> "sys_pll2_100m", "sys_pll2_500m",
> -  "clk_ext1", "clk_ext2", 
> "clk_ext3",
> -  "clk_ext4", 
> "sys_pll1_400m", };
> -
>  static const char * const imx8mp_media_mipi_test_byte_sels[] =
> {"osc_24m", "sys_pll2_200m", "sys_pll2_50m",
>   "sys_pll3_out", 
> "sys_pll2_100m",
>   "sys_pll1_80m", 
> "sys_pll1_160m", @@
> -585,7 +573,6 @@ static int imx8mp_clocks_probe(struct platform_device
> *pdev)
>   hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2",
> imx8mp_vpu_g2_sels, ccm_base + 0xa180);
>   hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1",
> imx8mp_can1_sels, ccm_base + 0xa200);
>   hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2",
> imx8mp_can2_sels, ccm_base + 0xa280);
> - hws[IMX8MP_CLK_PCIE_PHY] = imx8m_clk_hw_composite("pcie_phy",
> imx8mp_pcie_phy_sels, ccm_base + 0xa380);
>   hws[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_hw_composite("pcie_aux",
> imx8mp_pcie_aux_sels, ccm_base + 0xa400);
>   hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5",
> imx8mp_i2c5_sels, ccm_base + 0xa480);
>   hws[IMX8MP_CLK_I2C6] = imx8m_clk_hw_composite("i2c6",
> imx8mp_i2c6_sels, ccm_base + 0xa500); @@ -64

[PATCH] clk: imx8mp: Remove the none exist pcie clocks

2021-02-17 Thread Richard Zhu 
In the i.MX8MP PCIe design, the PCIe PHY REF clock comes from external
OSC or internal system PLL. It is configured in the IOMUX_GPR14 register
directly, and can't be contolled by CCM at all.
Remove the PCIE PHY clock from clock driver to clean up codes.
There is only one PCIe in i.MX8MP, remove the none exist second PCIe
related clocks.

Signed-off-by: Richard Zhu 
Reviewed-by: Jason Liu 
---
 drivers/clk/imx/clk-imx8mp.c | 15 ---
 1 file changed, 15 deletions(-)

diff --git a/drivers/clk/imx/clk-imx8mp.c b/drivers/clk/imx/clk-imx8mp.c
index 2f4e1d674e1c..afbeb6bf1909 100644
--- a/drivers/clk/imx/clk-imx8mp.c
+++ b/drivers/clk/imx/clk-imx8mp.c
@@ -152,10 +152,6 @@ static const char * const imx8mp_can2_sels[] = {"osc_24m", 
"sys_pll2_200m", "sys
"sys_pll1_160m", 
"sys_pll1_800m", "sys_pll3_out",
"sys_pll2_250m", 
"audio_pll2_out", };
 
-static const char * const imx8mp_pcie_phy_sels[] = {"osc_24m", 
"sys_pll2_100m", "sys_pll2_500m",
-   "clk_ext1", "clk_ext2", 
"clk_ext3",
-   "clk_ext4", 
"sys_pll1_400m", };
-
 static const char * const imx8mp_pcie_aux_sels[] = {"osc_24m", 
"sys_pll2_200m", "sys_pll2_50m",
"sys_pll3_out", 
"sys_pll2_100m", "sys_pll1_80m",
"sys_pll1_160m", 
"sys_pll1_200m", };
@@ -380,14 +376,6 @@ static const char * const imx8mp_memrepair_sels[] = 
{"osc_24m", "sys_pll2_100m",
"sys_pll1_800m", 
"sys_pll2_1000m", "sys_pll3_out",
"clk_ext3", 
"audio_pll2_out", };
 
-static const char * const imx8mp_pcie2_ctrl_sels[] = {"osc_24m", 
"sys_pll2_250m", "sys_pll2_200m",
- "sys_pll1_266m", 
"sys_pll1_800m", "sys_pll2_500m",
- "sys_pll2_333m", 
"sys_pll3_out", };
-
-static const char * const imx8mp_pcie2_phy_sels[] = {"osc_24m", 
"sys_pll2_100m", "sys_pll2_500m",
-"clk_ext1", "clk_ext2", 
"clk_ext3",
-"clk_ext4", 
"sys_pll1_400m", };
-
 static const char * const imx8mp_media_mipi_test_byte_sels[] = {"osc_24m", 
"sys_pll2_200m", "sys_pll2_50m",
"sys_pll3_out", 
"sys_pll2_100m",
"sys_pll1_80m", 
"sys_pll1_160m",
@@ -585,7 +573,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_VPU_G2] = imx8m_clk_hw_composite("vpu_g2", 
imx8mp_vpu_g2_sels, ccm_base + 0xa180);
hws[IMX8MP_CLK_CAN1] = imx8m_clk_hw_composite("can1", imx8mp_can1_sels, 
ccm_base + 0xa200);
hws[IMX8MP_CLK_CAN2] = imx8m_clk_hw_composite("can2", imx8mp_can2_sels, 
ccm_base + 0xa280);
-   hws[IMX8MP_CLK_PCIE_PHY] = imx8m_clk_hw_composite("pcie_phy", 
imx8mp_pcie_phy_sels, ccm_base + 0xa380);
hws[IMX8MP_CLK_PCIE_AUX] = imx8m_clk_hw_composite("pcie_aux", 
imx8mp_pcie_aux_sels, ccm_base + 0xa400);
hws[IMX8MP_CLK_I2C5] = imx8m_clk_hw_composite("i2c5", imx8mp_i2c5_sels, 
ccm_base + 0xa480);
hws[IMX8MP_CLK_I2C6] = imx8m_clk_hw_composite("i2c6", imx8mp_i2c6_sels, 
ccm_base + 0xa500);
@@ -643,8 +630,6 @@ static int imx8mp_clocks_probe(struct platform_device *pdev)
hws[IMX8MP_CLK_MEDIA_CAM2_PIX] = 
imx8m_clk_hw_composite("media_cam2_pix", imx8mp_media_cam2_pix_sels, ccm_base + 
0xbe80);
hws[IMX8MP_CLK_MEDIA_LDB] = imx8m_clk_hw_composite("media_ldb", 
imx8mp_media_ldb_sels, ccm_base + 0xbf00);
hws[IMX8MP_CLK_MEMREPAIR] = 
imx8m_clk_hw_composite_critical("mem_repair", imx8mp_memrepair_sels, ccm_base + 
0xbf80);
-   hws[IMX8MP_CLK_PCIE2_CTRL] = imx8m_clk_hw_composite("pcie2_ctrl", 
imx8mp_pcie2_ctrl_sels, ccm_base + 0xc000);
-   hws[IMX8MP_CLK_PCIE2_PHY] = imx8m_clk_hw_composite("pcie2_phy", 
imx8mp_pcie2_phy_sels, ccm_base + 0xc080);
hws[IMX8MP_CLK_MEDIA_MIPI_TEST_BYTE] = 
imx8m_clk_hw_composite("media_mipi_test_byte", 
imx8mp_media_mipi_test_byte_sels, ccm_base + 0xc100);
hws[IMX8MP_CLK_ECSPI3] = imx8m_clk_hw_composite("ecspi3", 
imx8mp_ecspi3_sels, ccm_base + 0xc180);
hws[IMX8MP_CLK_PDM] = imx8m_clk_hw_composite("pdm", imx8mp_pdm_sels, 
ccm_base + 0xc200);
-- 
2.17.1