[PATCH v3 2/2] phy: add inno-usb2-phy driver for hi3798cv200 SoC

2018-02-28 Thread Shawn Guo 
From: Pengcheng Li 

It adds inno-usb2-phy driver for hi3798cv200 SoC USB 2.0 support.  One
inno-usb2-phy device can support up to two PHY ports.  While there is
device level reference clock and power reset to be controlled, each PHY
port has its own utmi reset that needs to assert/de-assert as needed.

Hi3798cv200 needs to access PHY port0 register via particular peripheral
syscon controller register to control PHY, like turning on PHY clock.

Signed-off-by: Pengcheng Li 
Signed-off-by: Jiancheng Xue 
Signed-off-by: Shawn Guo 
---
 drivers/phy/hisilicon/Kconfig  |  10 ++
 drivers/phy/hisilicon/Makefile |   1 +
 drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 218 +
 3 files changed, 229 insertions(+)
 create mode 100644 drivers/phy/hisilicon/phy-hisi-inno-usb2.c

diff --git a/drivers/phy/hisilicon/Kconfig b/drivers/phy/hisilicon/Kconfig
index 6164c4cd0f65..c21470eb7fba 100644
--- a/drivers/phy/hisilicon/Kconfig
+++ b/drivers/phy/hisilicon/Kconfig
@@ -11,6 +11,16 @@ config PHY_HI6220_USB
 
  To compile this driver as a module, choose M here.
 
+config PHY_HISI_INNO_USB2
+   tristate "HiSilicon INNO USB2 PHY support"
+   depends on (ARCH_HISI && ARM64) || COMPILE_TEST
+   select GENERIC_PHY
+   select MFD_SYSCON
+   help
+ Support for INNO USB2 PHY on HiSilicon SoCs. This Phy supports
+ USB 1.5Mb/s, USB 12Mb/s, USB 480Mb/s speeds. It supports one
+ USB host port to accept one USB device.
+
 config PHY_HIX5HD2_SATA
tristate "HIX5HD2 SATA PHY Driver"
depends on ARCH_HIX5HD2 && OF && HAS_IOMEM
diff --git a/drivers/phy/hisilicon/Makefile b/drivers/phy/hisilicon/Makefile
index 541b348187a8..e6c979458d3b 100644
--- a/drivers/phy/hisilicon/Makefile
+++ b/drivers/phy/hisilicon/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_PHY_HI6220_USB)   += phy-hi6220-usb.o
+obj-$(CONFIG_PHY_HISI_INNO_USB2)   += phy-hisi-inno-usb2.o
 obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o
diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c 
b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
new file mode 100644
index ..4b6b6fd43682
--- /dev/null
+++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
@@ -0,0 +1,218 @@
+/*
+ * HiSilicon INNO USB2 PHY Driver.
+ *
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define INNO_PHY_PORT_NUM  2
+#define REF_CLK_STABLE_TIME100 /* unit:us */
+#define UTMI_CLK_STABLE_TIME   200 /* unit:us */
+#define TEST_CLK_STABLE_TIME   2   /* unit:ms */
+#define PHY_CLK_STABLE_TIME2   /* unit:ms */
+#define UTMI_RST_COMPLETE_TIME 2   /* unit:ms */
+#define POR_RST_COMPLETE_TIME  300 /* unit:us */
+#define PHY_TEST_DATA  GENMASK(7, 0)
+#define PHY_TEST_ADDR  GENMASK(15, 8)
+#define PHY_TEST_PORT  GENMASK(18, 16)
+#define PHY_TEST_WREN  BIT(21)
+#define PHY_TEST_CLK   BIT(22) /* rising edge active */
+#define PHY_TEST_RST   BIT(23) /* low active */
+#define PHY_CLK_ENABLE BIT(2)
+
+struct hisi_inno_phy_port {
+   struct phy *phy;
+   struct device *dev;
+   struct reset_control *utmi_rst;
+};
+
+struct hisi_inno_phy_priv {
+   void __iomem *mmio;
+   struct clk *ref_clk;
+   struct reset_control *por_rst;
+   struct hisi_inno_phy_port ports[INNO_PHY_PORT_NUM];
+   u32 port_num;
+};
+
+static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv,
+   u8 port, u32 addr, u32 data)
+{
+   void __iomem *reg = priv->mmio;
+   u32 val;
+
+   val = (data & PHY_TEST_DATA) |
+ ((addr << 8) & PHY_TEST_ADDR) |
+ ((port << 16) & PHY_TEST_PORT) |
+ PHY_TEST_WREN | PHY_TEST_RST;
+   writel(val, reg);
+
+   val |= PHY_TEST_CLK;
+   writel(val, reg);
+
+   val &= ~PHY_TEST_CLK;
+   writel(val, reg);
+}
+
+static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv)
+{
+   /* The phy clk is controlled by the port0 register 0x06. */
+   hisi_inno_phy_write_reg(priv, 0, 0x06, PHY_CLK_ENABLE);
+

[PATCH v3 2/2] phy: add inno-usb2-phy driver for hi3798cv200 SoC

2018-02-28 Thread Shawn Guo 
From: Pengcheng Li 

It adds inno-usb2-phy driver for hi3798cv200 SoC USB 2.0 support.  One
inno-usb2-phy device can support up to two PHY ports.  While there is
device level reference clock and power reset to be controlled, each PHY
port has its own utmi reset that needs to assert/de-assert as needed.

Hi3798cv200 needs to access PHY port0 register via particular peripheral
syscon controller register to control PHY, like turning on PHY clock.

Signed-off-by: Pengcheng Li 
Signed-off-by: Jiancheng Xue 
Signed-off-by: Shawn Guo 
---
 drivers/phy/hisilicon/Kconfig  |  10 ++
 drivers/phy/hisilicon/Makefile |   1 +
 drivers/phy/hisilicon/phy-hisi-inno-usb2.c | 218 +
 3 files changed, 229 insertions(+)
 create mode 100644 drivers/phy/hisilicon/phy-hisi-inno-usb2.c

diff --git a/drivers/phy/hisilicon/Kconfig b/drivers/phy/hisilicon/Kconfig
index 6164c4cd0f65..c21470eb7fba 100644
--- a/drivers/phy/hisilicon/Kconfig
+++ b/drivers/phy/hisilicon/Kconfig
@@ -11,6 +11,16 @@ config PHY_HI6220_USB
 
  To compile this driver as a module, choose M here.
 
+config PHY_HISI_INNO_USB2
+   tristate "HiSilicon INNO USB2 PHY support"
+   depends on (ARCH_HISI && ARM64) || COMPILE_TEST
+   select GENERIC_PHY
+   select MFD_SYSCON
+   help
+ Support for INNO USB2 PHY on HiSilicon SoCs. This Phy supports
+ USB 1.5Mb/s, USB 12Mb/s, USB 480Mb/s speeds. It supports one
+ USB host port to accept one USB device.
+
 config PHY_HIX5HD2_SATA
tristate "HIX5HD2 SATA PHY Driver"
depends on ARCH_HIX5HD2 && OF && HAS_IOMEM
diff --git a/drivers/phy/hisilicon/Makefile b/drivers/phy/hisilicon/Makefile
index 541b348187a8..e6c979458d3b 100644
--- a/drivers/phy/hisilicon/Makefile
+++ b/drivers/phy/hisilicon/Makefile
@@ -1,2 +1,3 @@
 obj-$(CONFIG_PHY_HI6220_USB)   += phy-hi6220-usb.o
+obj-$(CONFIG_PHY_HISI_INNO_USB2)   += phy-hisi-inno-usb2.o
 obj-$(CONFIG_PHY_HIX5HD2_SATA) += phy-hix5hd2-sata.o
diff --git a/drivers/phy/hisilicon/phy-hisi-inno-usb2.c 
b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
new file mode 100644
index ..4b6b6fd43682
--- /dev/null
+++ b/drivers/phy/hisilicon/phy-hisi-inno-usb2.c
@@ -0,0 +1,218 @@
+/*
+ * HiSilicon INNO USB2 PHY Driver.
+ *
+ * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program. If not, see .
+ */
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+
+#define INNO_PHY_PORT_NUM  2
+#define REF_CLK_STABLE_TIME100 /* unit:us */
+#define UTMI_CLK_STABLE_TIME   200 /* unit:us */
+#define TEST_CLK_STABLE_TIME   2   /* unit:ms */
+#define PHY_CLK_STABLE_TIME2   /* unit:ms */
+#define UTMI_RST_COMPLETE_TIME 2   /* unit:ms */
+#define POR_RST_COMPLETE_TIME  300 /* unit:us */
+#define PHY_TEST_DATA  GENMASK(7, 0)
+#define PHY_TEST_ADDR  GENMASK(15, 8)
+#define PHY_TEST_PORT  GENMASK(18, 16)
+#define PHY_TEST_WREN  BIT(21)
+#define PHY_TEST_CLK   BIT(22) /* rising edge active */
+#define PHY_TEST_RST   BIT(23) /* low active */
+#define PHY_CLK_ENABLE BIT(2)
+
+struct hisi_inno_phy_port {
+   struct phy *phy;
+   struct device *dev;
+   struct reset_control *utmi_rst;
+};
+
+struct hisi_inno_phy_priv {
+   void __iomem *mmio;
+   struct clk *ref_clk;
+   struct reset_control *por_rst;
+   struct hisi_inno_phy_port ports[INNO_PHY_PORT_NUM];
+   u32 port_num;
+};
+
+static void hisi_inno_phy_write_reg(struct hisi_inno_phy_priv *priv,
+   u8 port, u32 addr, u32 data)
+{
+   void __iomem *reg = priv->mmio;
+   u32 val;
+
+   val = (data & PHY_TEST_DATA) |
+ ((addr << 8) & PHY_TEST_ADDR) |
+ ((port << 16) & PHY_TEST_PORT) |
+ PHY_TEST_WREN | PHY_TEST_RST;
+   writel(val, reg);
+
+   val |= PHY_TEST_CLK;
+   writel(val, reg);
+
+   val &= ~PHY_TEST_CLK;
+   writel(val, reg);
+}
+
+static void hisi_inno_phy_setup(struct hisi_inno_phy_priv *priv)
+{
+   /* The phy clk is controlled by the port0 register 0x06. */
+   hisi_inno_phy_write_reg(priv, 0, 0x06, PHY_CLK_ENABLE);
+   msleep(PHY_CLK_STABLE_TIME);
+}
+
+static int hisi_inno_phy_init(struct phy *phy)
+{
+   struct