[llvm-branch-commits] [clang] release/18.x: [clang-format] Fix a bug in formatting goto labels in macros (#92494) (PR #93494)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/93494 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] 768118d - [clang-format] Fix a bug in formatting goto labels in macros (#92494)
Author: Owen Pan
Date: 2024-06-05T14:56:32-07:00
New Revision: 768118d1ad38bf13c545828f67bd6b474d61fc55
URL:
https://github.com/llvm/llvm-project/commit/768118d1ad38bf13c545828f67bd6b474d61fc55
DIFF:
https://github.com/llvm/llvm-project/commit/768118d1ad38bf13c545828f67bd6b474d61fc55.diff
LOG: [clang-format] Fix a bug in formatting goto labels in macros (#92494)
Fixes #92300.
(cherry picked from commit d89f20058b45e3836527e816af7ed7372e1d554d)
Added:
Modified:
clang/lib/Format/UnwrappedLineParser.cpp
clang/unittests/Format/FormatTest.cpp
clang/unittests/Format/TokenAnnotatorTest.cpp
Removed:
diff --git a/clang/lib/Format/UnwrappedLineParser.cpp
b/clang/lib/Format/UnwrappedLineParser.cpp
index f70affb732a0d..179d77bf00491 100644
--- a/clang/lib/Format/UnwrappedLineParser.cpp
+++ b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -1185,12 +1185,6 @@ void UnwrappedLineParser::parsePPDefine() {
return;
}
- if (FormatTok->is(tok::identifier) &&
- Tokens->peekNextToken()->is(tok::colon)) {
-nextToken();
-nextToken();
- }
-
// Errors during a preprocessor directive can only affect the layout of the
// preprocessor directive, and thus we ignore them. An alternative approach
// would be to use the same approach we use on the file level (no
@@ -1671,7 +1665,8 @@ void UnwrappedLineParser::parseStructuralElement(
if (!Style.isJavaScript() && !Style.isVerilog() && !Style.isTableGen() &&
Tokens->peekNextToken()->is(tok::colon) && !Line->MustBeDeclaration) {
nextToken();
- Line->Tokens.begin()->Tok->MustBreakBefore = true;
+ if (!Line->InMacroBody || CurrentLines->size() > 1)
+Line->Tokens.begin()->Tok->MustBreakBefore = true;
FormatTok->setFinalizedType(TT_GotoLabelColon);
parseLabel(!Style.IndentGotoLabels);
if (HasLabel)
diff --git a/clang/unittests/Format/FormatTest.cpp
b/clang/unittests/Format/FormatTest.cpp
index d69632f7f0f8c..11ae41bc78ace 100644
--- a/clang/unittests/Format/FormatTest.cpp
+++ b/clang/unittests/Format/FormatTest.cpp
@@ -3118,6 +3118,7 @@ TEST_F(FormatTest, FormatsLabels) {
"g();\n"
" }\n"
"}");
+
FormatStyle Style = getLLVMStyle();
Style.IndentGotoLabels = false;
verifyFormat("void f() {\n"
@@ -3157,6 +3158,13 @@ TEST_F(FormatTest, FormatsLabels) {
" }\n"
"}",
Style);
+
+ Style.ColumnLimit = 15;
+ verifyFormat("#define FOO \\\n"
+ "label:\\\n"
+ " break;",
+ Style);
+
// The opening brace may either be on the same unwrapped line as the colon or
// on a separate one. The formatter should recognize both.
Style = getLLVMStyle();
diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp
b/clang/unittests/Format/TokenAnnotatorTest.cpp
index 44ebad9d5a872..dfa9c22430f36 100644
--- a/clang/unittests/Format/TokenAnnotatorTest.cpp
+++ b/clang/unittests/Format/TokenAnnotatorTest.cpp
@@ -2353,15 +2353,28 @@ TEST_F(TokenAnnotatorTest, UnderstandsLabels) {
auto Tokens = annotate("{ x: break; }");
ASSERT_EQ(Tokens.size(), 7u) << Tokens;
EXPECT_TOKEN(Tokens[2], tok::colon, TT_GotoLabelColon);
+
Tokens = annotate("{ case x: break; }");
ASSERT_EQ(Tokens.size(), 8u) << Tokens;
EXPECT_TOKEN(Tokens[3], tok::colon, TT_CaseLabelColon);
+
Tokens = annotate("{ x: { break; } }");
ASSERT_EQ(Tokens.size(), 9u) << Tokens;
EXPECT_TOKEN(Tokens[2], tok::colon, TT_GotoLabelColon);
+
Tokens = annotate("{ case x: { break; } }");
ASSERT_EQ(Tokens.size(), 10u) << Tokens;
EXPECT_TOKEN(Tokens[3], tok::colon, TT_CaseLabelColon);
+
+ Tokens = annotate("#define FOO label:");
+ ASSERT_EQ(Tokens.size(), 6u) << Tokens;
+ EXPECT_TOKEN(Tokens[4], tok::colon, TT_GotoLabelColon);
+
+ Tokens = annotate("#define FOO \\\n"
+"label: \\\n"
+" break;");
+ ASSERT_EQ(Tokens.size(), 8u) << Tokens;
+ EXPECT_TOKEN(Tokens[4], tok::colon, TT_GotoLabelColon);
}
TEST_F(TokenAnnotatorTest, UnderstandsNestedBlocks) {
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[llvm-branch-commits] [clang] release/18.x: [clang-format] Don't always break before << between str… (PR #94091)
tstellar wrote: @owenca Do you have a release note we can put in the release announcement? https://github.com/llvm/llvm-project/pull/94091 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [clang-format] Fix a bug in formatting goto labels in macros (#92494) (PR #93494)
tstellar wrote: @owenca Do you have a release note we can put in the release announcement? https://github.com/llvm/llvm-project/pull/93494 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [clang-format] Fix a bug in formatting goto labels in macros (#92494) (PR #93494)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/93494
>From 768118d1ad38bf13c545828f67bd6b474d61fc55 Mon Sep 17 00:00:00 2001
From: Owen Pan
Date: Tue, 21 May 2024 01:35:31 -0700
Subject: [PATCH] [clang-format] Fix a bug in formatting goto labels in macros
(#92494)
Fixes #92300.
(cherry picked from commit d89f20058b45e3836527e816af7ed7372e1d554d)
---
clang/lib/Format/UnwrappedLineParser.cpp | 9 ++---
clang/unittests/Format/FormatTest.cpp | 8
clang/unittests/Format/TokenAnnotatorTest.cpp | 13 +
3 files changed, 23 insertions(+), 7 deletions(-)
diff --git a/clang/lib/Format/UnwrappedLineParser.cpp
b/clang/lib/Format/UnwrappedLineParser.cpp
index f70affb732a0d..179d77bf00491 100644
--- a/clang/lib/Format/UnwrappedLineParser.cpp
+++ b/clang/lib/Format/UnwrappedLineParser.cpp
@@ -1185,12 +1185,6 @@ void UnwrappedLineParser::parsePPDefine() {
return;
}
- if (FormatTok->is(tok::identifier) &&
- Tokens->peekNextToken()->is(tok::colon)) {
-nextToken();
-nextToken();
- }
-
// Errors during a preprocessor directive can only affect the layout of the
// preprocessor directive, and thus we ignore them. An alternative approach
// would be to use the same approach we use on the file level (no
@@ -1671,7 +1665,8 @@ void UnwrappedLineParser::parseStructuralElement(
if (!Style.isJavaScript() && !Style.isVerilog() && !Style.isTableGen() &&
Tokens->peekNextToken()->is(tok::colon) && !Line->MustBeDeclaration) {
nextToken();
- Line->Tokens.begin()->Tok->MustBreakBefore = true;
+ if (!Line->InMacroBody || CurrentLines->size() > 1)
+Line->Tokens.begin()->Tok->MustBreakBefore = true;
FormatTok->setFinalizedType(TT_GotoLabelColon);
parseLabel(!Style.IndentGotoLabels);
if (HasLabel)
diff --git a/clang/unittests/Format/FormatTest.cpp
b/clang/unittests/Format/FormatTest.cpp
index d69632f7f0f8c..11ae41bc78ace 100644
--- a/clang/unittests/Format/FormatTest.cpp
+++ b/clang/unittests/Format/FormatTest.cpp
@@ -3118,6 +3118,7 @@ TEST_F(FormatTest, FormatsLabels) {
"g();\n"
" }\n"
"}");
+
FormatStyle Style = getLLVMStyle();
Style.IndentGotoLabels = false;
verifyFormat("void f() {\n"
@@ -3157,6 +3158,13 @@ TEST_F(FormatTest, FormatsLabels) {
" }\n"
"}",
Style);
+
+ Style.ColumnLimit = 15;
+ verifyFormat("#define FOO \\\n"
+ "label:\\\n"
+ " break;",
+ Style);
+
// The opening brace may either be on the same unwrapped line as the colon or
// on a separate one. The formatter should recognize both.
Style = getLLVMStyle();
diff --git a/clang/unittests/Format/TokenAnnotatorTest.cpp
b/clang/unittests/Format/TokenAnnotatorTest.cpp
index 44ebad9d5a872..dfa9c22430f36 100644
--- a/clang/unittests/Format/TokenAnnotatorTest.cpp
+++ b/clang/unittests/Format/TokenAnnotatorTest.cpp
@@ -2353,15 +2353,28 @@ TEST_F(TokenAnnotatorTest, UnderstandsLabels) {
auto Tokens = annotate("{ x: break; }");
ASSERT_EQ(Tokens.size(), 7u) << Tokens;
EXPECT_TOKEN(Tokens[2], tok::colon, TT_GotoLabelColon);
+
Tokens = annotate("{ case x: break; }");
ASSERT_EQ(Tokens.size(), 8u) << Tokens;
EXPECT_TOKEN(Tokens[3], tok::colon, TT_CaseLabelColon);
+
Tokens = annotate("{ x: { break; } }");
ASSERT_EQ(Tokens.size(), 9u) << Tokens;
EXPECT_TOKEN(Tokens[2], tok::colon, TT_GotoLabelColon);
+
Tokens = annotate("{ case x: { break; } }");
ASSERT_EQ(Tokens.size(), 10u) << Tokens;
EXPECT_TOKEN(Tokens[3], tok::colon, TT_CaseLabelColon);
+
+ Tokens = annotate("#define FOO label:");
+ ASSERT_EQ(Tokens.size(), 6u) << Tokens;
+ EXPECT_TOKEN(Tokens[4], tok::colon, TT_GotoLabelColon);
+
+ Tokens = annotate("#define FOO \\\n"
+"label: \\\n"
+" break;");
+ ASSERT_EQ(Tokens.size(), 8u) << Tokens;
+ EXPECT_TOKEN(Tokens[4], tok::colon, TT_GotoLabelColon);
}
TEST_F(TokenAnnotatorTest, UnderstandsNestedBlocks) {
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[llvm-branch-commits] [clang] release/18.x: [clang-format] Don't always break before << between str… (PR #94091)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/94091 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [clang-format] Fix a bug in formatting goto labels in macros (#92494) (PR #93494)
tstellar wrote: @owenca OK, can you give me more details: 1) How risky is this fix? 2) When was the last known working version of clang-format? https://github.com/llvm/llvm-project/pull/93494 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [clang-format] Don't always break before << between str… (PR #94091)
tstellar wrote: @owenca I'm only going to take regression fixes for 18.1.7. https://github.com/llvm/llvm-project/pull/94091 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [clang-format] Fix a bug in formatting goto labels in macros (#92494) (PR #93494)
tstellar wrote: @owenca I'm only going to take regression fixes for 18.1.7. https://github.com/llvm/llvm-project/pull/93494 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [PPCMergeStringPool] Only replace constant once (#92996) (PR #93442)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/93442 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [PPCMergeStringPool] Only replace constant once (#92996) (PR #93442)
tstellar wrote: What release note should we use for this change? https://github.com/llvm/llvm-project/pull/93442 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Bump version to 18.1.7 (PR #93723)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/93723 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Bump version to 18.1.7 (PR #93723)
tstellar wrote: @whentojump Yes, but I'm only going to accept critical fixes or regressions for this one. https://github.com/llvm/llvm-project/pull/93723 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Bump version to 18.1.7 (PR #93723)
https://github.com/tstellar edited https://github.com/llvm/llvm-project/pull/93723 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Bump version to 18.1.7 (PR #93723)
https://github.com/tstellar created https://github.com/llvm/llvm-project/pull/93723 None >From 828c6f81112b194cd322cc38ac50b0f2e3404587 Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Wed, 29 May 2024 12:37:48 -0700 Subject: [PATCH] Bump version to 18.1.7 --- llvm/CMakeLists.txt| 2 +- llvm/utils/lit/lit/__init__.py | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/CMakeLists.txt b/llvm/CMakeLists.txt index 26b7b01bb1f8d..51278943847aa 100644 --- a/llvm/CMakeLists.txt +++ b/llvm/CMakeLists.txt @@ -22,7 +22,7 @@ if(NOT DEFINED LLVM_VERSION_MINOR) set(LLVM_VERSION_MINOR 1) endif() if(NOT DEFINED LLVM_VERSION_PATCH) - set(LLVM_VERSION_PATCH 6) + set(LLVM_VERSION_PATCH 7) endif() if(NOT DEFINED LLVM_VERSION_SUFFIX) set(LLVM_VERSION_SUFFIX) diff --git a/llvm/utils/lit/lit/__init__.py b/llvm/utils/lit/lit/__init__.py index d8b0e3bd1c69e..5003d78ce5218 100644 --- a/llvm/utils/lit/lit/__init__.py +++ b/llvm/utils/lit/lit/__init__.py @@ -2,7 +2,7 @@ __author__ = "Daniel Dunbar" __email__ = "dan...@minormatter.com" -__versioninfo__ = (18, 1, 6) +__versioninfo__ = (18, 1, 7) __version__ = ".".join(str(v) for v in __versioninfo__) + "dev" __all__ = [] ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] Bump version to 18.1.7 (PR #93723)
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[llvm-branch-commits] [llvm] [workflows] Rework pre-commit CI for the release branch (PR #91550)
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[llvm-branch-commits] [libcxx] [libcxxabi] release/18.x: [libcxx][libcxxabi] Fix build for OpenBSD (#92186) (PR #92601)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/92601 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxxabi] 1118c2e - [libcxx][libcxxabi] Fix build for OpenBSD (#92186)
Author: John Ericson
Date: 2024-05-18T07:14:07-07:00
New Revision: 1118c2e05e67a36ed8ca250524525cdb66a55256
URL:
https://github.com/llvm/llvm-project/commit/1118c2e05e67a36ed8ca250524525cdb66a55256
DIFF:
https://github.com/llvm/llvm-project/commit/1118c2e05e67a36ed8ca250524525cdb66a55256.diff
LOG: [libcxx][libcxxabi] Fix build for OpenBSD (#92186)
- No indirect syscalls on OpenBSD. Instead there is a `futex` function
which issues a direct syscall.
- Monotonic clock is available despite the full POSIX suite of timers
not being available in its entirety.
See https://lists.boost.org/boost-bugs/2015/07/41690.php and
https://github.com/boostorg/log/commit/c98b1f459add14d5ce3e9e63e2469064601d7f71
for a description of an analogous problem and fix for Boost.
(cherry picked from commit af7467ce9f447d6fe977b73db1f03a18d6bbd511)
Added:
Modified:
libcxx/src/atomic.cpp
libcxx/src/chrono.cpp
libcxxabi/src/cxa_guard_impl.h
Removed:
diff --git a/libcxx/src/atomic.cpp b/libcxx/src/atomic.cpp
index 2f0389ae6974a..6b1f03c21bbcc 100644
--- a/libcxx/src/atomic.cpp
+++ b/libcxx/src/atomic.cpp
@@ -25,16 +25,28 @@
# if !defined(SYS_futex) && defined(SYS_futex_time64)
#define SYS_futex SYS_futex_time64
# endif
+# define _LIBCPP_FUTEX(...) syscall(SYS_futex, __VA_ARGS__)
#elif defined(__FreeBSD__)
# include
# include
+# define _LIBCPP_FUTEX(...) syscall(SYS_futex, __VA_ARGS__)
+
+#elif defined(__OpenBSD__)
+
+# include
+
+// OpenBSD has no indirect syscalls
+# define _LIBCPP_FUTEX(...) futex(__VA_ARGS__)
+
#else // <- Add other operating systems here
// Baseline needs no new headers
+# define _LIBCPP_FUTEX(...) syscall(SYS_futex, __VA_ARGS__)
+
#endif
_LIBCPP_BEGIN_NAMESPACE_STD
@@ -44,11 +56,11 @@ _LIBCPP_BEGIN_NAMESPACE_STD
static void
__libcpp_platform_wait_on_address(__cxx_atomic_contention_t const volatile*
__ptr, __cxx_contention_t __val) {
static constexpr timespec __timeout = {2, 0};
- syscall(SYS_futex, __ptr, FUTEX_WAIT_PRIVATE, __val, &__timeout, 0, 0);
+ _LIBCPP_FUTEX(__ptr, FUTEX_WAIT_PRIVATE, __val, &__timeout, 0, 0);
}
static void __libcpp_platform_wake_by_address(__cxx_atomic_contention_t const
volatile* __ptr, bool __notify_one) {
- syscall(SYS_futex, __ptr, FUTEX_WAKE_PRIVATE, __notify_one ? 1 : INT_MAX, 0,
0, 0);
+ _LIBCPP_FUTEX(__ptr, FUTEX_WAKE_PRIVATE, __notify_one ? 1 : INT_MAX, 0, 0,
0);
}
#elif defined(__APPLE__) && defined(_LIBCPP_USE_ULOCK)
diff --git a/libcxx/src/chrono.cpp b/libcxx/src/chrono.cpp
index c5e827c0cb59f..e7d6dfbc22924 100644
--- a/libcxx/src/chrono.cpp
+++ b/libcxx/src/chrono.cpp
@@ -31,7 +31,9 @@
# include // for gettimeofday and timeval
#endif
-#if defined(__APPLE__) || defined(__gnu_hurd__) || (defined(_POSIX_TIMERS) &&
_POSIX_TIMERS > 0)
+// OpenBSD does not have a fully conformant suite of POSIX timers, but
+// it does have clock_gettime and CLOCK_MONOTONIC which is all we need.
+#if defined(__APPLE__) || defined(__gnu_hurd__) || defined(__OpenBSD__) ||
(defined(_POSIX_TIMERS) && _POSIX_TIMERS > 0)
# define _LIBCPP_HAS_CLOCK_GETTIME
#endif
diff --git a/libcxxabi/src/cxa_guard_impl.h b/libcxxabi/src/cxa_guard_impl.h
index e00d54b3a7318..90d589be4d773 100644
--- a/libcxxabi/src/cxa_guard_impl.h
+++ b/libcxxabi/src/cxa_guard_impl.h
@@ -47,6 +47,9 @@
#include "__cxxabi_config.h"
#include "include/atomic_support.h" // from libc++
#if defined(__has_include)
+# if __has_include()
+#include
+# endif
# if __has_include()
#include
# endif
@@ -411,7 +414,18 @@ struct InitByteGlobalMutex {
// Futex Implementation
//===--===//
-#if defined(SYS_futex)
+#if defined(__OpenBSD__)
+void PlatformFutexWait(int* addr, int expect) {
+ constexpr int WAIT = 0;
+ futex(reinterpret_cast(addr), WAIT, expect, NULL, NULL);
+ __tsan_acquire(addr);
+}
+void PlatformFutexWake(int* addr) {
+ constexpr int WAKE = 1;
+ __tsan_release(addr);
+ futex(reinterpret_cast(addr), WAKE, INT_MAX, NULL, NULL);
+}
+#elif defined(SYS_futex)
void PlatformFutexWait(int* addr, int expect) {
constexpr int WAIT = 0;
syscall(SYS_futex, addr, WAIT, expect, 0);
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[llvm-branch-commits] [libcxx] [libcxxabi] release/18.x: [libcxx][libcxxabi] Fix build for OpenBSD (#92186) (PR #92601)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/92601
>From 1118c2e05e67a36ed8ca250524525cdb66a55256 Mon Sep 17 00:00:00 2001
From: John Ericson
Date: Fri, 17 May 2024 16:49:04 -0400
Subject: [PATCH] [libcxx][libcxxabi] Fix build for OpenBSD (#92186)
- No indirect syscalls on OpenBSD. Instead there is a `futex` function
which issues a direct syscall.
- Monotonic clock is available despite the full POSIX suite of timers
not being available in its entirety.
See https://lists.boost.org/boost-bugs/2015/07/41690.php and
https://github.com/boostorg/log/commit/c98b1f459add14d5ce3e9e63e2469064601d7f71
for a description of an analogous problem and fix for Boost.
(cherry picked from commit af7467ce9f447d6fe977b73db1f03a18d6bbd511)
---
libcxx/src/atomic.cpp | 16 ++--
libcxx/src/chrono.cpp | 4 +++-
libcxxabi/src/cxa_guard_impl.h | 16 +++-
3 files changed, 32 insertions(+), 4 deletions(-)
diff --git a/libcxx/src/atomic.cpp b/libcxx/src/atomic.cpp
index 2f0389ae6974a..6b1f03c21bbcc 100644
--- a/libcxx/src/atomic.cpp
+++ b/libcxx/src/atomic.cpp
@@ -25,16 +25,28 @@
# if !defined(SYS_futex) && defined(SYS_futex_time64)
#define SYS_futex SYS_futex_time64
# endif
+# define _LIBCPP_FUTEX(...) syscall(SYS_futex, __VA_ARGS__)
#elif defined(__FreeBSD__)
# include
# include
+# define _LIBCPP_FUTEX(...) syscall(SYS_futex, __VA_ARGS__)
+
+#elif defined(__OpenBSD__)
+
+# include
+
+// OpenBSD has no indirect syscalls
+# define _LIBCPP_FUTEX(...) futex(__VA_ARGS__)
+
#else // <- Add other operating systems here
// Baseline needs no new headers
+# define _LIBCPP_FUTEX(...) syscall(SYS_futex, __VA_ARGS__)
+
#endif
_LIBCPP_BEGIN_NAMESPACE_STD
@@ -44,11 +56,11 @@ _LIBCPP_BEGIN_NAMESPACE_STD
static void
__libcpp_platform_wait_on_address(__cxx_atomic_contention_t const volatile*
__ptr, __cxx_contention_t __val) {
static constexpr timespec __timeout = {2, 0};
- syscall(SYS_futex, __ptr, FUTEX_WAIT_PRIVATE, __val, &__timeout, 0, 0);
+ _LIBCPP_FUTEX(__ptr, FUTEX_WAIT_PRIVATE, __val, &__timeout, 0, 0);
}
static void __libcpp_platform_wake_by_address(__cxx_atomic_contention_t const
volatile* __ptr, bool __notify_one) {
- syscall(SYS_futex, __ptr, FUTEX_WAKE_PRIVATE, __notify_one ? 1 : INT_MAX, 0,
0, 0);
+ _LIBCPP_FUTEX(__ptr, FUTEX_WAKE_PRIVATE, __notify_one ? 1 : INT_MAX, 0, 0,
0);
}
#elif defined(__APPLE__) && defined(_LIBCPP_USE_ULOCK)
diff --git a/libcxx/src/chrono.cpp b/libcxx/src/chrono.cpp
index c5e827c0cb59f..e7d6dfbc22924 100644
--- a/libcxx/src/chrono.cpp
+++ b/libcxx/src/chrono.cpp
@@ -31,7 +31,9 @@
# include // for gettimeofday and timeval
#endif
-#if defined(__APPLE__) || defined(__gnu_hurd__) || (defined(_POSIX_TIMERS) &&
_POSIX_TIMERS > 0)
+// OpenBSD does not have a fully conformant suite of POSIX timers, but
+// it does have clock_gettime and CLOCK_MONOTONIC which is all we need.
+#if defined(__APPLE__) || defined(__gnu_hurd__) || defined(__OpenBSD__) ||
(defined(_POSIX_TIMERS) && _POSIX_TIMERS > 0)
# define _LIBCPP_HAS_CLOCK_GETTIME
#endif
diff --git a/libcxxabi/src/cxa_guard_impl.h b/libcxxabi/src/cxa_guard_impl.h
index e00d54b3a7318..90d589be4d773 100644
--- a/libcxxabi/src/cxa_guard_impl.h
+++ b/libcxxabi/src/cxa_guard_impl.h
@@ -47,6 +47,9 @@
#include "__cxxabi_config.h"
#include "include/atomic_support.h" // from libc++
#if defined(__has_include)
+# if __has_include()
+#include
+# endif
# if __has_include()
#include
# endif
@@ -411,7 +414,18 @@ struct InitByteGlobalMutex {
// Futex Implementation
//===--===//
-#if defined(SYS_futex)
+#if defined(__OpenBSD__)
+void PlatformFutexWait(int* addr, int expect) {
+ constexpr int WAIT = 0;
+ futex(reinterpret_cast(addr), WAIT, expect, NULL, NULL);
+ __tsan_acquire(addr);
+}
+void PlatformFutexWake(int* addr) {
+ constexpr int WAKE = 1;
+ __tsan_release(addr);
+ futex(reinterpret_cast(addr), WAKE, INT_MAX, NULL, NULL);
+}
+#elif defined(SYS_futex)
void PlatformFutexWait(int* addr, int expect) {
constexpr int WAIT = 0;
syscall(SYS_futex, addr, WAIT, expect, 0);
___
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[llvm-branch-commits] [clang] release/18.x: [clang] Don't assume location of compiler-rt for OpenBSD (#92183) (PR #92293)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/92293 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] 48c1364 - [clang] Don't assume location of compiler-rt for OpenBSD (#92183)
Author: John Ericson
Date: 2024-05-17T16:26:37-07:00
New Revision: 48c1364200b5649dda2f9ccbe382b0bd908b99de
URL:
https://github.com/llvm/llvm-project/commit/48c1364200b5649dda2f9ccbe382b0bd908b99de
DIFF:
https://github.com/llvm/llvm-project/commit/48c1364200b5649dda2f9ccbe382b0bd908b99de.diff
LOG: [clang] Don't assume location of compiler-rt for OpenBSD (#92183)
If the `/usr/lib/...` path where compiler-rt is conventionally installed
on OpenBSD does not exist, fall back to the regular logic to find it.
This is a minimal change to allow OpenBSD cross compilation from a
toolchain that doesn't adopt all of OpenBSD's monorepo's conventions.
(cherry picked from commit be10746f3a4381456eb5082a968766201c17ab5d)
Added:
Modified:
clang/lib/Driver/ToolChains/OpenBSD.cpp
Removed:
diff --git a/clang/lib/Driver/ToolChains/OpenBSD.cpp
b/clang/lib/Driver/ToolChains/OpenBSD.cpp
index fd6aa4d7e6844..00b6c520fcdd7 100644
--- a/clang/lib/Driver/ToolChains/OpenBSD.cpp
+++ b/clang/lib/Driver/ToolChains/OpenBSD.cpp
@@ -371,7 +371,8 @@ std::string OpenBSD::getCompilerRT(const ArgList ,
StringRef Component,
if (Component == "builtins") {
SmallString<128> Path(getDriver().SysRoot);
llvm::sys::path::append(Path, "/usr/lib/libcompiler_rt.a");
-return std::string(Path);
+if (getVFS().exists(Path))
+ return std::string(Path);
}
SmallString<128> P(getDriver().ResourceDir);
std::string CRTBasename =
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[llvm-branch-commits] [libcxx] [libcxxabi] release/18.x: [libcxx][libcxxabi] Fix build for OpenBSD (#92186) (PR #92601)
tstellar wrote: @brad0 Can you look at #92293 too? https://github.com/llvm/llvm-project/pull/92601 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [llvm] release/18.x: [LoongArch] Use R_LARCH_ALIGN with section symbol (#84741) (PR #88891)
https://github.com/tstellar demilestoned https://github.com/llvm/llvm-project/pull/88891 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [GlobalOpt] Don't replace aliasee with alias that has weak linkage (#91483) (PR #92468)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/92468 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 3d0752b - [GlobalOpt] Don't replace aliasee with alias that has weak linkage (#91483)
Author: DianQK
Date: 2024-05-17T13:50:38-07:00
New Revision: 3d0752b9492efd60e85aedec79676596af6fb4f8
URL:
https://github.com/llvm/llvm-project/commit/3d0752b9492efd60e85aedec79676596af6fb4f8
DIFF:
https://github.com/llvm/llvm-project/commit/3d0752b9492efd60e85aedec79676596af6fb4f8.diff
LOG: [GlobalOpt] Don't replace aliasee with alias that has weak linkage (#91483)
Fixes #91312.
Don't perform the transform if the alias may be replaced at link time.
(cherry picked from commit c79690040acf5bb3d857558b0878db47f7f23dc3)
Added:
llvm/test/Transforms/GlobalOpt/alias-weak.ll
Modified:
llvm/lib/Transforms/IPO/GlobalOpt.cpp
Removed:
diff --git a/llvm/lib/Transforms/IPO/GlobalOpt.cpp
b/llvm/lib/Transforms/IPO/GlobalOpt.cpp
index 951372adcfa93..619b3f612f25f 100644
--- a/llvm/lib/Transforms/IPO/GlobalOpt.cpp
+++ b/llvm/lib/Transforms/IPO/GlobalOpt.cpp
@@ -2212,6 +2212,9 @@ static bool mayHaveOtherReferences(GlobalValue , const
LLVMUsed ) {
static bool hasUsesToReplace(GlobalAlias , const LLVMUsed ,
bool ) {
+ if (GA.isWeakForLinker())
+return false;
+
RenameTarget = false;
bool Ret = false;
if (hasUseOtherThanLLVMUsed(GA, U))
diff --git a/llvm/test/Transforms/GlobalOpt/alias-weak.ll
b/llvm/test/Transforms/GlobalOpt/alias-weak.ll
new file mode 100644
index 0..aec2a56313b12
--- /dev/null
+++ b/llvm/test/Transforms/GlobalOpt/alias-weak.ll
@@ -0,0 +1,57 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --check-globals all --include-generated-funcs --version 4
+; RUN: opt < %s -passes=globalopt -S | FileCheck %s
+
+@f1_alias = linkonce_odr hidden alias void (), ptr @f1
+@f2_alias = linkonce_odr hidden alias void (), ptr @f2
+
+define void @foo() {
+ call void @f1_alias()
+ ret void
+}
+
+define void @bar() {
+ call void @f1()
+ ret void
+}
+
+define void @baz() {
+ call void @f2_alias()
+ ret void
+}
+
+; We cannot use `f1_alias` to replace `f1` because they are both in use
+; and `f1_alias` could be replaced at link time.
+define internal void @f1() {
+ ret void
+}
+
+; FIXME: We can use `f2_alias` to replace `f2` because `b2` is not in use.
+define internal void @f2() {
+ ret void
+}
+;.
+; CHECK: @f1_alias = linkonce_odr hidden alias void (), ptr @f1
+; CHECK: @f2_alias = linkonce_odr hidden alias void (), ptr @f2
+;.
+; CHECK-LABEL: define void @foo() local_unnamed_addr {
+; CHECK-NEXT:call void @f1_alias()
+; CHECK-NEXT:ret void
+;
+;
+; CHECK-LABEL: define void @bar() local_unnamed_addr {
+; CHECK-NEXT:call void @f1()
+; CHECK-NEXT:ret void
+;
+;
+; CHECK-LABEL: define void @baz() local_unnamed_addr {
+; CHECK-NEXT:call void @f2_alias()
+; CHECK-NEXT:ret void
+;
+;
+; CHECK-LABEL: define internal void @f1() {
+; CHECK-NEXT:ret void
+;
+;
+; CHECK-LABEL: define internal void @f2() {
+; CHECK-NEXT:ret void
+;
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[llvm-branch-commits] [llvm] release/18.x: [GlobalOpt] Don't replace aliasee with alias that has weak linkage (#91483) (PR #92468)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/92468
>From 3d0752b9492efd60e85aedec79676596af6fb4f8 Mon Sep 17 00:00:00 2001
From: DianQK
Date: Fri, 17 May 2024 05:51:49 +0800
Subject: [PATCH] [GlobalOpt] Don't replace aliasee with alias that has weak
linkage (#91483)
Fixes #91312.
Don't perform the transform if the alias may be replaced at link time.
(cherry picked from commit c79690040acf5bb3d857558b0878db47f7f23dc3)
---
llvm/lib/Transforms/IPO/GlobalOpt.cpp| 3 ++
llvm/test/Transforms/GlobalOpt/alias-weak.ll | 57
2 files changed, 60 insertions(+)
create mode 100644 llvm/test/Transforms/GlobalOpt/alias-weak.ll
diff --git a/llvm/lib/Transforms/IPO/GlobalOpt.cpp
b/llvm/lib/Transforms/IPO/GlobalOpt.cpp
index 951372adcfa93..619b3f612f25f 100644
--- a/llvm/lib/Transforms/IPO/GlobalOpt.cpp
+++ b/llvm/lib/Transforms/IPO/GlobalOpt.cpp
@@ -2212,6 +2212,9 @@ static bool mayHaveOtherReferences(GlobalValue , const
LLVMUsed ) {
static bool hasUsesToReplace(GlobalAlias , const LLVMUsed ,
bool ) {
+ if (GA.isWeakForLinker())
+return false;
+
RenameTarget = false;
bool Ret = false;
if (hasUseOtherThanLLVMUsed(GA, U))
diff --git a/llvm/test/Transforms/GlobalOpt/alias-weak.ll
b/llvm/test/Transforms/GlobalOpt/alias-weak.ll
new file mode 100644
index 0..aec2a56313b12
--- /dev/null
+++ b/llvm/test/Transforms/GlobalOpt/alias-weak.ll
@@ -0,0 +1,57 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --check-globals all --include-generated-funcs --version 4
+; RUN: opt < %s -passes=globalopt -S | FileCheck %s
+
+@f1_alias = linkonce_odr hidden alias void (), ptr @f1
+@f2_alias = linkonce_odr hidden alias void (), ptr @f2
+
+define void @foo() {
+ call void @f1_alias()
+ ret void
+}
+
+define void @bar() {
+ call void @f1()
+ ret void
+}
+
+define void @baz() {
+ call void @f2_alias()
+ ret void
+}
+
+; We cannot use `f1_alias` to replace `f1` because they are both in use
+; and `f1_alias` could be replaced at link time.
+define internal void @f1() {
+ ret void
+}
+
+; FIXME: We can use `f2_alias` to replace `f2` because `b2` is not in use.
+define internal void @f2() {
+ ret void
+}
+;.
+; CHECK: @f1_alias = linkonce_odr hidden alias void (), ptr @f1
+; CHECK: @f2_alias = linkonce_odr hidden alias void (), ptr @f2
+;.
+; CHECK-LABEL: define void @foo() local_unnamed_addr {
+; CHECK-NEXT:call void @f1_alias()
+; CHECK-NEXT:ret void
+;
+;
+; CHECK-LABEL: define void @bar() local_unnamed_addr {
+; CHECK-NEXT:call void @f1()
+; CHECK-NEXT:ret void
+;
+;
+; CHECK-LABEL: define void @baz() local_unnamed_addr {
+; CHECK-NEXT:call void @f2_alias()
+; CHECK-NEXT:ret void
+;
+;
+; CHECK-LABEL: define internal void @f1() {
+; CHECK-NEXT:ret void
+;
+;
+; CHECK-LABEL: define internal void @f2() {
+; CHECK-NEXT:ret void
+;
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[llvm-branch-commits] [llvm] [workflows] Fix libclang-abi-tests to work with new version scheme (PR #91096)
tstellar wrote: Merged: 6456ebbc18a6c2eaa2d7f6cfb7b2e5938e2daf7a https://github.com/llvm/llvm-project/pull/91096 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [workflows] Fix libclang-abi-tests to work with new version scheme (PR #91096)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91096 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [release/18.x] Backport fixes for ARM64EC thunk generation (PR #92580)
tstellar wrote: @dpaoliello (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/92580 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] [release/18.x] Backport fixes for ARM64EC thunk generation (PR #92580)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/92580 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 9208786 - [Arm64EC] Correctly handle sret in entry thunks. (#92326)
Author: Eli Friedman
Date: 2024-05-17T13:35:09-07:00
New Revision: 92087868d5d291464056066f3e193eca97621514
URL:
https://github.com/llvm/llvm-project/commit/92087868d5d291464056066f3e193eca97621514
DIFF:
https://github.com/llvm/llvm-project/commit/92087868d5d291464056066f3e193eca97621514.diff
LOG: [Arm64EC] Correctly handle sret in entry thunks. (#92326)
I accidentally left out the code to transfer sret attributes to entry
thunks, so values weren't being passed in the right registers, and the
sret pointer wasn't returned in the correct register.
Fixes #90229
Added:
Modified:
llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
index d4dd28aecac48..862aefe46193d 100644
--- a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
@@ -514,7 +514,14 @@ Function
*AArch64Arm64ECCallLowering::buildEntryThunk(Function *F) {
// Call the function passed to the thunk.
Value *Callee = Thunk->getArg(0);
Callee = IRB.CreateBitCast(Callee, PtrTy);
- Value *Call = IRB.CreateCall(Arm64Ty, Callee, Args);
+ CallInst *Call = IRB.CreateCall(Arm64Ty, Callee, Args);
+
+ auto SRetAttr = F->getAttributes().getParamAttr(0, Attribute::StructRet);
+ auto InRegAttr = F->getAttributes().getParamAttr(0, Attribute::InReg);
+ if (SRetAttr.isValid() && !InRegAttr.isValid()) {
+Thunk->addParamAttr(1, SRetAttr);
+Call->addParamAttr(0, SRetAttr);
+ }
Value *RetVal = Call;
if (TransformDirectToSRet) {
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
index c00c9bfe127e8..e9556b9d5cbee 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
@@ -222,12 +222,12 @@ define i8 @matches_has_sret() nounwind {
}
%TSRet = type { i64, i64 }
-define void @has_aligned_sret(ptr align 32 sret(%TSRet)) nounwind {
-; CHECK-LABEL:.def$ientry_thunk$cdecl$m16$v;
-; CHECK: .section
.wowthk$aa,"xr",discard,$ientry_thunk$cdecl$m16$v
+define void @has_aligned_sret(ptr align 32 sret(%TSRet), i32) nounwind {
+; CHECK-LABEL:.def$ientry_thunk$cdecl$m16$i8;
+; CHECK: .section
.wowthk$aa,"xr",discard,$ientry_thunk$cdecl$m16$i8
; CHECK: // %bb.0:
-; CHECK-NEXT: stp q6, q7, [sp, #-176]!// 32-byte Folded
Spill
-; CHECK-NEXT: .seh_save_any_reg_pxq6, 176
+; CHECK-NEXT: stp q6, q7, [sp, #-192]!// 32-byte Folded
Spill
+; CHECK-NEXT: .seh_save_any_reg_pxq6, 192
; CHECK-NEXT: stp q8, q9, [sp, #32] // 32-byte Folded
Spill
; CHECK-NEXT: .seh_save_any_reg_p q8, 32
; CHECK-NEXT: stp q10, q11, [sp, #64] // 32-byte Folded
Spill
@@ -236,17 +236,25 @@ define void @has_aligned_sret(ptr align 32 sret(%TSRet))
nounwind {
; CHECK-NEXT: .seh_save_any_reg_p q12, 96
; CHECK-NEXT: stp q14, q15, [sp, #128]// 32-byte Folded
Spill
; CHECK-NEXT: .seh_save_any_reg_p q14, 128
-; CHECK-NEXT: stp x29, x30, [sp, #160]// 16-byte Folded
Spill
-; CHECK-NEXT: .seh_save_fplr 160
-; CHECK-NEXT: add x29, sp, #160
-; CHECK-NEXT: .seh_add_fp 160
+; CHECK-NEXT: str x19, [sp, #160] // 8-byte Folded
Spill
+; CHECK-NEXT: .seh_save_reg x19, 160
+; CHECK-NEXT: stp x29, x30, [sp, #168]// 16-byte Folded
Spill
+; CHECK-NEXT: .seh_save_fplr 168
+; CHECK-NEXT: add x29, sp, #168
+; CHECK-NEXT: .seh_add_fp 168
; CHECK-NEXT: .seh_endprologue
+; CHECK-NEXT: mov x19, x0
+; CHECK-NEXT: mov x8, x0
+; CHECK-NEXT: mov x0, x1
; CHECK-NEXT: blr x9
; CHECK-NEXT: adrpx8, __os_arm64x_dispatch_ret
; CHECK-NEXT: ldr x0, [x8, :lo12:__os_arm64x_dispatch_ret]
+; CHECK-NEXT: mov x8, x19
; CHECK-NEXT: .seh_startepilogue
-; CHECK-NEXT: ldp x29, x30, [sp, #160]// 16-byte Folded
Reload
-; CHECK-NEXT: .seh_save_fplr 160
+; CHECK-NEXT: ldp x29, x30, [sp, #168]// 16-byte Folded
Reload
+; CHECK-NEXT: .seh_save_fplr 168
+; CHECK-NEXT: ldr x19, [sp, #160] // 8-byte Folded
Reload
+; CHECK-NEXT: .seh_save_reg x19, 160
; CHECK-NEXT: ldp q14, q15, [sp, #128]// 32-byte Folded
Reload
; CHECK-NEXT: .seh_save_any_reg_p q14, 128
; CHECK-NEXT: ldp q12, q13, [sp, #96] // 32-byte Folded
Reload
@@ -255,8 +263,8 @@ define void @has_aligned_sret(ptr align 32 sret(%TSRet))
nounwind {
; CHECK-NEXT: .seh_save_any_reg_p
[llvm-branch-commits] [llvm] bee6966 - [Arm64EC] Improve alignment mangling in arm64ec thunks. (#90115)
Author: Eli Friedman
Date: 2024-05-17T13:35:09-07:00
New Revision: bee6966d8efa18041e2e228c3bb7b09c4618677b
URL:
https://github.com/llvm/llvm-project/commit/bee6966d8efa18041e2e228c3bb7b09c4618677b
DIFF:
https://github.com/llvm/llvm-project/commit/bee6966d8efa18041e2e228c3bb7b09c4618677b.diff
LOG: [Arm64EC] Improve alignment mangling in arm64ec thunks. (#90115)
In some cases, MSVC's mangling for arm64ec thunks includes the alignment
of a struct. I added some code to try to match... but it never really
worked right. The issues:
- Alignment is only mangled if it's 16 or more (I guess the default is
supposed to be 8).
- Alignment isn't mangled on return values (since the memory is
allocated by the caller).
The current patch leaves hooks to make alignment mangling work... but
doesn't actually ever mangle alignment: clang never actually encodes a
relevant alignment into the IR. Once we get clang to emit the real
size/alignment of structs, we can start emitting it.
Added:
Modified:
llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
index 55c5bbc66a3f4..d4dd28aecac48 100644
--- a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
@@ -181,13 +181,14 @@ void AArch64Arm64ECCallLowering::getThunkArgTypes(
}
for (unsigned E = FT->getNumParams(); I != E; ++I) {
-Align ParamAlign = AttrList.getParamAlignment(I).valueOrOne();
#if 0
// FIXME: Need more information about argument size; see
// https://reviews.llvm.org/D132926
uint64_t ArgSizeBytes = AttrList.getParamArm64ECArgSizeBytes(I);
+Align ParamAlign = AttrList.getParamAlignment(I).valueOrOne();
#else
uint64_t ArgSizeBytes = 0;
+Align ParamAlign = Align();
#endif
Type *Arm64Ty, *X64Ty;
canonicalizeThunkType(FT->getParamType(I), ParamAlign,
@@ -297,7 +298,7 @@ void AArch64Arm64ECCallLowering::canonicalizeThunkType(
uint64_t TotalSizeBytes = ElementCnt * ElementSizePerBytes;
if (ElementTy->isFloatTy() || ElementTy->isDoubleTy()) {
Out << (ElementTy->isFloatTy() ? "F" : "D") << TotalSizeBytes;
- if (Alignment.value() >= 8 && !T->isPointerTy())
+ if (Alignment.value() >= 16 && !Ret)
Out << "a" << Alignment.value();
Arm64Ty = T;
if (TotalSizeBytes <= 8) {
@@ -328,7 +329,7 @@ void AArch64Arm64ECCallLowering::canonicalizeThunkType(
Out << "m";
if (TypeSize != 4)
Out << TypeSize;
- if (Alignment.value() >= 8 && !T->isPointerTy())
+ if (Alignment.value() >= 16 && !Ret)
Out << "a" << Alignment.value();
// FIXME: Try to canonicalize Arm64Ty more thoroughly?
Arm64Ty = T;
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
index bb9ba05f7a272..c00c9bfe127e8 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
@@ -223,8 +223,8 @@ define i8 @matches_has_sret() nounwind {
%TSRet = type { i64, i64 }
define void @has_aligned_sret(ptr align 32 sret(%TSRet)) nounwind {
-; CHECK-LABEL:.def$ientry_thunk$cdecl$m16a32$v;
-; CHECK: .section
.wowthk$aa,"xr",discard,$ientry_thunk$cdecl$m16a32$v
+; CHECK-LABEL:.def$ientry_thunk$cdecl$m16$v;
+; CHECK: .section
.wowthk$aa,"xr",discard,$ientry_thunk$cdecl$m16$v
; CHECK: // %bb.0:
; CHECK-NEXT: stp q6, q7, [sp, #-176]!// 32-byte Folded
Spill
; CHECK-NEXT: .seh_save_any_reg_pxq6, 176
@@ -457,7 +457,7 @@ define %T2 @simple_struct(%T1 %0, %T2 %1, %T3, %T4)
nounwind {
; CHECK-NEXT: .symidx $ientry_thunk$cdecl$i8$v
; CHECK-NEXT: .word 1
; CHECK-NEXT: .symidx "#has_aligned_sret"
-; CHECK-NEXT: .symidx $ientry_thunk$cdecl$m16a32$v
+; CHECK-NEXT: .symidx $ientry_thunk$cdecl$m16$v
; CHECK-NEXT: .word 1
; CHECK-NEXT: .symidx "#small_array"
; CHECK-NEXT: .symidx $ientry_thunk$cdecl$m2$m2F8
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
b/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
index 3b911e78aff2a..7a40fcd85ac58 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
@@ -236,8 +236,8 @@ declare void @has_sret(ptr sret([100 x i8])) nounwind;
%TSRet = type { i64, i64 }
declare void @has_aligned_sret(ptr align 32 sret(%TSRet)) nounwind;
-; CHECK-LABEL:.def$iexit_thunk$cdecl$m16a32$v;
-; CHECK: .section
.wowthk$aa,"xr",discard,$iexit_thunk$cdecl$m16a32$v
+; CHECK-LABEL:.def$iexit_thunk$cdecl$m16$v;
+; CHECK: .section
[llvm-branch-commits] [llvm] [release/18.x] Backport fixes for ARM64EC thunk generation (PR #92580)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/92580
>From bee6966d8efa18041e2e228c3bb7b09c4618677b Mon Sep 17 00:00:00 2001
From: Eli Friedman
Date: Fri, 26 Apr 2024 11:06:11 -0700
Subject: [PATCH 1/2] [Arm64EC] Improve alignment mangling in arm64ec thunks.
(#90115)
In some cases, MSVC's mangling for arm64ec thunks includes the alignment
of a struct. I added some code to try to match... but it never really
worked right. The issues:
- Alignment is only mangled if it's 16 or more (I guess the default is
supposed to be 8).
- Alignment isn't mangled on return values (since the memory is
allocated by the caller).
The current patch leaves hooks to make alignment mangling work... but
doesn't actually ever mangle alignment: clang never actually encodes a
relevant alignment into the IR. Once we get clang to emit the real
size/alignment of structs, we can start emitting it.
---
llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp | 7 ---
llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll | 6 +++---
llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll | 10 +-
3 files changed, 12 insertions(+), 11 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
index 55c5bbc66a3f4..d4dd28aecac48 100644
--- a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp
@@ -181,13 +181,14 @@ void AArch64Arm64ECCallLowering::getThunkArgTypes(
}
for (unsigned E = FT->getNumParams(); I != E; ++I) {
-Align ParamAlign = AttrList.getParamAlignment(I).valueOrOne();
#if 0
// FIXME: Need more information about argument size; see
// https://reviews.llvm.org/D132926
uint64_t ArgSizeBytes = AttrList.getParamArm64ECArgSizeBytes(I);
+Align ParamAlign = AttrList.getParamAlignment(I).valueOrOne();
#else
uint64_t ArgSizeBytes = 0;
+Align ParamAlign = Align();
#endif
Type *Arm64Ty, *X64Ty;
canonicalizeThunkType(FT->getParamType(I), ParamAlign,
@@ -297,7 +298,7 @@ void AArch64Arm64ECCallLowering::canonicalizeThunkType(
uint64_t TotalSizeBytes = ElementCnt * ElementSizePerBytes;
if (ElementTy->isFloatTy() || ElementTy->isDoubleTy()) {
Out << (ElementTy->isFloatTy() ? "F" : "D") << TotalSizeBytes;
- if (Alignment.value() >= 8 && !T->isPointerTy())
+ if (Alignment.value() >= 16 && !Ret)
Out << "a" << Alignment.value();
Arm64Ty = T;
if (TotalSizeBytes <= 8) {
@@ -328,7 +329,7 @@ void AArch64Arm64ECCallLowering::canonicalizeThunkType(
Out << "m";
if (TypeSize != 4)
Out << TypeSize;
- if (Alignment.value() >= 8 && !T->isPointerTy())
+ if (Alignment.value() >= 16 && !Ret)
Out << "a" << Alignment.value();
// FIXME: Try to canonicalize Arm64Ty more thoroughly?
Arm64Ty = T;
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
index bb9ba05f7a272..c00c9bfe127e8 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll
@@ -223,8 +223,8 @@ define i8 @matches_has_sret() nounwind {
%TSRet = type { i64, i64 }
define void @has_aligned_sret(ptr align 32 sret(%TSRet)) nounwind {
-; CHECK-LABEL:.def$ientry_thunk$cdecl$m16a32$v;
-; CHECK: .section
.wowthk$aa,"xr",discard,$ientry_thunk$cdecl$m16a32$v
+; CHECK-LABEL:.def$ientry_thunk$cdecl$m16$v;
+; CHECK: .section
.wowthk$aa,"xr",discard,$ientry_thunk$cdecl$m16$v
; CHECK: // %bb.0:
; CHECK-NEXT: stp q6, q7, [sp, #-176]!// 32-byte Folded
Spill
; CHECK-NEXT: .seh_save_any_reg_pxq6, 176
@@ -457,7 +457,7 @@ define %T2 @simple_struct(%T1 %0, %T2 %1, %T3, %T4)
nounwind {
; CHECK-NEXT: .symidx $ientry_thunk$cdecl$i8$v
; CHECK-NEXT: .word 1
; CHECK-NEXT: .symidx "#has_aligned_sret"
-; CHECK-NEXT: .symidx $ientry_thunk$cdecl$m16a32$v
+; CHECK-NEXT: .symidx $ientry_thunk$cdecl$m16$v
; CHECK-NEXT: .word 1
; CHECK-NEXT: .symidx "#small_array"
; CHECK-NEXT: .symidx $ientry_thunk$cdecl$m2$m2F8
diff --git a/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
b/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
index 3b911e78aff2a..7a40fcd85ac58 100644
--- a/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
+++ b/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll
@@ -236,8 +236,8 @@ declare void @has_sret(ptr sret([100 x i8])) nounwind;
%TSRet = type { i64, i64 }
declare void @has_aligned_sret(ptr align 32 sret(%TSRet)) nounwind;
-; CHECK-LABEL:.def$iexit_thunk$cdecl$m16a32$v;
-; CHECK: .section
.wowthk$aa,"xr",discard,$iexit_thunk$cdecl$m16a32$v
+; CHECK-LABEL:.def$iexit_thunk$cdecl$m16$v;
+; CHECK: .section
.wowthk$aa,"xr",discard,$iexit_thunk$cdecl$m16$v
; CHECK: // %bb.0:
; CHECK-NEXT:
[llvm-branch-commits] [llvm] release/18.x: [workflows] Fix libclang-abi-tests to work with new version scheme (#91865) (PR #92258)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/92258 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [workflows] Fix libclang-abi-tests to work with new version scheme (#91865) (PR #92258)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/92258
>From 6456ebbc18a6c2eaa2d7f6cfb7b2e5938e2daf7a Mon Sep 17 00:00:00 2001
From: Tom Stellard
Date: Wed, 15 May 2024 06:08:29 -0700
Subject: [PATCH] [workflows] Fix libclang-abi-tests to work with new version
scheme (#91865)
(cherry picked from commit d06270ee00e37b247eb99268fb2f106dbeee08ff)
---
.github/workflows/libclang-abi-tests.yml | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/.github/workflows/libclang-abi-tests.yml
b/.github/workflows/libclang-abi-tests.yml
index ccfc1e5fb8a74..972d21c3bcedf 100644
--- a/.github/workflows/libclang-abi-tests.yml
+++ b/.github/workflows/libclang-abi-tests.yml
@@ -33,7 +33,6 @@ jobs:
ABI_HEADERS: ${{ steps.vars.outputs.ABI_HEADERS }}
ABI_LIBS: ${{ steps.vars.outputs.ABI_LIBS }}
BASELINE_VERSION_MAJOR: ${{ steps.vars.outputs.BASELINE_VERSION_MAJOR }}
- BASELINE_VERSION_MINOR: ${{ steps.vars.outputs.BASELINE_VERSION_MINOR }}
LLVM_VERSION_MAJOR: ${{ steps.version.outputs.LLVM_VERSION_MAJOR }}
LLVM_VERSION_MINOR: ${{ steps.version.outputs.LLVM_VERSION_MINOR }}
LLVM_VERSION_PATCH: ${{ steps.version.outputs.LLVM_VERSION_PATCH }}
@@ -51,9 +50,9 @@ jobs:
id: vars
run: |
remote_repo='https://github.com/llvm/llvm-project'
- if [ ${{ steps.version.outputs.LLVM_VERSION_MINOR }} -ne 0 ] || [
${{ steps.version.outputs.LLVM_VERSION_PATCH }} -eq 0 ]; then
+ if [ ${{ steps.version.outputs.LLVM_VERSION_PATCH }} -eq 0 ]; then
major_version=$(( ${{ steps.version.outputs.LLVM_VERSION_MAJOR }}
- 1))
-baseline_ref="llvmorg-$major_version.0.0"
+baseline_ref="llvmorg-$major_version.1.0"
# If there is a minor release, we want to use that as the base
line.
minor_ref=$(git ls-remote --refs -t "$remote_repo"
llvmorg-"$major_version".[1-9].[0-9] | tail -n1 | grep -o 'llvmorg-.\+' || true)
@@ -75,7 +74,7 @@ jobs:
else
{
echo "BASELINE_VERSION_MAJOR=${{
steps.version.outputs.LLVM_VERSION_MAJOR }}"
- echo "BASELINE_REF=llvmorg-${{
steps.version.outputs.LLVM_VERSION_MAJOR }}.0.0"
+ echo "BASELINE_REF=llvmorg-${{
steps.version.outputs.LLVM_VERSION_MAJOR }}.1.0"
echo "ABI_HEADERS=."
echo "ABI_LIBS=libclang.so libclang-cpp.so"
} >> "$GITHUB_OUTPUT"
___
llvm-branch-commits mailing list
llvm-branch-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] release/18.x: [clang] Don't assume location of compiler-rt for OpenBSD (#92183) (PR #92293)
tstellar wrote: cc @epsilon-0 https://github.com/llvm/llvm-project/pull/92293 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [GlobalOpt] Don't replace aliasee with alias that has weak linkage (#91483) (PR #92468)
tstellar wrote: > Per [#91483 > (comment)](https://github.com/llvm/llvm-project/pull/91483#issuecomment-2116394616), > we still need to further investigate this issue, but it won't stop us from > backporting it. > > cc @MaskRay What exactly does this mean? Was there a bug in the original patch? https://github.com/llvm/llvm-project/pull/92468 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
tstellar wrote: @topperc (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] a7cd0c6 - [RISCV] Add a unaligned-scalar-mem feature like we had in clang 17.
Author: Craig Topper
Date: 2024-05-17T13:22:27-07:00
New Revision: a7cd0c61123889a632ceea67dc8c8e2c8753ae08
URL:
https://github.com/llvm/llvm-project/commit/a7cd0c61123889a632ceea67dc8c8e2c8753ae08
DIFF:
https://github.com/llvm/llvm-project/commit/a7cd0c61123889a632ceea67dc8c8e2c8753ae08.diff
LOG: [RISCV] Add a unaligned-scalar-mem feature like we had in clang 17.
This is ORed with the fast-unaligned-access feature which applies
to scalar and vector together.:
Added:
Modified:
llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
llvm/lib/Target/RISCV/RISCVFeatures.td
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/test/CodeGen/RISCV/memcpy-inline.ll
llvm/test/CodeGen/RISCV/memcpy.ll
llvm/test/CodeGen/RISCV/memset-inline.ll
llvm/test/CodeGen/RISCV/pr56110.ll
llvm/test/CodeGen/RISCV/unaligned-load-store.ll
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index 0a314fdd41cbe..89207640ee54a 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -317,8 +317,9 @@ bool
RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock ,
.addReg(MBBI->getOperand(1).getReg())
.add(MBBI->getOperand(2));
if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
-// FIXME: Zdinx RV32 can not work on unaligned memory.
-assert(!STI->hasFastUnalignedAccess());
+// FIXME: Zdinx RV32 can not work on unaligned scalar memory.
+assert(!STI->hasFastUnalignedAccess() &&
+ !STI->enableUnalignedScalarMem());
assert(MBBI->getOperand(2).getOffset() % 8 == 0);
MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 26451c80f57b4..1bb6b6a561f4a 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1025,6 +1025,11 @@ def FeatureFastUnalignedAccess
"true", "Has reasonably performant unaligned "
"loads and stores (both scalar and vector)">;
+def FeatureUnalignedScalarMem
+ : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",
+ "true", "Has reasonably performant unaligned scalar "
+ "loads and stores">;
+
def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
"UsePostRAScheduler", "true", "Schedule again after register allocation">;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d46093b9e260a..3fe7ddfdd4279 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1883,7 +1883,8 @@ bool
RISCVTargetLowering::shouldConvertConstantLoadToIntImm(const APInt ,
// replace. If we don't support unaligned scalar mem, prefer the constant
// pool.
// TODO: Can the caller pass down the alignment?
- if (!Subtarget.hasFastUnalignedAccess())
+ if (!Subtarget.hasFastUnalignedAccess() &&
+ !Subtarget.enableUnalignedScalarMem())
return true;
// Prefer to keep the load if it would require many instructions.
@@ -19772,8 +19773,10 @@ bool
RISCVTargetLowering::allowsMisalignedMemoryAccesses(
unsigned *Fast) const {
if (!VT.isVector()) {
if (Fast)
- *Fast = Subtarget.hasFastUnalignedAccess();
-return Subtarget.hasFastUnalignedAccess();
+ *Fast = Subtarget.hasFastUnalignedAccess() ||
+ Subtarget.enableUnalignedScalarMem();
+return Subtarget.hasFastUnalignedAccess() ||
+ Subtarget.enableUnalignedScalarMem();
}
// All vector implementations must support element alignment
diff --git a/llvm/test/CodeGen/RISCV/memcpy-inline.ll
b/llvm/test/CodeGen/RISCV/memcpy-inline.ll
index 343695ee37da8..709b8264b5833 100644
--- a/llvm/test/CodeGen/RISCV/memcpy-inline.ll
+++ b/llvm/test/CodeGen/RISCV/memcpy-inline.ll
@@ -7,6 +7,10 @@
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
; RUN: llc < %s -mtriple=riscv64 -mattr=+fast-unaligned-access \
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
+; RUN: llc < %s -mtriple=riscv32 -mattr=+unaligned-scalar-mem \
+; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
+; RUN: llc < %s -mtriple=riscv64 -mattr=+unaligned-scalar-mem \
+; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
; --
; Fully unaligned cases
diff --git a/llvm/test/CodeGen/RISCV/memcpy.ll
b/llvm/test/CodeGen/RISCV/memcpy.ll
index 12ec0881b20d9..f8f5d25947d7f 100644
--- a/llvm/test/CodeGen/RISCV/memcpy.ll
+++ b/llvm/test/CodeGen/RISCV/memcpy.ll
@@ -7,6 +7,10 @@
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
; RUN:
[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/92143
>From a7cd0c61123889a632ceea67dc8c8e2c8753ae08 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Thu, 16 May 2024 12:27:05 -0700
Subject: [PATCH] [RISCV] Add a unaligned-scalar-mem feature like we had in
clang 17.
This is ORed with the fast-unaligned-access feature which applies
to scalar and vector together.:
---
llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp | 5 +++--
llvm/lib/Target/RISCV/RISCVFeatures.td | 5 +
llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 9 ++---
llvm/test/CodeGen/RISCV/memcpy-inline.ll | 4
llvm/test/CodeGen/RISCV/memcpy.ll| 4
llvm/test/CodeGen/RISCV/memset-inline.ll | 4
llvm/test/CodeGen/RISCV/pr56110.ll | 1 +
llvm/test/CodeGen/RISCV/unaligned-load-store.ll | 4
8 files changed, 31 insertions(+), 5 deletions(-)
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
index 0a314fdd41cbe..89207640ee54a 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -317,8 +317,9 @@ bool
RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock ,
.addReg(MBBI->getOperand(1).getReg())
.add(MBBI->getOperand(2));
if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
-// FIXME: Zdinx RV32 can not work on unaligned memory.
-assert(!STI->hasFastUnalignedAccess());
+// FIXME: Zdinx RV32 can not work on unaligned scalar memory.
+assert(!STI->hasFastUnalignedAccess() &&
+ !STI->enableUnalignedScalarMem());
assert(MBBI->getOperand(2).getOffset() % 8 == 0);
MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td
b/llvm/lib/Target/RISCV/RISCVFeatures.td
index 26451c80f57b4..1bb6b6a561f4a 100644
--- a/llvm/lib/Target/RISCV/RISCVFeatures.td
+++ b/llvm/lib/Target/RISCV/RISCVFeatures.td
@@ -1025,6 +1025,11 @@ def FeatureFastUnalignedAccess
"true", "Has reasonably performant unaligned "
"loads and stores (both scalar and vector)">;
+def FeatureUnalignedScalarMem
+ : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem",
+ "true", "Has reasonably performant unaligned scalar "
+ "loads and stores">;
+
def FeaturePostRAScheduler : SubtargetFeature<"use-postra-scheduler",
"UsePostRAScheduler", "true", "Schedule again after register allocation">;
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index d46093b9e260a..3fe7ddfdd4279 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -1883,7 +1883,8 @@ bool
RISCVTargetLowering::shouldConvertConstantLoadToIntImm(const APInt ,
// replace. If we don't support unaligned scalar mem, prefer the constant
// pool.
// TODO: Can the caller pass down the alignment?
- if (!Subtarget.hasFastUnalignedAccess())
+ if (!Subtarget.hasFastUnalignedAccess() &&
+ !Subtarget.enableUnalignedScalarMem())
return true;
// Prefer to keep the load if it would require many instructions.
@@ -19772,8 +19773,10 @@ bool
RISCVTargetLowering::allowsMisalignedMemoryAccesses(
unsigned *Fast) const {
if (!VT.isVector()) {
if (Fast)
- *Fast = Subtarget.hasFastUnalignedAccess();
-return Subtarget.hasFastUnalignedAccess();
+ *Fast = Subtarget.hasFastUnalignedAccess() ||
+ Subtarget.enableUnalignedScalarMem();
+return Subtarget.hasFastUnalignedAccess() ||
+ Subtarget.enableUnalignedScalarMem();
}
// All vector implementations must support element alignment
diff --git a/llvm/test/CodeGen/RISCV/memcpy-inline.ll
b/llvm/test/CodeGen/RISCV/memcpy-inline.ll
index 343695ee37da8..709b8264b5833 100644
--- a/llvm/test/CodeGen/RISCV/memcpy-inline.ll
+++ b/llvm/test/CodeGen/RISCV/memcpy-inline.ll
@@ -7,6 +7,10 @@
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
; RUN: llc < %s -mtriple=riscv64 -mattr=+fast-unaligned-access \
; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
+; RUN: llc < %s -mtriple=riscv32 -mattr=+unaligned-scalar-mem \
+; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
+; RUN: llc < %s -mtriple=riscv64 -mattr=+unaligned-scalar-mem \
+; RUN: | FileCheck %s --check-prefixes=RV64-BOTH,RV64-FAST
; --
; Fully unaligned cases
diff --git a/llvm/test/CodeGen/RISCV/memcpy.ll
b/llvm/test/CodeGen/RISCV/memcpy.ll
index 12ec0881b20d9..f8f5d25947d7f 100644
--- a/llvm/test/CodeGen/RISCV/memcpy.ll
+++ b/llvm/test/CodeGen/RISCV/memcpy.ll
@@ -7,6 +7,10 @@
; RUN: | FileCheck %s --check-prefixes=RV32-BOTH,RV32-FAST
; RUN: llc < %s -mtriple=riscv64
[llvm-branch-commits] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
tstellar wrote: @topperc The plan is to release Friday. Do we have agreement on merging this updated patch? https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libcxx] release/18.x: change the visibility of libc++ header to public in libcxx module (PR #91182)
tstellar wrote: Is there a similar change that is proposed for the main branch? https://github.com/llvm/llvm-project/pull/91182 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
tstellar wrote: @topperc Can this be merged as is? There might not be time to get an updated patch merged before the last release. https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [InstCombine] Drop nuw flag when CtlzOp is a sub nuw (#91776) (PR #91917)
tstellar wrote: @dtcxzyw (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91917 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [InstCombine] Drop nuw flag when CtlzOp is a sub nuw (#91776) (PR #91917)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91917 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 2a4a0bf - Update llvm/test/Transforms/InstCombine/bit_ceil.ll
Author: Tom Stellard
Date: 2024-05-16T11:42:50-07:00
New Revision: 2a4a0bf1db8b828f104123de52d9f9cace020ed0
URL:
https://github.com/llvm/llvm-project/commit/2a4a0bf1db8b828f104123de52d9f9cace020ed0
DIFF:
https://github.com/llvm/llvm-project/commit/2a4a0bf1db8b828f104123de52d9f9cace020ed0.diff
LOG: Update llvm/test/Transforms/InstCombine/bit_ceil.ll
Co-authored-by: Yingwei Zheng
Added:
Modified:
llvm/test/Transforms/InstCombine/bit_ceil.ll
Removed:
diff --git a/llvm/test/Transforms/InstCombine/bit_ceil.ll
b/llvm/test/Transforms/InstCombine/bit_ceil.ll
index 63a5ae012eeb6..2c459a8c9d6db 100644
--- a/llvm/test/Transforms/InstCombine/bit_ceil.ll
+++ b/llvm/test/Transforms/InstCombine/bit_ceil.ll
@@ -287,7 +287,7 @@ define <4 x i32> @bit_ceil_v4i32(<4 x i32> %x) {
define i32 @pr91691(i32 %0) {
; CHECK-LABEL: @pr91691(
; CHECK-NEXT:[[TMP2:%.*]] = sub i32 -2, [[TMP0:%.*]]
-; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:[[TMP3:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[TMP2]], i1
false), !range [[RNG0]]
; CHECK-NEXT:[[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
; CHECK-NEXT:[[TMP5:%.*]] = and i32 [[TMP4]], 31
; CHECK-NEXT:[[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
@@ -305,7 +305,7 @@ define i32 @pr91691(i32 %0) {
define i32 @pr91691_keep_nsw(i32 %0) {
; CHECK-LABEL: @pr91691_keep_nsw(
; CHECK-NEXT:[[TMP2:%.*]] = sub nsw i32 -2, [[TMP0:%.*]]
-; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:[[TMP3:%.*]] = tail call i32 @llvm.ctlz.i32(i32 [[TMP2]], i1
false), !range [[RNG0]]
; CHECK-NEXT:[[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
; CHECK-NEXT:[[TMP5:%.*]] = and i32 [[TMP4]], 31
; CHECK-NEXT:[[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
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[llvm-branch-commits] [llvm] 26ccc6b - [InstCombine] Drop nuw flag when CtlzOp is a sub nuw (#91776)
Author: Yingwei Zheng
Date: 2024-05-16T11:42:50-07:00
New Revision: 26ccc6b5c1c73a92e5d08299065709e1d163b6c2
URL:
https://github.com/llvm/llvm-project/commit/26ccc6b5c1c73a92e5d08299065709e1d163b6c2
DIFF:
https://github.com/llvm/llvm-project/commit/26ccc6b5c1c73a92e5d08299065709e1d163b6c2.diff
LOG: [InstCombine] Drop nuw flag when CtlzOp is a sub nuw (#91776)
See the following case:
```
define i32 @src1(i32 %x) {
%dec = sub nuw i32 -2, %x
%ctlz = tail call i32 @llvm.ctlz.i32(i32 %dec, i1 false)
%sub = sub nsw i32 32, %ctlz
%shl = shl i32 1, %sub
%ugt = icmp ult i32 %x, -2
%sel = select i1 %ugt, i32 %shl, i32 1
ret i32 %sel
}
define i32 @tgt1(i32 %x) {
%dec = sub nuw i32 -2, %x
%ctlz = tail call i32 @llvm.ctlz.i32(i32 %dec, i1 false)
%sub = sub nsw i32 32, %ctlz
%and = and i32 %sub, 31
%shl = shl nuw i32 1, %and
ret i32 %shl
}
```
`nuw` in `%dec` should be dropped after the select instruction is
eliminated.
Alive2: https://alive2.llvm.org/ce/z/7S9529
Fixes https://github.com/llvm/llvm-project/issues/91691.
(cherry picked from commit b5f4210e9f51f938ae517f219f04f9ab431a2684)
Added:
Modified:
llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
llvm/test/Transforms/InstCombine/bit_ceil.ll
Removed:
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index 8cc7901cbac7f..86a39cf2ee93f 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -3201,7 +3201,8 @@ Instruction
*InstCombinerImpl::foldSelectOfBools(SelectInst ) {
// pattern.
static bool isSafeToRemoveBitCeilSelect(ICmpInst::Predicate Pred, Value *Cond0,
const APInt *Cond1, Value *CtlzOp,
-unsigned BitWidth) {
+unsigned BitWidth,
+bool ) {
// The challenge in recognizing std::bit_ceil(X) is that the operand is used
// for the CTLZ proper and select condition, each possibly with some
// operation like add and sub.
@@ -3224,6 +3225,8 @@ static bool
isSafeToRemoveBitCeilSelect(ICmpInst::Predicate Pred, Value *Cond0,
ConstantRange CR = ConstantRange::makeExactICmpRegion(
CmpInst::getInversePredicate(Pred), *Cond1);
+ ShouldDropNUW = false;
+
// Match the operation that's used to compute CtlzOp from CommonAncestor. If
// CtlzOp == CommonAncestor, return true as no operation is needed. If a
// match is found, execute the operation on CR, update CR, and return true.
@@ -3237,6 +3240,7 @@ static bool
isSafeToRemoveBitCeilSelect(ICmpInst::Predicate Pred, Value *Cond0,
return true;
}
if (match(CtlzOp, m_Sub(m_APInt(C), m_Specific(CommonAncestor {
+ ShouldDropNUW = true;
CR = ConstantRange(*C).sub(CR);
return true;
}
@@ -3306,14 +3310,20 @@ static Instruction *foldBitCeil(SelectInst ,
IRBuilderBase ) {
Pred = CmpInst::getInversePredicate(Pred);
}
+ bool ShouldDropNUW;
+
if (!match(FalseVal, m_One()) ||
!match(TrueVal,
m_OneUse(m_Shl(m_One(), m_OneUse(m_Sub(m_SpecificInt(BitWidth),
m_Value(Ctlz)) ||
!match(Ctlz, m_Intrinsic(m_Value(CtlzOp), m_Zero())) ||
- !isSafeToRemoveBitCeilSelect(Pred, Cond0, Cond1, CtlzOp, BitWidth))
+ !isSafeToRemoveBitCeilSelect(Pred, Cond0, Cond1, CtlzOp, BitWidth,
+ ShouldDropNUW))
return nullptr;
+ if (ShouldDropNUW)
+cast(CtlzOp)->setHasNoUnsignedWrap(false);
+
// Build 1 << (-CTLZ & (BitWidth-1)). The negation likely corresponds to a
// single hardware instruction as opposed to BitWidth - CTLZ, where BitWidth
// is an integer constant. Masking with BitWidth-1 comes free on some
diff --git a/llvm/test/Transforms/InstCombine/bit_ceil.ll
b/llvm/test/Transforms/InstCombine/bit_ceil.ll
index 52e70c78ba542..63a5ae012eeb6 100644
--- a/llvm/test/Transforms/InstCombine/bit_ceil.ll
+++ b/llvm/test/Transforms/InstCombine/bit_ceil.ll
@@ -284,6 +284,42 @@ define <4 x i32> @bit_ceil_v4i32(<4 x i32> %x) {
ret <4 x i32> %sel
}
+define i32 @pr91691(i32 %0) {
+; CHECK-LABEL: @pr91691(
+; CHECK-NEXT:[[TMP2:%.*]] = sub i32 -2, [[TMP0:%.*]]
+; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:[[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
+; CHECK-NEXT:[[TMP5:%.*]] = and i32 [[TMP4]], 31
+; CHECK-NEXT:[[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
+; CHECK-NEXT:ret i32 [[TMP6]]
+;
+ %2 = sub nuw i32 -2, %0
+ %3 = tail call i32 @llvm.ctlz.i32(i32 %2, i1 false)
+ %4 = sub i32 32, %3
+ %5 = shl i32 1, %4
+ %6 = icmp ult i32 %0, -2
+ %7 = select i1 %6, i32 %5, i32 1
+ ret i32 %7
+}
+
[llvm-branch-commits] [llvm] release/18.x Revert "[SLP]Fix a crash if the argument of call was affected by minbitwidth analysis." (PR #91682)
tstellar wrote: @AtariDreams (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91682 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x Revert "[SLP]Fix a crash if the argument of call was affected by minbitwidth analysis." (PR #91682)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91682 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] aa2549e - Revert "[SLP]Fix a crash if the argument of call was affected by minbitwidth analysis."
Author: Rose
Date: 2024-05-15T19:11:07-07:00
New Revision: aa2549e2bf1297af5fe2bc1903025e5d30e18f54
URL:
https://github.com/llvm/llvm-project/commit/aa2549e2bf1297af5fe2bc1903025e5d30e18f54
DIFF:
https://github.com/llvm/llvm-project/commit/aa2549e2bf1297af5fe2bc1903025e5d30e18f54.diff
LOG: Revert "[SLP]Fix a crash if the argument of call was affected by
minbitwidth analysis."
After reconsidering the words of @nikic, I have decided to revisit the patches
I suggested be backported. Upon further analysis, I think there is a high
likelihood that this change added to release 18.x was referencing a crash that
was caused by a PR that isn't added.
I will, however, keep the test that was added just in case.
This reverts commit 6e071cf30599e821be56b75e6041cfedb7872216.
Added:
Modified:
llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
Removed:
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 1fbd69e38eaee..0a9e2c7f49f55 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -11653,12 +11653,12 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool
PostponedPHIs) {
if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, -1))
TysForDecl.push_back(
FixedVectorType::get(CI->getType(), E->Scalars.size()));
- auto *CEI = cast(VL0);
for (unsigned I : seq(0, CI->arg_size())) {
ValueList OpVL;
// Some intrinsics have scalar arguments. This argument should not be
// vectorized.
if (UseIntrinsic && isVectorIntrinsicWithScalarOpAtArg(ID, I)) {
+ CallInst *CEI = cast(VL0);
ScalarArg = CEI->getArgOperand(I);
OpVecs.push_back(CEI->getArgOperand(I));
if (isVectorIntrinsicWithOverloadTypeAtArg(ID, I))
@@ -11671,25 +11671,6 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool
PostponedPHIs) {
LLVM_DEBUG(dbgs() << "SLP: Diamond merged for " << *VL0 << ".\n");
return E->VectorizedValue;
}
-auto GetOperandSignedness = [&](unsigned Idx) {
- const TreeEntry *OpE = getOperandEntry(E, Idx);
- bool IsSigned = false;
- auto It = MinBWs.find(OpE);
- if (It != MinBWs.end())
-IsSigned = It->second.second;
- else
-IsSigned = any_of(OpE->Scalars, [&](Value *R) {
- return !isKnownNonNegative(R, SimplifyQuery(*DL));
-});
- return IsSigned;
-};
-ScalarArg = CEI->getArgOperand(I);
-if (cast(OpVec->getType())->getElementType() !=
-ScalarArg->getType()) {
- auto *CastTy = FixedVectorType::get(ScalarArg->getType(),
- VecTy->getNumElements());
- OpVec = Builder.CreateIntCast(OpVec, CastTy,
GetOperandSignedness(I));
-}
LLVM_DEBUG(dbgs() << "SLP: OpVec[" << I << "]: " << *OpVec << "\n");
OpVecs.push_back(OpVec);
if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, I))
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[llvm-branch-commits] [llvm] release/18.x Revert "[SLP]Fix a crash if the argument of call was affected by minbitwidth analysis." (PR #91682)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/91682
>From aa2549e2bf1297af5fe2bc1903025e5d30e18f54 Mon Sep 17 00:00:00 2001
From: Rose
Date: Thu, 9 May 2024 19:52:24 -0400
Subject: [PATCH] Revert "[SLP]Fix a crash if the argument of call was affected
by minbitwidth analysis."
After reconsidering the words of @nikic, I have decided to revisit the patches
I suggested be backported. Upon further analysis, I think there is a high
likelihood that this change added to release 18.x was referencing a crash that
was caused by a PR that isn't added.
I will, however, keep the test that was added just in case.
This reverts commit 6e071cf30599e821be56b75e6041cfedb7872216.
---
.../Transforms/Vectorize/SLPVectorizer.cpp| 21 +--
1 file changed, 1 insertion(+), 20 deletions(-)
diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
index 1fbd69e38eaee..0a9e2c7f49f55 100644
--- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
+++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp
@@ -11653,12 +11653,12 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool
PostponedPHIs) {
if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, -1))
TysForDecl.push_back(
FixedVectorType::get(CI->getType(), E->Scalars.size()));
- auto *CEI = cast(VL0);
for (unsigned I : seq(0, CI->arg_size())) {
ValueList OpVL;
// Some intrinsics have scalar arguments. This argument should not be
// vectorized.
if (UseIntrinsic && isVectorIntrinsicWithScalarOpAtArg(ID, I)) {
+ CallInst *CEI = cast(VL0);
ScalarArg = CEI->getArgOperand(I);
OpVecs.push_back(CEI->getArgOperand(I));
if (isVectorIntrinsicWithOverloadTypeAtArg(ID, I))
@@ -11671,25 +11671,6 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool
PostponedPHIs) {
LLVM_DEBUG(dbgs() << "SLP: Diamond merged for " << *VL0 << ".\n");
return E->VectorizedValue;
}
-auto GetOperandSignedness = [&](unsigned Idx) {
- const TreeEntry *OpE = getOperandEntry(E, Idx);
- bool IsSigned = false;
- auto It = MinBWs.find(OpE);
- if (It != MinBWs.end())
-IsSigned = It->second.second;
- else
-IsSigned = any_of(OpE->Scalars, [&](Value *R) {
- return !isKnownNonNegative(R, SimplifyQuery(*DL));
-});
- return IsSigned;
-};
-ScalarArg = CEI->getArgOperand(I);
-if (cast(OpVec->getType())->getElementType() !=
-ScalarArg->getType()) {
- auto *CastTy = FixedVectorType::get(ScalarArg->getType(),
- VecTy->getNumElements());
- OpVec = Builder.CreateIntCast(OpVec, CastTy,
GetOperandSignedness(I));
-}
LLVM_DEBUG(dbgs() << "SLP: OpVec[" << I << "]: " << *OpVec << "\n");
OpVecs.push_back(OpVec);
if (UseIntrinsic && isVectorIntrinsicWithOverloadTypeAtArg(ID, I))
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[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)
tstellar wrote: @DianQK (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/92129 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/92129 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] c6d5546 - [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072)
Author: Thorsten Schütt
Date: 2024-05-15T19:08:49-07:00
New Revision: c6d5546189311e81aeee251d0d40dd970ae2f70e
URL:
https://github.com/llvm/llvm-project/commit/c6d5546189311e81aeee251d0d40dd970ae2f70e
DIFF:
https://github.com/llvm/llvm-project/commit/c6d5546189311e81aeee251d0d40dd970ae2f70e.diff
LOG: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072)
Fixes https://github.com/llvm/llvm-project/issues/92062
(cherry picked from commit d422e90fcb68749918ddd86c94188807efce)
Added:
llvm/test/CodeGen/AArch64/pr92062.ll
Modified:
llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
Removed:
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index b8e5e7bbdaba7..06cdd7e4ef481 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -623,8 +623,11 @@ bool AArch64RegisterBankInfo::isLoadFromFPType(const
MachineInstr ) const {
EltTy = GV->getValueType();
// Look at the first element of the struct to determine the type we are
// loading
-while (StructType *StructEltTy = dyn_cast(EltTy))
+while (StructType *StructEltTy = dyn_cast(EltTy)) {
+ if (StructEltTy->getNumElements() == 0)
+break;
EltTy = StructEltTy->getTypeAtIndex(0U);
+}
// Look at the first element of the array to determine its type
if (isa(EltTy))
EltTy = EltTy->getArrayElementType();
diff --git a/llvm/test/CodeGen/AArch64/pr92062.ll
b/llvm/test/CodeGen/AArch64/pr92062.ll
new file mode 100644
index 0..6111ee0fbe18f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr92062.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mtriple=aarch64 -O0 -global-isel %s -o - 2>&1 | FileCheck %s
+
+target triple = "arm64"
+
+@p = external global { {}, { ptr } }
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK: // %bb.0: // %bb
+; CHECK-NEXT:adrp x8, :got:p
+; CHECK-NEXT:ldr x8, [x8, :got_lo12:p]
+; CHECK-NEXT:ldr x8, [x8]
+; CHECK-NEXT:mov x9, xzr
+; CHECK-NEXT:str x8, [x9]
+; CHECK-NEXT:ret
+bb:
+ %i1 = load ptr, ptr @p, align 8
+ store ptr %i1, ptr null, align 8
+ ret void
+}
___
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[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/92129
>From c6d5546189311e81aeee251d0d40dd970ae2f70e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?=
Date: Tue, 14 May 2024 15:54:05 +0200
Subject: [PATCH] [GlobalIsel][AArch64] fix out of range access in
regbankselect (#92072)
Fixes https://github.com/llvm/llvm-project/issues/92062
(cherry picked from commit d422e90fcb68749918ddd86c94188807efce)
---
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 5 -
llvm/test/CodeGen/AArch64/pr92062.ll | 21 +++
2 files changed, 25 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AArch64/pr92062.ll
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index b8e5e7bbdaba7..06cdd7e4ef481 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -623,8 +623,11 @@ bool AArch64RegisterBankInfo::isLoadFromFPType(const
MachineInstr ) const {
EltTy = GV->getValueType();
// Look at the first element of the struct to determine the type we are
// loading
-while (StructType *StructEltTy = dyn_cast(EltTy))
+while (StructType *StructEltTy = dyn_cast(EltTy)) {
+ if (StructEltTy->getNumElements() == 0)
+break;
EltTy = StructEltTy->getTypeAtIndex(0U);
+}
// Look at the first element of the array to determine its type
if (isa(EltTy))
EltTy = EltTy->getArrayElementType();
diff --git a/llvm/test/CodeGen/AArch64/pr92062.ll
b/llvm/test/CodeGen/AArch64/pr92062.ll
new file mode 100644
index 0..6111ee0fbe18f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr92062.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mtriple=aarch64 -O0 -global-isel %s -o - 2>&1 | FileCheck %s
+
+target triple = "arm64"
+
+@p = external global { {}, { ptr } }
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK: // %bb.0: // %bb
+; CHECK-NEXT:adrp x8, :got:p
+; CHECK-NEXT:ldr x8, [x8, :got_lo12:p]
+; CHECK-NEXT:ldr x8, [x8]
+; CHECK-NEXT:mov x9, xzr
+; CHECK-NEXT:str x8, [x9]
+; CHECK-NEXT:ret
+bb:
+ %i1 = load ptr, ptr @p, align 8
+ store ptr %i1, ptr null, align 8
+ ret void
+}
___
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[llvm-branch-commits] [llvm] release/18.x: [SystemZ] Handle address clobbering in splitMove(). (#92105) (PR #92221)
tstellar wrote: @nikic (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR https://github.com/llvm/llvm-project/pull/92221 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 9acb41b - [SystemZ] Handle address clobbering in splitMove(). (#92105)
Author: Jonas Paulsson
Date: 2024-05-15T19:01:13-07:00
New Revision: 9acb41b1e4bb897cbc70301824acf1da4c46a51d
URL:
https://github.com/llvm/llvm-project/commit/9acb41b1e4bb897cbc70301824acf1da4c46a51d
DIFF:
https://github.com/llvm/llvm-project/commit/9acb41b1e4bb897cbc70301824acf1da4c46a51d.diff
LOG: [SystemZ] Handle address clobbering in splitMove(). (#92105)
When expanding an L128 (which is used to reload i128) it is
possible that the quadword destination register clobbers an
address register. This patch adds an assertion against the case
where both of the expanded parts clobber the address, and in the
case where one of the expanded parts do so puts it last.
Fixes #91437
(cherry picked from commit d6ee7e8481fbaee30f37d82778ef12e135db5e67)
Added:
llvm/test/CodeGen/SystemZ/splitMove_addressReg.mir
Modified:
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
Removed:
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index bf6547cc87ec5..2f2dc6b807921 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -70,49 +70,62 @@ void
SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
MachineBasicBlock *MBB = MI->getParent();
MachineFunction = *MBB->getParent();
- // Get two load or store instructions. Use the original instruction for one
- // of them (arbitrarily the second here) and create a clone for the other.
- MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
- MBB->insert(MI, EarlierMI);
+ // Get two load or store instructions. Use the original instruction for
+ // one of them and create a clone for the other.
+ MachineInstr *HighPartMI = MF.CloneMachineInstr(&*MI);
+ MachineInstr *LowPartMI = &*MI;
+ MBB->insert(LowPartMI, HighPartMI);
// Set up the two 64-bit registers and remember super reg and its flags.
- MachineOperand = EarlierMI->getOperand(0);
- MachineOperand = MI->getOperand(0);
+ MachineOperand = HighPartMI->getOperand(0);
+ MachineOperand = LowPartMI->getOperand(0);
Register Reg128 = LowRegOp.getReg();
unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef());
HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
- if (MI->mayStore()) {
-// Add implicit uses of the super register in case one of the subregs is
-// undefined. We could track liveness and skip storing an undefined
-// subreg, but this is hopefully rare (discovered with llvm-stress).
-// If Reg128 was killed, set kill flag on MI.
-unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
-MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
-MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl |
Reg128Killed));
- }
-
// The address in the first (high) instruction is already correct.
// Adjust the offset in the second (low) instruction.
- MachineOperand = EarlierMI->getOperand(2);
- MachineOperand = MI->getOperand(2);
+ MachineOperand = HighPartMI->getOperand(2);
+ MachineOperand = LowPartMI->getOperand(2);
LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
- // Clear the kill flags on the registers in the first instruction.
- if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
-EarlierMI->getOperand(0).setIsKill(false);
- EarlierMI->getOperand(1).setIsKill(false);
- EarlierMI->getOperand(3).setIsKill(false);
-
// Set the opcodes.
unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
assert(HighOpcode && LowOpcode && "Both offsets should be in range");
+ HighPartMI->setDesc(get(HighOpcode));
+ LowPartMI->setDesc(get(LowOpcode));
+
+ MachineInstr *FirstMI = HighPartMI;
+ if (MI->mayStore()) {
+FirstMI->getOperand(0).setIsKill(false);
+// Add implicit uses of the super register in case one of the subregs is
+// undefined. We could track liveness and skip storing an undefined
+// subreg, but this is hopefully rare (discovered with llvm-stress).
+// If Reg128 was killed, set kill flag on MI.
+unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
+MachineInstrBuilder(MF, HighPartMI).addReg(Reg128, Reg128UndefImpl);
+MachineInstrBuilder(MF, LowPartMI).addReg(Reg128, (Reg128UndefImpl |
Reg128Killed));
+ } else {
+// If HighPartMI clobbers any of the address registers, it needs to come
+// after LowPartMI.
+auto overlapsAddressReg = [&](Register Reg) -> bool {
+ return RI.regsOverlap(Reg, MI->getOperand(1).getReg()) ||
+ RI.regsOverlap(Reg, MI->getOperand(3).getReg());
+};
+if (overlapsAddressReg(HighRegOp.getReg())) {
+
[llvm-branch-commits] [llvm] release/18.x: [SystemZ] Handle address clobbering in splitMove(). (#92105) (PR #92221)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/92221 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [SystemZ] Handle address clobbering in splitMove(). (#92105) (PR #92221)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/92221
>From 9acb41b1e4bb897cbc70301824acf1da4c46a51d Mon Sep 17 00:00:00 2001
From: Jonas Paulsson
Date: Wed, 15 May 2024 08:36:26 +0200
Subject: [PATCH] [SystemZ] Handle address clobbering in splitMove(). (#92105)
When expanding an L128 (which is used to reload i128) it is
possible that the quadword destination register clobbers an
address register. This patch adds an assertion against the case
where both of the expanded parts clobber the address, and in the
case where one of the expanded parts do so puts it last.
Fixes #91437
(cherry picked from commit d6ee7e8481fbaee30f37d82778ef12e135db5e67)
---
llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp | 65 +++
.../CodeGen/SystemZ/splitMove_addressReg.mir | 26
2 files changed, 65 insertions(+), 26 deletions(-)
create mode 100644 llvm/test/CodeGen/SystemZ/splitMove_addressReg.mir
diff --git a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
index bf6547cc87ec5..2f2dc6b807921 100644
--- a/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZInstrInfo.cpp
@@ -70,49 +70,62 @@ void
SystemZInstrInfo::splitMove(MachineBasicBlock::iterator MI,
MachineBasicBlock *MBB = MI->getParent();
MachineFunction = *MBB->getParent();
- // Get two load or store instructions. Use the original instruction for one
- // of them (arbitrarily the second here) and create a clone for the other.
- MachineInstr *EarlierMI = MF.CloneMachineInstr(&*MI);
- MBB->insert(MI, EarlierMI);
+ // Get two load or store instructions. Use the original instruction for
+ // one of them and create a clone for the other.
+ MachineInstr *HighPartMI = MF.CloneMachineInstr(&*MI);
+ MachineInstr *LowPartMI = &*MI;
+ MBB->insert(LowPartMI, HighPartMI);
// Set up the two 64-bit registers and remember super reg and its flags.
- MachineOperand = EarlierMI->getOperand(0);
- MachineOperand = MI->getOperand(0);
+ MachineOperand = HighPartMI->getOperand(0);
+ MachineOperand = LowPartMI->getOperand(0);
Register Reg128 = LowRegOp.getReg();
unsigned Reg128Killed = getKillRegState(LowRegOp.isKill());
unsigned Reg128Undef = getUndefRegState(LowRegOp.isUndef());
HighRegOp.setReg(RI.getSubReg(HighRegOp.getReg(), SystemZ::subreg_h64));
LowRegOp.setReg(RI.getSubReg(LowRegOp.getReg(), SystemZ::subreg_l64));
- if (MI->mayStore()) {
-// Add implicit uses of the super register in case one of the subregs is
-// undefined. We could track liveness and skip storing an undefined
-// subreg, but this is hopefully rare (discovered with llvm-stress).
-// If Reg128 was killed, set kill flag on MI.
-unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
-MachineInstrBuilder(MF, EarlierMI).addReg(Reg128, Reg128UndefImpl);
-MachineInstrBuilder(MF, MI).addReg(Reg128, (Reg128UndefImpl |
Reg128Killed));
- }
-
// The address in the first (high) instruction is already correct.
// Adjust the offset in the second (low) instruction.
- MachineOperand = EarlierMI->getOperand(2);
- MachineOperand = MI->getOperand(2);
+ MachineOperand = HighPartMI->getOperand(2);
+ MachineOperand = LowPartMI->getOperand(2);
LowOffsetOp.setImm(LowOffsetOp.getImm() + 8);
- // Clear the kill flags on the registers in the first instruction.
- if (EarlierMI->getOperand(0).isReg() && EarlierMI->getOperand(0).isUse())
-EarlierMI->getOperand(0).setIsKill(false);
- EarlierMI->getOperand(1).setIsKill(false);
- EarlierMI->getOperand(3).setIsKill(false);
-
// Set the opcodes.
unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm());
unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm());
assert(HighOpcode && LowOpcode && "Both offsets should be in range");
+ HighPartMI->setDesc(get(HighOpcode));
+ LowPartMI->setDesc(get(LowOpcode));
+
+ MachineInstr *FirstMI = HighPartMI;
+ if (MI->mayStore()) {
+FirstMI->getOperand(0).setIsKill(false);
+// Add implicit uses of the super register in case one of the subregs is
+// undefined. We could track liveness and skip storing an undefined
+// subreg, but this is hopefully rare (discovered with llvm-stress).
+// If Reg128 was killed, set kill flag on MI.
+unsigned Reg128UndefImpl = (Reg128Undef | RegState::Implicit);
+MachineInstrBuilder(MF, HighPartMI).addReg(Reg128, Reg128UndefImpl);
+MachineInstrBuilder(MF, LowPartMI).addReg(Reg128, (Reg128UndefImpl |
Reg128Killed));
+ } else {
+// If HighPartMI clobbers any of the address registers, it needs to come
+// after LowPartMI.
+auto overlapsAddressReg = [&](Register Reg) -> bool {
+ return RI.regsOverlap(Reg, MI->getOperand(1).getReg()) ||
+ RI.regsOverlap(Reg, MI->getOperand(3).getReg());
+};
+if (overlapsAddressReg(HighRegOp.getReg())) {
+
[llvm-branch-commits] [llvm] release/18.x: [InstCombine] Drop nuw flag when CtlzOp is a sub nuw (#91776) (PR #91917)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/91917
>From e4bbaa67ac5bb4aa0c6a4699aaa164f58ab5ae61 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 13 May 2024 14:27:59 +0800
Subject: [PATCH 1/2] [InstCombine] Drop nuw flag when CtlzOp is a sub nuw
(#91776)
See the following case:
```
define i32 @src1(i32 %x) {
%dec = sub nuw i32 -2, %x
%ctlz = tail call i32 @llvm.ctlz.i32(i32 %dec, i1 false)
%sub = sub nsw i32 32, %ctlz
%shl = shl i32 1, %sub
%ugt = icmp ult i32 %x, -2
%sel = select i1 %ugt, i32 %shl, i32 1
ret i32 %sel
}
define i32 @tgt1(i32 %x) {
%dec = sub nuw i32 -2, %x
%ctlz = tail call i32 @llvm.ctlz.i32(i32 %dec, i1 false)
%sub = sub nsw i32 32, %ctlz
%and = and i32 %sub, 31
%shl = shl nuw i32 1, %and
ret i32 %shl
}
```
`nuw` in `%dec` should be dropped after the select instruction is
eliminated.
Alive2: https://alive2.llvm.org/ce/z/7S9529
Fixes https://github.com/llvm/llvm-project/issues/91691.
(cherry picked from commit b5f4210e9f51f938ae517f219f04f9ab431a2684)
---
.../InstCombine/InstCombineSelect.cpp | 14 ++--
llvm/test/Transforms/InstCombine/bit_ceil.ll | 36 +++
2 files changed, 48 insertions(+), 2 deletions(-)
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index 8cc7901cbac7f..86a39cf2ee93f 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -3201,7 +3201,8 @@ Instruction
*InstCombinerImpl::foldSelectOfBools(SelectInst ) {
// pattern.
static bool isSafeToRemoveBitCeilSelect(ICmpInst::Predicate Pred, Value *Cond0,
const APInt *Cond1, Value *CtlzOp,
-unsigned BitWidth) {
+unsigned BitWidth,
+bool ) {
// The challenge in recognizing std::bit_ceil(X) is that the operand is used
// for the CTLZ proper and select condition, each possibly with some
// operation like add and sub.
@@ -3224,6 +3225,8 @@ static bool
isSafeToRemoveBitCeilSelect(ICmpInst::Predicate Pred, Value *Cond0,
ConstantRange CR = ConstantRange::makeExactICmpRegion(
CmpInst::getInversePredicate(Pred), *Cond1);
+ ShouldDropNUW = false;
+
// Match the operation that's used to compute CtlzOp from CommonAncestor. If
// CtlzOp == CommonAncestor, return true as no operation is needed. If a
// match is found, execute the operation on CR, update CR, and return true.
@@ -3237,6 +3240,7 @@ static bool
isSafeToRemoveBitCeilSelect(ICmpInst::Predicate Pred, Value *Cond0,
return true;
}
if (match(CtlzOp, m_Sub(m_APInt(C), m_Specific(CommonAncestor {
+ ShouldDropNUW = true;
CR = ConstantRange(*C).sub(CR);
return true;
}
@@ -3306,14 +3310,20 @@ static Instruction *foldBitCeil(SelectInst ,
IRBuilderBase ) {
Pred = CmpInst::getInversePredicate(Pred);
}
+ bool ShouldDropNUW;
+
if (!match(FalseVal, m_One()) ||
!match(TrueVal,
m_OneUse(m_Shl(m_One(), m_OneUse(m_Sub(m_SpecificInt(BitWidth),
m_Value(Ctlz)) ||
!match(Ctlz, m_Intrinsic(m_Value(CtlzOp), m_Zero())) ||
- !isSafeToRemoveBitCeilSelect(Pred, Cond0, Cond1, CtlzOp, BitWidth))
+ !isSafeToRemoveBitCeilSelect(Pred, Cond0, Cond1, CtlzOp, BitWidth,
+ ShouldDropNUW))
return nullptr;
+ if (ShouldDropNUW)
+cast(CtlzOp)->setHasNoUnsignedWrap(false);
+
// Build 1 << (-CTLZ & (BitWidth-1)). The negation likely corresponds to a
// single hardware instruction as opposed to BitWidth - CTLZ, where BitWidth
// is an integer constant. Masking with BitWidth-1 comes free on some
diff --git a/llvm/test/Transforms/InstCombine/bit_ceil.ll
b/llvm/test/Transforms/InstCombine/bit_ceil.ll
index 52e70c78ba542..63a5ae012eeb6 100644
--- a/llvm/test/Transforms/InstCombine/bit_ceil.ll
+++ b/llvm/test/Transforms/InstCombine/bit_ceil.ll
@@ -284,6 +284,42 @@ define <4 x i32> @bit_ceil_v4i32(<4 x i32> %x) {
ret <4 x i32> %sel
}
+define i32 @pr91691(i32 %0) {
+; CHECK-LABEL: @pr91691(
+; CHECK-NEXT:[[TMP2:%.*]] = sub i32 -2, [[TMP0:%.*]]
+; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:[[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
+; CHECK-NEXT:[[TMP5:%.*]] = and i32 [[TMP4]], 31
+; CHECK-NEXT:[[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
+; CHECK-NEXT:ret i32 [[TMP6]]
+;
+ %2 = sub nuw i32 -2, %0
+ %3 = tail call i32 @llvm.ctlz.i32(i32 %2, i1 false)
+ %4 = sub i32 32, %3
+ %5 = shl i32 1, %4
+ %6 = icmp ult i32 %0, -2
+ %7 = select i1 %6, i32 %5, i32 1
+ ret i32 %7
+}
+
+define i32 @pr91691_keep_nsw(i32 %0) {
+; CHECK-LABEL: @pr91691_keep_nsw(
+; CHECK-NEXT:[[TMP2:%.*]] = sub nsw
[llvm-branch-commits] [llvm] release/18.x: [GlobalIsel][AArch64] fix out of range access in regbankselect (#92072) (PR #92129)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/92129
>From e6e68660ab3868d99710be8e492fa61e3bb0a34d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?=
Date: Tue, 14 May 2024 15:54:05 +0200
Subject: [PATCH] [GlobalIsel][AArch64] fix out of range access in
regbankselect (#92072)
Fixes https://github.com/llvm/llvm-project/issues/92062
(cherry picked from commit d422e90fcb68749918ddd86c94188807efce)
---
.../AArch64/GISel/AArch64RegisterBankInfo.cpp | 5 -
llvm/test/CodeGen/AArch64/pr92062.ll | 21 +++
2 files changed, 25 insertions(+), 1 deletion(-)
create mode 100644 llvm/test/CodeGen/AArch64/pr92062.ll
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
index b8e5e7bbdaba7..06cdd7e4ef481 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64RegisterBankInfo.cpp
@@ -623,8 +623,11 @@ bool AArch64RegisterBankInfo::isLoadFromFPType(const
MachineInstr ) const {
EltTy = GV->getValueType();
// Look at the first element of the struct to determine the type we are
// loading
-while (StructType *StructEltTy = dyn_cast(EltTy))
+while (StructType *StructEltTy = dyn_cast(EltTy)) {
+ if (StructEltTy->getNumElements() == 0)
+break;
EltTy = StructEltTy->getTypeAtIndex(0U);
+}
// Look at the first element of the array to determine its type
if (isa(EltTy))
EltTy = EltTy->getArrayElementType();
diff --git a/llvm/test/CodeGen/AArch64/pr92062.ll
b/llvm/test/CodeGen/AArch64/pr92062.ll
new file mode 100644
index 0..6111ee0fbe18f
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/pr92062.ll
@@ -0,0 +1,21 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 4
+; RUN: llc -mtriple=aarch64 -O0 -global-isel %s -o - 2>&1 | FileCheck %s
+
+target triple = "arm64"
+
+@p = external global { {}, { ptr } }
+
+define void @foo() {
+; CHECK-LABEL: foo:
+; CHECK: // %bb.0: // %bb
+; CHECK-NEXT:adrp x8, :got:p
+; CHECK-NEXT:ldr x8, [x8, :got_lo12:p]
+; CHECK-NEXT:ldr x8, [x8]
+; CHECK-NEXT:mov x9, xzr
+; CHECK-NEXT:str x8, [x9]
+; CHECK-NEXT:ret
+bb:
+ %i1 = load ptr, ptr @p, align 8
+ store ptr %i1, ptr null, align 8
+ ret void
+}
___
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[llvm-branch-commits] [clang] release/18.x: [clang] Don't assume location of compiler-rt for OpenBSD (#92183) (PR #92293)
tstellar wrote: @brad0 What do you think about backporting this? https://github.com/llvm/llvm-project/pull/92293 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [DAGCombiner] In mergeTruncStore, make sure we aren't storing shifted in bits. (#90939) (PR #91038)
tstellar wrote: @AtariDreams I've noticed you've filed a lot of backport requests. How are you choosing which fixes to backport? Is there a specific use case you care about? https://github.com/llvm/llvm-project/pull/91038 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] release/18.x: [RISCV] Re-separate unaligned scalar and vector memory features in the backend. (PR #92143)
tstellar wrote: Should we still try to backport this? https://github.com/llvm/llvm-project/pull/92143 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libclc] release/18.x: [libclc] Fix linking against libIRReader (PR #91553)
tstellar wrote: @illwieckz (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libclc] release/18.x: [libclc] Fix linking against libIRReader (PR #91553)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libclc] 1665723 - release/18.x: [libclc] Fix linking against libIRReader
Author: Thomas Debesse
Date: 2024-05-15T06:37:42-07:00
New Revision: 1665723044ec1db5a2ca68ea911155c01e815515
URL:
https://github.com/llvm/llvm-project/commit/1665723044ec1db5a2ca68ea911155c01e815515
DIFF:
https://github.com/llvm/llvm-project/commit/1665723044ec1db5a2ca68ea911155c01e815515.diff
LOG: release/18.x: [libclc] Fix linking against libIRReader
Fixes https://github.com/llvm/llvm-project/issues/91551
Added:
Modified:
libclc/CMakeLists.txt
Removed:
diff --git a/libclc/CMakeLists.txt b/libclc/CMakeLists.txt
index fa1d8e4adbcc4..b7f8bb18c2288 100644
--- a/libclc/CMakeLists.txt
+++ b/libclc/CMakeLists.txt
@@ -114,6 +114,7 @@ include_directories( ${LLVM_INCLUDE_DIRS} )
set(LLVM_LINK_COMPONENTS
BitReader
BitWriter
+ IRReader
Core
Support
)
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[llvm-branch-commits] [libclc] release/18.x: [libclc] Fix linking against libIRReader (PR #91553)
https://github.com/tstellar approved this pull request. https://github.com/llvm/llvm-project/pull/91553 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [libclc] release/18.x: [libclc] Fix linking against libIRReader (PR #91553)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/91553
>From 1665723044ec1db5a2ca68ea911155c01e815515 Mon Sep 17 00:00:00 2001
From: Thomas Debesse
Date: Thu, 9 May 2024 05:18:35 +0200
Subject: [PATCH] release/18.x: [libclc] Fix linking against libIRReader
Fixes https://github.com/llvm/llvm-project/issues/91551
---
libclc/CMakeLists.txt | 1 +
1 file changed, 1 insertion(+)
diff --git a/libclc/CMakeLists.txt b/libclc/CMakeLists.txt
index fa1d8e4adbcc4..b7f8bb18c2288 100644
--- a/libclc/CMakeLists.txt
+++ b/libclc/CMakeLists.txt
@@ -114,6 +114,7 @@ include_directories( ${LLVM_INCLUDE_DIRS} )
set(LLVM_LINK_COMPONENTS
BitReader
BitWriter
+ IRReader
Core
Support
)
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[llvm-branch-commits] [llvm] release/18.x: [InstCombine] Drop nuw flag when CtlzOp is a sub nuw (#91776) (PR #91917)
@@ -284,6 +284,42 @@ define <4 x i32> @bit_ceil_v4i32(<4 x i32> %x) {
ret <4 x i32> %sel
}
+define i32 @pr91691(i32 %0) {
+; CHECK-LABEL: @pr91691(
+; CHECK-NEXT:[[TMP2:%.*]] = sub i32 -2, [[TMP0:%.*]]
+; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:[[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
+; CHECK-NEXT:[[TMP5:%.*]] = and i32 [[TMP4]], 31
+; CHECK-NEXT:[[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
+; CHECK-NEXT:ret i32 [[TMP6]]
+;
+ %2 = sub nuw i32 -2, %0
+ %3 = tail call i32 @llvm.ctlz.i32(i32 %2, i1 false)
+ %4 = sub i32 32, %3
+ %5 = shl i32 1, %4
+ %6 = icmp ult i32 %0, -2
+ %7 = select i1 %6, i32 %5, i32 1
+ ret i32 %7
+}
+
+define i32 @pr91691_keep_nsw(i32 %0) {
+; CHECK-LABEL: @pr91691_keep_nsw(
+; CHECK-NEXT:[[TMP2:%.*]] = sub nsw i32 -2, [[TMP0:%.*]]
+; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:[[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
+; CHECK-NEXT:[[TMP5:%.*]] = and i32 [[TMP4]], 31
+; CHECK-NEXT:[[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
+; CHECK-NEXT:ret i32 [[TMP6]]
+;
+ %2 = sub nsw i32 -2, %0
+ %3 = tail call i32 @llvm.ctlz.i32(i32 %2, i1 false)
+ %4 = sub i32 32, %3
+ %5 = shl i32 1, %4
+ %6 = icmp ult i32 %0, -2
+ %7 = select i1 %6, i32 %5, i32 1
+ ret i32 %7
+}
+
tstellar wrote:
@dtcxzyw I've enabled maintainer edits for this PR, so you can push directly
now.
https://github.com/llvm/llvm-project/pull/91917
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[llvm-branch-commits] [llvm] release/18.x: [InstCombine] Drop nuw flag when CtlzOp is a sub nuw (#91776) (PR #91917)
@@ -284,6 +284,42 @@ define <4 x i32> @bit_ceil_v4i32(<4 x i32> %x) {
ret <4 x i32> %sel
}
+define i32 @pr91691(i32 %0) {
+; CHECK-LABEL: @pr91691(
+; CHECK-NEXT:[[TMP2:%.*]] = sub i32 -2, [[TMP0:%.*]]
+; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:[[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
+; CHECK-NEXT:[[TMP5:%.*]] = and i32 [[TMP4]], 31
+; CHECK-NEXT:[[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
+; CHECK-NEXT:ret i32 [[TMP6]]
+;
+ %2 = sub nuw i32 -2, %0
+ %3 = tail call i32 @llvm.ctlz.i32(i32 %2, i1 false)
+ %4 = sub i32 32, %3
+ %5 = shl i32 1, %4
+ %6 = icmp ult i32 %0, -2
+ %7 = select i1 %6, i32 %5, i32 1
+ ret i32 %7
+}
+
+define i32 @pr91691_keep_nsw(i32 %0) {
+; CHECK-LABEL: @pr91691_keep_nsw(
+; CHECK-NEXT:[[TMP2:%.*]] = sub nsw i32 -2, [[TMP0:%.*]]
+; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:[[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
+; CHECK-NEXT:[[TMP5:%.*]] = and i32 [[TMP4]], 31
+; CHECK-NEXT:[[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
+; CHECK-NEXT:ret i32 [[TMP6]]
+;
+ %2 = sub nsw i32 -2, %0
+ %3 = tail call i32 @llvm.ctlz.i32(i32 %2, i1 false)
+ %4 = sub i32 32, %3
+ %5 = shl i32 1, %4
+ %6 = icmp ult i32 %0, -2
+ %7 = select i1 %6, i32 %5, i32 1
+ ret i32 %7
+}
+
tstellar wrote:
@nikic No, it's not. The problem is that you need two different types of
permissions to be able to set that feature (write access to the branch and
write access to the PR). Because these both have different scopes (the branch
is in the forked repository and the PR is in the main repository) it's not
possible to use fine-grained tokens. We'll have to switch back to the classic
token to get it to work. I'm planning to do this for the next release cycle.
https://github.com/llvm/llvm-project/pull/91917
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[llvm-branch-commits] [libcxx] release/18.x: change the visibility of libc++ header to public in libcxx module (PR #91182)
tstellar wrote: @mordante Do you think we should backport this? https://github.com/llvm/llvm-project/pull/91182 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215) (PR #91419)
tstellar wrote: @AtariDreams (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91419 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215) (PR #91419)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91419 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 494847b - [InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215)
Author: Yingwei Zheng
Date: 2024-05-14T16:32:24-07:00
New Revision: 494847ba8fef9a29cfa92aac3f8aaa1102b5d44f
URL:
https://github.com/llvm/llvm-project/commit/494847ba8fef9a29cfa92aac3f8aaa1102b5d44f
DIFF:
https://github.com/llvm/llvm-project/commit/494847ba8fef9a29cfa92aac3f8aaa1102b5d44f.diff
LOG: [InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215)
See the LangRef:
> All uses of a value returned by the same ‘freeze’ instruction are
guaranteed to always observe the same value, while different ‘freeze’
instructions may yield different values.
It is incorrect to replace freezes with the simplified value.
Proof:
https://alive2.llvm.org/ce/z/3Dn9Cd
https://alive2.llvm.org/ce/z/Qyh5h6
Fixes https://github.com/llvm/llvm-project/issues/91178
(cherry picked from commit d085b42cbbefe79a41113abcd2b1e1f2a203acef)
Revert "[InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced`
(#91215)"
This reverts commit 1c2eb18d52976fef89972e89c52d2ec5ed7e4868.
[InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215)
See the LangRef:
> All uses of a value returned by the same ‘freeze’ instruction are
guaranteed to always observe the same value, while different ‘freeze’
instructions may yield different values.
It is incorrect to replace freezes with the simplified value.
Proof:
https://alive2.llvm.org/ce/z/3Dn9Cd
https://alive2.llvm.org/ce/z/Qyh5h6
Fixes https://github.com/llvm/llvm-project/issues/91178
(cherry picked from commit d085b42cbbefe79a41113abcd2b1e1f2a203acef)
Added:
Modified:
llvm/lib/Analysis/InstructionSimplify.cpp
llvm/test/Transforms/InstCombine/icmp.ll
llvm/test/Transforms/InstCombine/select.ll
llvm/test/Transforms/PGOProfile/chr.ll
Removed:
diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp
b/llvm/lib/Analysis/InstructionSimplify.cpp
index 72b6dfa181e86..8dcffe45c644b 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -4322,6 +4322,10 @@ static Value *simplifyWithOpReplaced(Value *V, Value
*Op, Value *RepOp,
if (match(I, m_Intrinsic()))
return nullptr;
+ // Don't simplify freeze.
+ if (isa(I))
+return nullptr;
+
// Replace Op with RepOp in instruction operands.
SmallVector NewOps;
bool AnyReplaced = false;
diff --git a/llvm/test/Transforms/InstCombine/icmp.ll
b/llvm/test/Transforms/InstCombine/icmp.ll
index 10ab1fe118348..9ac35745742bb 100644
--- a/llvm/test/Transforms/InstCombine/icmp.ll
+++ b/llvm/test/Transforms/InstCombine/icmp.ll
@@ -5183,3 +5183,18 @@ entry:
%cmp = icmp eq i8 %add2, %add1
ret i1 %cmp
}
+
+define i1 @icmp_freeze_sext(i16 %x, i16 %y) {
+; CHECK-LABEL: @icmp_freeze_sext(
+; CHECK-NEXT:[[CMP1:%.*]] = icmp uge i16 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:[[CMP1_FR:%.*]] = freeze i1 [[CMP1]]
+; CHECK-NEXT:[[TMP1:%.*]] = icmp eq i16 [[Y]], 0
+; CHECK-NEXT:[[CMP2:%.*]] = or i1 [[TMP1]], [[CMP1_FR]]
+; CHECK-NEXT:ret i1 [[CMP2]]
+;
+ %cmp1 = icmp uge i16 %x, %y
+ %ext = sext i1 %cmp1 to i16
+ %ext.fr = freeze i16 %ext
+ %cmp2 = icmp uge i16 %ext.fr, %y
+ ret i1 %cmp2
+}
diff --git a/llvm/test/Transforms/InstCombine/select.ll
b/llvm/test/Transforms/InstCombine/select.ll
index 888e7d28f78af..1909f9b0daf82 100644
--- a/llvm/test/Transforms/InstCombine/select.ll
+++ b/llvm/test/Transforms/InstCombine/select.ll
@@ -3708,3 +3708,35 @@ define i32 @src_select_xxory_eq0_xorxy_y(i32 %x, i32 %y)
{
%cond = select i1 %xor0, i32 %xor, i32 %y
ret i32 %cond
}
+
+define i8 @test_replace_freeze_multiuse(i1 %x, i8 %y) {
+; CHECK-LABEL: @test_replace_freeze_multiuse(
+; CHECK-NEXT:[[EXT:%.*]] = zext i1 [[X:%.*]] to i8
+; CHECK-NEXT:[[SHL:%.*]] = shl nuw i8 [[EXT]], [[Y:%.*]]
+; CHECK-NEXT:[[SHL_FR:%.*]] = freeze i8 [[SHL]]
+; CHECK-NEXT:[[SEL:%.*]] = select i1 [[X]], i8 0, i8 [[SHL_FR]]
+; CHECK-NEXT:[[ADD:%.*]] = add i8 [[SHL_FR]], [[SEL]]
+; CHECK-NEXT:ret i8 [[ADD]]
+;
+ %ext = zext i1 %x to i8
+ %shl = shl nuw i8 %ext, %y
+ %shl.fr = freeze i8 %shl
+ %sel = select i1 %x, i8 0, i8 %shl.fr
+ %add = add i8 %shl.fr, %sel
+ ret i8 %add
+}
+
+define i8 @test_replace_freeze_oneuse(i1 %x, i8 %y) {
+; CHECK-LABEL: @test_replace_freeze_oneuse(
+; CHECK-NEXT:[[EXT:%.*]] = zext i1 [[X:%.*]] to i8
+; CHECK-NEXT:[[SHL:%.*]] = shl nuw i8 [[EXT]], [[Y:%.*]]
+; CHECK-NEXT:[[SHL_FR:%.*]] = freeze i8 [[SHL]]
+; CHECK-NEXT:[[SEL:%.*]] = select i1 [[X]], i8 0, i8 [[SHL_FR]]
+; CHECK-NEXT:ret i8 [[SEL]]
+;
+ %ext = zext i1 %x to i8
+ %shl = shl nuw i8 %ext, %y
+ %shl.fr = freeze i8 %shl
+ %sel = select i1 %x, i8 0, i8 %shl.fr
+ ret i8 %sel
+}
diff --git a/llvm/test/Transforms/PGOProfile/chr.ll
b/llvm/test/Transforms/PGOProfile/chr.ll
index 0551a171091ca..38e8f8536a19c 100644
--- a/llvm/test/Transforms/PGOProfile/chr.ll
+++ b/llvm/test/Transforms/PGOProfile/chr.ll
@@ -1298,11
[llvm-branch-commits] [llvm] release/18.x: [InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215) (PR #91419)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/91419
>From 494847ba8fef9a29cfa92aac3f8aaa1102b5d44f Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Wed, 8 May 2024 10:04:09 +0800
Subject: [PATCH] [InstSimplify] Do not simplify freeze in
`simplifyWithOpReplaced` (#91215)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
See the LangRef:
> All uses of a value returned by the same ‘freeze’ instruction are
guaranteed to always observe the same value, while different ‘freeze’
instructions may yield different values.
It is incorrect to replace freezes with the simplified value.
Proof:
https://alive2.llvm.org/ce/z/3Dn9Cd
https://alive2.llvm.org/ce/z/Qyh5h6
Fixes https://github.com/llvm/llvm-project/issues/91178
(cherry picked from commit d085b42cbbefe79a41113abcd2b1e1f2a203acef)
Revert "[InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced`
(#91215)"
This reverts commit 1c2eb18d52976fef89972e89c52d2ec5ed7e4868.
[InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215)
See the LangRef:
> All uses of a value returned by the same ‘freeze’ instruction are
guaranteed to always observe the same value, while different ‘freeze’
instructions may yield different values.
It is incorrect to replace freezes with the simplified value.
Proof:
https://alive2.llvm.org/ce/z/3Dn9Cd
https://alive2.llvm.org/ce/z/Qyh5h6
Fixes https://github.com/llvm/llvm-project/issues/91178
(cherry picked from commit d085b42cbbefe79a41113abcd2b1e1f2a203acef)
---
llvm/lib/Analysis/InstructionSimplify.cpp | 4 +++
llvm/test/Transforms/InstCombine/icmp.ll | 15 ++
llvm/test/Transforms/InstCombine/select.ll | 32 ++
llvm/test/Transforms/PGOProfile/chr.ll | 7 +++--
4 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp
b/llvm/lib/Analysis/InstructionSimplify.cpp
index 72b6dfa181e86..8dcffe45c644b 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -4322,6 +4322,10 @@ static Value *simplifyWithOpReplaced(Value *V, Value
*Op, Value *RepOp,
if (match(I, m_Intrinsic()))
return nullptr;
+ // Don't simplify freeze.
+ if (isa(I))
+return nullptr;
+
// Replace Op with RepOp in instruction operands.
SmallVector NewOps;
bool AnyReplaced = false;
diff --git a/llvm/test/Transforms/InstCombine/icmp.ll
b/llvm/test/Transforms/InstCombine/icmp.ll
index 10ab1fe118348..9ac35745742bb 100644
--- a/llvm/test/Transforms/InstCombine/icmp.ll
+++ b/llvm/test/Transforms/InstCombine/icmp.ll
@@ -5183,3 +5183,18 @@ entry:
%cmp = icmp eq i8 %add2, %add1
ret i1 %cmp
}
+
+define i1 @icmp_freeze_sext(i16 %x, i16 %y) {
+; CHECK-LABEL: @icmp_freeze_sext(
+; CHECK-NEXT:[[CMP1:%.*]] = icmp uge i16 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:[[CMP1_FR:%.*]] = freeze i1 [[CMP1]]
+; CHECK-NEXT:[[TMP1:%.*]] = icmp eq i16 [[Y]], 0
+; CHECK-NEXT:[[CMP2:%.*]] = or i1 [[TMP1]], [[CMP1_FR]]
+; CHECK-NEXT:ret i1 [[CMP2]]
+;
+ %cmp1 = icmp uge i16 %x, %y
+ %ext = sext i1 %cmp1 to i16
+ %ext.fr = freeze i16 %ext
+ %cmp2 = icmp uge i16 %ext.fr, %y
+ ret i1 %cmp2
+}
diff --git a/llvm/test/Transforms/InstCombine/select.ll
b/llvm/test/Transforms/InstCombine/select.ll
index 888e7d28f78af..1909f9b0daf82 100644
--- a/llvm/test/Transforms/InstCombine/select.ll
+++ b/llvm/test/Transforms/InstCombine/select.ll
@@ -3708,3 +3708,35 @@ define i32 @src_select_xxory_eq0_xorxy_y(i32 %x, i32 %y)
{
%cond = select i1 %xor0, i32 %xor, i32 %y
ret i32 %cond
}
+
+define i8 @test_replace_freeze_multiuse(i1 %x, i8 %y) {
+; CHECK-LABEL: @test_replace_freeze_multiuse(
+; CHECK-NEXT:[[EXT:%.*]] = zext i1 [[X:%.*]] to i8
+; CHECK-NEXT:[[SHL:%.*]] = shl nuw i8 [[EXT]], [[Y:%.*]]
+; CHECK-NEXT:[[SHL_FR:%.*]] = freeze i8 [[SHL]]
+; CHECK-NEXT:[[SEL:%.*]] = select i1 [[X]], i8 0, i8 [[SHL_FR]]
+; CHECK-NEXT:[[ADD:%.*]] = add i8 [[SHL_FR]], [[SEL]]
+; CHECK-NEXT:ret i8 [[ADD]]
+;
+ %ext = zext i1 %x to i8
+ %shl = shl nuw i8 %ext, %y
+ %shl.fr = freeze i8 %shl
+ %sel = select i1 %x, i8 0, i8 %shl.fr
+ %add = add i8 %shl.fr, %sel
+ ret i8 %add
+}
+
+define i8 @test_replace_freeze_oneuse(i1 %x, i8 %y) {
+; CHECK-LABEL: @test_replace_freeze_oneuse(
+; CHECK-NEXT:[[EXT:%.*]] = zext i1 [[X:%.*]] to i8
+; CHECK-NEXT:[[SHL:%.*]] = shl nuw i8 [[EXT]], [[Y:%.*]]
+; CHECK-NEXT:[[SHL_FR:%.*]] = freeze i8 [[SHL]]
+; CHECK-NEXT:[[SEL:%.*]] = select i1 [[X]], i8 0, i8 [[SHL_FR]]
+; CHECK-NEXT:ret i8 [[SEL]]
+;
+ %ext = zext i1 %x to i8
+ %shl = shl nuw i8 %ext, %y
+ %shl.fr = freeze i8 %shl
+ %sel = select i1 %x, i8 0, i8 %shl.fr
+ ret i8 %sel
+}
diff --git a/llvm/test/Transforms/PGOProfile/chr.ll
b/llvm/test/Transforms/PGOProfile/chr.ll
index 0551a171091ca..38e8f8536a19c 100644
--- a/llvm/test/Transforms/PGOProfile/chr.ll
+++ b/llvm/test/Transforms/PGOProfile/chr.ll
@@
[llvm-branch-commits] [llvm] release/18.x: [X86][Driver] Do not add `-evex512` for `-march=native` when the target doesn't support AVX512 (#91694) (PR #91705)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91705 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] fac122a - [X86][Driver] Do not add `-evex512` for `-march=native` when the target doesn't support AVX512 (#91694)
Author: Phoebe Wang
Date: 2024-05-14T16:26:16-07:00
New Revision: fac122ac439191d5f46da6400681c54b0bf7e3db
URL:
https://github.com/llvm/llvm-project/commit/fac122ac439191d5f46da6400681c54b0bf7e3db
DIFF:
https://github.com/llvm/llvm-project/commit/fac122ac439191d5f46da6400681c54b0bf7e3db.diff
LOG: [X86][Driver] Do not add `-evex512` for `-march=native` when the target
doesn't support AVX512 (#91694)
(cherry picked from commit 87f3407856e61a73798af4e41b28bc33b5bf4ce6)
Added:
Modified:
llvm/lib/TargetParser/Host.cpp
Removed:
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index 1adef15771fa1..848b531dd8dd9 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -1774,7 +1774,8 @@ bool sys::getHostCPUFeatures(StringMap ) {
Features["rtm"]= HasLeaf7 && ((EBX >> 11) & 1);
// AVX512 is only supported if the OS supports the context save for it.
Features["avx512f"]= HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
- Features["evex512"]= Features["avx512f"];
+ if (Features["avx512f"])
+Features["evex512"] = true;
Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
Features["adx"]= HasLeaf7 && ((EBX >> 19) & 1);
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[llvm-branch-commits] [llvm] release/18.x: [X86][Driver] Do not add `-evex512` for `-march=native` when the target doesn't support AVX512 (#91694) (PR #91705)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/91705
>From fac122ac439191d5f46da6400681c54b0bf7e3db Mon Sep 17 00:00:00 2001
From: Phoebe Wang
Date: Fri, 10 May 2024 13:25:37 +0800
Subject: [PATCH] [X86][Driver] Do not add `-evex512` for `-march=native` when
the target doesn't support AVX512 (#91694)
(cherry picked from commit 87f3407856e61a73798af4e41b28bc33b5bf4ce6)
---
llvm/lib/TargetParser/Host.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp
index 1adef15771fa1..848b531dd8dd9 100644
--- a/llvm/lib/TargetParser/Host.cpp
+++ b/llvm/lib/TargetParser/Host.cpp
@@ -1774,7 +1774,8 @@ bool sys::getHostCPUFeatures(StringMap ) {
Features["rtm"]= HasLeaf7 && ((EBX >> 11) & 1);
// AVX512 is only supported if the OS supports the context save for it.
Features["avx512f"]= HasLeaf7 && ((EBX >> 16) & 1) && HasAVX512Save;
- Features["evex512"]= Features["avx512f"];
+ if (Features["avx512f"])
+Features["evex512"] = true;
Features["avx512dq"] = HasLeaf7 && ((EBX >> 17) & 1) && HasAVX512Save;
Features["rdseed"] = HasLeaf7 && ((EBX >> 18) & 1);
Features["adx"]= HasLeaf7 && ((EBX >> 19) & 1);
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[llvm-branch-commits] [llvm] release/18.x: [X86][Driver] Do not add `-evex512` for `-march=native` when the target doesn't support AVX512 (#91694) (PR #91705)
tstellar wrote: @phoebewang (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91705 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)
tstellar wrote: Hi @topperc (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91514 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215) (PR #91419)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/91419
>From 0a5378ecdc47e357a0c1b8631e583ba12ad6e3b0 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Wed, 8 May 2024 10:04:09 +0800
Subject: [PATCH] [InstSimplify] Do not simplify freeze in
`simplifyWithOpReplaced` (#91215)
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit
See the LangRef:
> All uses of a value returned by the same ‘freeze’ instruction are
guaranteed to always observe the same value, while different ‘freeze’
instructions may yield different values.
It is incorrect to replace freezes with the simplified value.
Proof:
https://alive2.llvm.org/ce/z/3Dn9Cd
https://alive2.llvm.org/ce/z/Qyh5h6
Fixes https://github.com/llvm/llvm-project/issues/91178
(cherry picked from commit d085b42cbbefe79a41113abcd2b1e1f2a203acef)
Revert "[InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced`
(#91215)"
This reverts commit 1c2eb18d52976fef89972e89c52d2ec5ed7e4868.
[InstSimplify] Do not simplify freeze in `simplifyWithOpReplaced` (#91215)
See the LangRef:
> All uses of a value returned by the same ‘freeze’ instruction are
guaranteed to always observe the same value, while different ‘freeze’
instructions may yield different values.
It is incorrect to replace freezes with the simplified value.
Proof:
https://alive2.llvm.org/ce/z/3Dn9Cd
https://alive2.llvm.org/ce/z/Qyh5h6
Fixes https://github.com/llvm/llvm-project/issues/91178
(cherry picked from commit d085b42cbbefe79a41113abcd2b1e1f2a203acef)
---
llvm/lib/Analysis/InstructionSimplify.cpp | 4 +++
llvm/test/Transforms/InstCombine/icmp.ll | 15 ++
llvm/test/Transforms/InstCombine/select.ll | 32 ++
llvm/test/Transforms/PGOProfile/chr.ll | 7 +++--
4 files changed, 55 insertions(+), 3 deletions(-)
diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp
b/llvm/lib/Analysis/InstructionSimplify.cpp
index 72b6dfa181e86..8dcffe45c644b 100644
--- a/llvm/lib/Analysis/InstructionSimplify.cpp
+++ b/llvm/lib/Analysis/InstructionSimplify.cpp
@@ -4322,6 +4322,10 @@ static Value *simplifyWithOpReplaced(Value *V, Value
*Op, Value *RepOp,
if (match(I, m_Intrinsic()))
return nullptr;
+ // Don't simplify freeze.
+ if (isa(I))
+return nullptr;
+
// Replace Op with RepOp in instruction operands.
SmallVector NewOps;
bool AnyReplaced = false;
diff --git a/llvm/test/Transforms/InstCombine/icmp.ll
b/llvm/test/Transforms/InstCombine/icmp.ll
index 10ab1fe118348..9ac35745742bb 100644
--- a/llvm/test/Transforms/InstCombine/icmp.ll
+++ b/llvm/test/Transforms/InstCombine/icmp.ll
@@ -5183,3 +5183,18 @@ entry:
%cmp = icmp eq i8 %add2, %add1
ret i1 %cmp
}
+
+define i1 @icmp_freeze_sext(i16 %x, i16 %y) {
+; CHECK-LABEL: @icmp_freeze_sext(
+; CHECK-NEXT:[[CMP1:%.*]] = icmp uge i16 [[X:%.*]], [[Y:%.*]]
+; CHECK-NEXT:[[CMP1_FR:%.*]] = freeze i1 [[CMP1]]
+; CHECK-NEXT:[[TMP1:%.*]] = icmp eq i16 [[Y]], 0
+; CHECK-NEXT:[[CMP2:%.*]] = or i1 [[TMP1]], [[CMP1_FR]]
+; CHECK-NEXT:ret i1 [[CMP2]]
+;
+ %cmp1 = icmp uge i16 %x, %y
+ %ext = sext i1 %cmp1 to i16
+ %ext.fr = freeze i16 %ext
+ %cmp2 = icmp uge i16 %ext.fr, %y
+ ret i1 %cmp2
+}
diff --git a/llvm/test/Transforms/InstCombine/select.ll
b/llvm/test/Transforms/InstCombine/select.ll
index 888e7d28f78af..1909f9b0daf82 100644
--- a/llvm/test/Transforms/InstCombine/select.ll
+++ b/llvm/test/Transforms/InstCombine/select.ll
@@ -3708,3 +3708,35 @@ define i32 @src_select_xxory_eq0_xorxy_y(i32 %x, i32 %y)
{
%cond = select i1 %xor0, i32 %xor, i32 %y
ret i32 %cond
}
+
+define i8 @test_replace_freeze_multiuse(i1 %x, i8 %y) {
+; CHECK-LABEL: @test_replace_freeze_multiuse(
+; CHECK-NEXT:[[EXT:%.*]] = zext i1 [[X:%.*]] to i8
+; CHECK-NEXT:[[SHL:%.*]] = shl nuw i8 [[EXT]], [[Y:%.*]]
+; CHECK-NEXT:[[SHL_FR:%.*]] = freeze i8 [[SHL]]
+; CHECK-NEXT:[[SEL:%.*]] = select i1 [[X]], i8 0, i8 [[SHL_FR]]
+; CHECK-NEXT:[[ADD:%.*]] = add i8 [[SHL_FR]], [[SEL]]
+; CHECK-NEXT:ret i8 [[ADD]]
+;
+ %ext = zext i1 %x to i8
+ %shl = shl nuw i8 %ext, %y
+ %shl.fr = freeze i8 %shl
+ %sel = select i1 %x, i8 0, i8 %shl.fr
+ %add = add i8 %shl.fr, %sel
+ ret i8 %add
+}
+
+define i8 @test_replace_freeze_oneuse(i1 %x, i8 %y) {
+; CHECK-LABEL: @test_replace_freeze_oneuse(
+; CHECK-NEXT:[[EXT:%.*]] = zext i1 [[X:%.*]] to i8
+; CHECK-NEXT:[[SHL:%.*]] = shl nuw i8 [[EXT]], [[Y:%.*]]
+; CHECK-NEXT:[[SHL_FR:%.*]] = freeze i8 [[SHL]]
+; CHECK-NEXT:[[SEL:%.*]] = select i1 [[X]], i8 0, i8 [[SHL_FR]]
+; CHECK-NEXT:ret i8 [[SEL]]
+;
+ %ext = zext i1 %x to i8
+ %shl = shl nuw i8 %ext, %y
+ %shl.fr = freeze i8 %shl
+ %sel = select i1 %x, i8 0, i8 %shl.fr
+ ret i8 %sel
+}
diff --git a/llvm/test/Transforms/PGOProfile/chr.ll
b/llvm/test/Transforms/PGOProfile/chr.ll
index 0551a171091ca..38e8f8536a19c 100644
--- a/llvm/test/Transforms/PGOProfile/chr.ll
+++ b/llvm/test/Transforms/PGOProfile/chr.ll
@@
[llvm-branch-commits] [llvm] release/18.x: [AArch64][SelectionDAG] Mask for SUBS with multiple users cannot be elided (#90911) (PR #91151)
tstellar wrote: @AtariDreams (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91151 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [AArch64][SelectionDAG] Mask for SUBS with multiple users cannot be elided (#90911) (PR #91151)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91151 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] 47b6dc4 - [AArch64][SelectionDAG] Mask for SUBS with multiple users cannot be elided (#90911)
Author: Weihang Fan
Date: 2024-05-14T14:13:35-07:00
New Revision: 47b6dc45e39aea5369308c602f0d6341a054aca2
URL:
https://github.com/llvm/llvm-project/commit/47b6dc45e39aea5369308c602f0d6341a054aca2
DIFF:
https://github.com/llvm/llvm-project/commit/47b6dc45e39aea5369308c602f0d6341a054aca2.diff
LOG: [AArch64][SelectionDAG] Mask for SUBS with multiple users cannot be elided
(#90911)
In DAGCombiner, the `performCONDCombine` function attempts to remove AND
instructions in front of SUBS (cmp) instructions for which the AND is
transparent. The rules for that are correct, but it fails to take into
account the case where the SUBS instruction has multiple users with
different condition codes for comparison and simply removes the AND for
all of them. This causes a miscompilation in the attached test case.
(cherry picked from commit 72eaa0ed9934bfaa2449091bbc6e45648d1396d6)
Added:
Modified:
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/test/CodeGen/AArch64/and-mask-removal.ll
Removed:
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 95d8ab95b2c09..bcfd0253e73c8 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -22122,7 +22122,8 @@ SDValue performCONDCombine(SDNode *N,
SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
unsigned CondOpcode = SubsNode->getOpcode();
- if (CondOpcode != AArch64ISD::SUBS || SubsNode->hasAnyUseOfValue(0))
+ if (CondOpcode != AArch64ISD::SUBS || SubsNode->hasAnyUseOfValue(0) ||
+ !SubsNode->hasOneUse())
return SDValue();
// There is a SUBS feeding this condition. Is it fed by a mask we can
diff --git a/llvm/test/CodeGen/AArch64/and-mask-removal.ll
b/llvm/test/CodeGen/AArch64/and-mask-removal.ll
index 17ff015970168..a31355549ba87 100644
--- a/llvm/test/CodeGen/AArch64/and-mask-removal.ll
+++ b/llvm/test/CodeGen/AArch64/and-mask-removal.ll
@@ -526,4 +526,26 @@ define i64 @pr58109b(i8 signext %0, i64 %a, i64 %b) {
ret i64 %4
}
+define i64 @test_2_selects(i8 zeroext %a) {
+; CHECK-LABEL: test_2_selects:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:add w9, w0, #24
+; CHECK-NEXT:mov w8, #131
+; CHECK-NEXT:and w9, w9, #0xff
+; CHECK-NEXT:cmp w9, #81
+; CHECK-NEXT:mov w9, #57
+; CHECK-NEXT:csel x8, x8, xzr, lo
+; CHECK-NEXT:csel x9, xzr, x9, eq
+; CHECK-NEXT:add x0, x8, x9
+; CHECK-NEXT:ret
+ %1 = add i8 %a, 24
+ %2 = zext i8 %1 to i64
+ %3 = icmp ult i8 %1, 81
+ %4 = select i1 %3, i64 131, i64 0
+ %5 = icmp eq i8 %1, 81
+ %6 = select i1 %5, i64 0, i64 57
+ %7 = add i64 %4, %6
+ ret i64 %7
+}
+
declare i8 @llvm.usub.sat.i8(i8, i8) #0
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[llvm-branch-commits] [llvm] release/18.x: [AArch64][SelectionDAG] Mask for SUBS with multiple users cannot be elided (#90911) (PR #91151)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/91151
>From 47b6dc45e39aea5369308c602f0d6341a054aca2 Mon Sep 17 00:00:00 2001
From: Weihang Fan <134108011+weihangf-ap...@users.noreply.github.com>
Date: Sun, 5 May 2024 04:01:13 -0700
Subject: [PATCH] [AArch64][SelectionDAG] Mask for SUBS with multiple users
cannot be elided (#90911)
In DAGCombiner, the `performCONDCombine` function attempts to remove AND
instructions in front of SUBS (cmp) instructions for which the AND is
transparent. The rules for that are correct, but it fails to take into
account the case where the SUBS instruction has multiple users with
different condition codes for comparison and simply removes the AND for
all of them. This causes a miscompilation in the attached test case.
(cherry picked from commit 72eaa0ed9934bfaa2449091bbc6e45648d1396d6)
---
.../Target/AArch64/AArch64ISelLowering.cpp| 3 ++-
llvm/test/CodeGen/AArch64/and-mask-removal.ll | 22 +++
2 files changed, 24 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 95d8ab95b2c09..bcfd0253e73c8 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -22122,7 +22122,8 @@ SDValue performCONDCombine(SDNode *N,
SDNode *SubsNode = N->getOperand(CmpIndex).getNode();
unsigned CondOpcode = SubsNode->getOpcode();
- if (CondOpcode != AArch64ISD::SUBS || SubsNode->hasAnyUseOfValue(0))
+ if (CondOpcode != AArch64ISD::SUBS || SubsNode->hasAnyUseOfValue(0) ||
+ !SubsNode->hasOneUse())
return SDValue();
// There is a SUBS feeding this condition. Is it fed by a mask we can
diff --git a/llvm/test/CodeGen/AArch64/and-mask-removal.ll
b/llvm/test/CodeGen/AArch64/and-mask-removal.ll
index 17ff015970168..a31355549ba87 100644
--- a/llvm/test/CodeGen/AArch64/and-mask-removal.ll
+++ b/llvm/test/CodeGen/AArch64/and-mask-removal.ll
@@ -526,4 +526,26 @@ define i64 @pr58109b(i8 signext %0, i64 %a, i64 %b) {
ret i64 %4
}
+define i64 @test_2_selects(i8 zeroext %a) {
+; CHECK-LABEL: test_2_selects:
+; CHECK: ; %bb.0:
+; CHECK-NEXT:add w9, w0, #24
+; CHECK-NEXT:mov w8, #131
+; CHECK-NEXT:and w9, w9, #0xff
+; CHECK-NEXT:cmp w9, #81
+; CHECK-NEXT:mov w9, #57
+; CHECK-NEXT:csel x8, x8, xzr, lo
+; CHECK-NEXT:csel x9, xzr, x9, eq
+; CHECK-NEXT:add x0, x8, x9
+; CHECK-NEXT:ret
+ %1 = add i8 %a, 24
+ %2 = zext i8 %1 to i64
+ %3 = icmp ult i8 %1, 81
+ %4 = select i1 %3, i64 131, i64 0
+ %5 = icmp eq i8 %1, 81
+ %6 = select i1 %5, i64 0, i64 57
+ %7 = add i64 %4, %6
+ ret i64 %7
+}
+
declare i8 @llvm.usub.sat.i8(i8, i8) #0
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[llvm-branch-commits] [clang] be23965 - [RISCV] Add canonical ISA string as Module metadata in IR. (#80760)
Author: Craig Topper
Date: 2024-05-14T12:58:46-07:00
New Revision: be239653149f45e4a23036c840ae0bcdc9818161
URL:
https://github.com/llvm/llvm-project/commit/be239653149f45e4a23036c840ae0bcdc9818161
DIFF:
https://github.com/llvm/llvm-project/commit/be239653149f45e4a23036c840ae0bcdc9818161.diff
LOG: [RISCV] Add canonical ISA string as Module metadata in IR. (#80760)
In an LTO build, we don't set the ELF attributes to indicate what
extensions were compiled with. The target CPU/Attrs in
RISCVTargetMachine do not get set for an LTO build. Each function gets a
target-cpu/feature attribute, but this isn't usable to set ELF attributs
since we wouldn't know what function to use. We can't just once since it
might have been compiler with an attribute likes target_verson.
This patch adds the ISA as Module metadata so we can retrieve it in the
backend. Individual translation units can still be compiled with
different strings so we need to collect the unique set when Modules are
merged.
The backend will need to combine the unique ISA strings to produce a
single value for the ELF attributes. This will be done in a separate
patch.
Added:
clang/test/CodeGen/RISCV/riscv-metadata-arch.c
Modified:
clang/lib/CodeGen/CodeGenModule.cpp
clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
Removed:
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 1280bcd36de94..eb13cd40eb8a2 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -67,6 +67,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ConvertUTF.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/TimeProfiler.h"
#include "llvm/Support/xxhash.h"
#include "llvm/TargetParser/Triple.h"
@@ -1059,6 +1060,19 @@ void CodeGenModule::Release() {
llvm::LLVMContext = TheModule.getContext();
getModule().addModuleFlag(llvm::Module::Error, "target-abi",
llvm::MDString::get(Ctx, ABIStr));
+
+// Add the canonical ISA string as metadata so the backend can set the ELF
+// attributes correctly. We use AppendUnique so LTO will keep all of the
+// unique ISA strings that were linked together.
+const std::vector =
+getTarget().getTargetOpts().Features;
+auto ParseResult = llvm::RISCVISAInfo::parseFeatures(
+Arch == llvm::Triple::riscv64 ? 64 : 32, Features);
+if (!errorToBool(ParseResult.takeError()))
+ getModule().addModuleFlag(
+ llvm::Module::AppendUnique, "riscv-isa",
+ llvm::MDNode::get(
+ Ctx, llvm::MDString::get(Ctx, (*ParseResult)->toString(;
}
if (CodeGenOpts.SanitizeCfiCrossDso) {
diff --git a/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
b/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
index 897edbc6450af..b11c2ca010e7c 100644
--- a/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
+++ b/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
@@ -28,190 +28,190 @@ vint8m1_t *scvc1, *scvc2;
// clang-format off
void ntl_all_sizes() { // CHECK-LABEL:
ntl_all_sizes
- uc = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
- sc = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
- us = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
- ss = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
- ui = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !5
- si = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !5
- ull = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !5
- sll = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !5
- h1 = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
half{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
- f1 = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
float{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !5
- d1 = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
double{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !5
- v4si1 = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); //
CHECK: load <4 x
[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91514 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] dff7178 - [RISCV] Use 'riscv-isa' module flag to set ELF flags and attributes. (#85155)
Author: Craig Topper
Date: 2024-05-14T12:58:46-07:00
New Revision: dff7178183567f1f2a9ad1e2eb99da9fae019e15
URL:
https://github.com/llvm/llvm-project/commit/dff7178183567f1f2a9ad1e2eb99da9fae019e15
DIFF:
https://github.com/llvm/llvm-project/commit/dff7178183567f1f2a9ad1e2eb99da9fae019e15.diff
LOG: [RISCV] Use 'riscv-isa' module flag to set ELF flags and attributes.
(#85155)
Walk all the ISA strings and set the subtarget bits for any extension we
find in any string.
This allows LTO output to have a ELF attributes from the union of all of
the files used to compile it.
Added:
llvm/test/CodeGen/RISCV/attributes-module-flag.ll
llvm/test/CodeGen/RISCV/module-elf-flags.ll
Modified:
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
Removed:
diff --git a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
index b2e9cd87373b0..87bd9b4048cd1 100644
--- a/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ b/llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -100,7 +100,7 @@ class RISCVAsmPrinter : public AsmPrinter {
bool emitDirectiveOptionArch();
private:
- void emitAttributes();
+ void emitAttributes(const MCSubtargetInfo );
void emitNTLHint(const MachineInstr *MI);
@@ -385,8 +385,32 @@ void RISCVAsmPrinter::emitStartOfAsmFile(Module ) {
if (const MDString *ModuleTargetABI =
dyn_cast_or_null(M.getModuleFlag("target-abi")))
RTS.setTargetABI(RISCVABI::getTargetABI(ModuleTargetABI->getString()));
+
+ MCSubtargetInfo SubtargetInfo = *TM.getMCSubtargetInfo();
+
+ // Use module flag to update feature bits.
+ if (auto *MD = dyn_cast_or_null(M.getModuleFlag("riscv-isa"))) {
+for (auto : MD->operands()) {
+ if (auto *ISAString = dyn_cast_or_null(ISA)) {
+auto ParseResult = llvm::RISCVISAInfo::parseArchString(
+ISAString->getString(), /*EnableExperimentalExtension=*/true,
+/*ExperimentalExtensionVersionCheck=*/true);
+if (!errorToBool(ParseResult.takeError())) {
+ auto = *ParseResult;
+ for (const auto : RISCVFeatureKV) {
+if (ISAInfo->hasExtension(Feature.Key) &&
+!SubtargetInfo.hasFeature(Feature.Value))
+ SubtargetInfo.ToggleFeature(Feature.Key);
+ }
+}
+ }
+}
+
+RTS.setFlagsFromFeatures(SubtargetInfo);
+ }
+
if (TM.getTargetTriple().isOSBinFormatELF())
-emitAttributes();
+emitAttributes(SubtargetInfo);
}
void RISCVAsmPrinter::emitEndOfAsmFile(Module ) {
@@ -398,13 +422,13 @@ void RISCVAsmPrinter::emitEndOfAsmFile(Module ) {
EmitHwasanMemaccessSymbols(M);
}
-void RISCVAsmPrinter::emitAttributes() {
+void RISCVAsmPrinter::emitAttributes(const MCSubtargetInfo ) {
RISCVTargetStreamer =
static_cast(*OutStreamer->getTargetStreamer());
// Use MCSubtargetInfo from TargetMachine. Individual functions may have
// attributes that
diff er from other functions in the module and we have no
// way to know which function is correct.
- RTS.emitTargetAttributes(*TM.getMCSubtargetInfo(), /*EmitStackAlign*/ true);
+ RTS.emitTargetAttributes(SubtargetInfo, /*EmitStackAlign*/ true);
}
void RISCVAsmPrinter::emitFunctionEntryLabel() {
diff --git a/llvm/test/CodeGen/RISCV/attributes-module-flag.ll
b/llvm/test/CodeGen/RISCV/attributes-module-flag.ll
new file mode 100644
index 0..4580539fbb29b
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/attributes-module-flag.ll
@@ -0,0 +1,17 @@
+; RUN: llc -mtriple=riscv32 %s -o - | FileCheck %s --check-prefix=RV32
+; RUN: llc -mtriple=riscv64 %s -o - | FileCheck %s --check-prefix=RV64
+
+; Test generation of ELF attribute from module metadata
+
+; RV32: .attribute 5, "rv32i2p1_m2p0_zba1p0"
+; RV64: .attribute 5, "rv64i2p1_m2p0_zba1p0"
+
+define i32 @addi(i32 %a) {
+ %1 = add i32 %a, 1
+ ret i32 %1
+}
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 6, !"riscv-isa", !1}
+!1 = !{!"rv64i2p1_m2p0", !"rv64i2p1_zba1p0"}
diff --git a/llvm/test/CodeGen/RISCV/module-elf-flags.ll
b/llvm/test/CodeGen/RISCV/module-elf-flags.ll
new file mode 100644
index 0..1b4bc9fd5466c
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/module-elf-flags.ll
@@ -0,0 +1,13 @@
+; RUN: llc -mtriple=riscv32 -filetype=obj < %s | llvm-readelf -h - | FileCheck
-check-prefixes=FLAGS %s
+
+; FLAGS: Flags: 0x11, RVC, TSO
+
+define i32 @addi(i32 %a) {
+ %1 = add i32 %a, 1
+ ret i32 %1
+}
+
+!llvm.module.flags = !{!0}
+
+!0 = !{i32 6, !"riscv-isa", !1}
+!1 = !{!"rv64i2p1_c2p0_ztso0p1"}
___
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[llvm-branch-commits] [llvm] 3512b12 - [RISCV] Store RVC and TSO ELF flags explicitly in RISCVTargetStreamer. NFCI (#83344)
Author: Craig Topper
Date: 2024-05-14T12:58:46-07:00
New Revision: 3512b12a79818b8089fcfa223586981a15ffb6b4
URL:
https://github.com/llvm/llvm-project/commit/3512b12a79818b8089fcfa223586981a15ffb6b4
DIFF:
https://github.com/llvm/llvm-project/commit/3512b12a79818b8089fcfa223586981a15ffb6b4.diff
LOG: [RISCV] Store RVC and TSO ELF flags explicitly in RISCVTargetStreamer.
NFCI (#83344)
Instead of caching STI in the RISCVELFTargetStreamer, store the two
flags we need from it.
My goal is to allow RISCVAsmPrinter to override these flags using IR
module metadata for LTO. So they need to be separated from the STI used
to construct the TargetStreamer.
This patch should be NFC as long as no one is changing the contents of
the STI that was used to construct the TargetStreamer between the
constructor and the use of the flags.
Added:
Modified:
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
Removed:
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
index 961b8f0afe225..cdf7c048a4bf1 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp
@@ -31,12 +31,13 @@ using namespace llvm;
// This part is for ELF object output.
RISCVTargetELFStreamer::RISCVTargetELFStreamer(MCStreamer ,
const MCSubtargetInfo )
-: RISCVTargetStreamer(S), CurrentVendor("riscv"), STI(STI) {
+: RISCVTargetStreamer(S), CurrentVendor("riscv") {
MCAssembler = getStreamer().getAssembler();
const FeatureBitset = STI.getFeatureBits();
auto = static_cast(MCA.getBackend());
setTargetABI(RISCVABI::computeTargetABI(STI.getTargetTriple(), Features,
MAB.getTargetOptions().getABIName()));
+ setFlagsFromFeatures(STI);
// `j label` in `.option norelax; j label; .option relax; ...; label:` needs
a
// relocation to ensure the jump target is correct after linking. This is due
// to a limitation that shouldForceRelocation has to make the decision
upfront
@@ -87,14 +88,13 @@ void RISCVTargetELFStreamer::finishAttributeSection() {
void RISCVTargetELFStreamer::finish() {
RISCVTargetStreamer::finish();
MCAssembler = getStreamer().getAssembler();
- const FeatureBitset = STI.getFeatureBits();
RISCVABI::ABI ABI = getTargetABI();
unsigned EFlags = MCA.getELFHeaderEFlags();
- if (Features[RISCV::FeatureStdExtC])
+ if (hasRVC())
EFlags |= ELF::EF_RISCV_RVC;
- if (Features[RISCV::FeatureStdExtZtso])
+ if (hasTSO())
EFlags |= ELF::EF_RISCV_TSO;
switch (ABI) {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
index a6f54bf67b5d2..e8f29cd8449ba 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h
@@ -46,7 +46,6 @@ class RISCVTargetELFStreamer : public RISCVTargetStreamer {
StringRef CurrentVendor;
MCSection *AttributeSection = nullptr;
- const MCSubtargetInfo
void emitAttribute(unsigned Attribute, unsigned Value) override;
void emitTextAttribute(unsigned Attribute, StringRef String) override;
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
index ac4861bf113eb..eee78a8c161f0 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
@@ -48,6 +48,11 @@ void RISCVTargetStreamer::setTargetABI(RISCVABI::ABI ABI) {
TargetABI = ABI;
}
+void RISCVTargetStreamer::setFlagsFromFeatures(const MCSubtargetInfo ) {
+ HasRVC = STI.hasFeature(RISCV::FeatureStdExtC);
+ HasTSO = STI.hasFeature(RISCV::FeatureStdExtZtso);
+}
+
void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo ,
bool EmitStackAlign) {
if (EmitStackAlign) {
diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
index 070e72fb157ae..cb8bc21cb6355 100644
--- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
+++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
@@ -33,6 +33,8 @@ struct RISCVOptionArchArg {
class RISCVTargetStreamer : public MCTargetStreamer {
RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
+ bool HasRVC = false;
+ bool HasTSO = false;
public:
RISCVTargetStreamer(MCStreamer );
@@ -58,6 +60,9 @@ class RISCVTargetStreamer : public MCTargetStreamer {
void emitTargetAttributes(const MCSubtargetInfo ,
[llvm-branch-commits] [clang] [llvm] Backport "riscv-isa" module metadata to 18.x (PR #91514)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/91514
>From be239653149f45e4a23036c840ae0bcdc9818161 Mon Sep 17 00:00:00 2001
From: Craig Topper
Date: Tue, 13 Feb 2024 16:17:50 -0800
Subject: [PATCH 1/3] [RISCV] Add canonical ISA string as Module metadata in
IR. (#80760)
In an LTO build, we don't set the ELF attributes to indicate what
extensions were compiled with. The target CPU/Attrs in
RISCVTargetMachine do not get set for an LTO build. Each function gets a
target-cpu/feature attribute, but this isn't usable to set ELF attributs
since we wouldn't know what function to use. We can't just once since it
might have been compiler with an attribute likes target_verson.
This patch adds the ISA as Module metadata so we can retrieve it in the
backend. Individual translation units can still be compiled with
different strings so we need to collect the unique set when Modules are
merged.
The backend will need to combine the unique ISA strings to produce a
single value for the ELF attributes. This will be done in a separate
patch.
---
clang/lib/CodeGen/CodeGenModule.cpp | 14 +
.../RISCV/ntlh-intrinsics/riscv32-zihintntl.c | 350 +-
.../test/CodeGen/RISCV/riscv-metadata-arch.c | 20 +
3 files changed, 209 insertions(+), 175 deletions(-)
create mode 100644 clang/test/CodeGen/RISCV/riscv-metadata-arch.c
diff --git a/clang/lib/CodeGen/CodeGenModule.cpp
b/clang/lib/CodeGen/CodeGenModule.cpp
index 1280bcd36de94..eb13cd40eb8a2 100644
--- a/clang/lib/CodeGen/CodeGenModule.cpp
+++ b/clang/lib/CodeGen/CodeGenModule.cpp
@@ -67,6 +67,7 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/ConvertUTF.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/RISCVISAInfo.h"
#include "llvm/Support/TimeProfiler.h"
#include "llvm/Support/xxhash.h"
#include "llvm/TargetParser/Triple.h"
@@ -1059,6 +1060,19 @@ void CodeGenModule::Release() {
llvm::LLVMContext = TheModule.getContext();
getModule().addModuleFlag(llvm::Module::Error, "target-abi",
llvm::MDString::get(Ctx, ABIStr));
+
+// Add the canonical ISA string as metadata so the backend can set the ELF
+// attributes correctly. We use AppendUnique so LTO will keep all of the
+// unique ISA strings that were linked together.
+const std::vector =
+getTarget().getTargetOpts().Features;
+auto ParseResult = llvm::RISCVISAInfo::parseFeatures(
+Arch == llvm::Triple::riscv64 ? 64 : 32, Features);
+if (!errorToBool(ParseResult.takeError()))
+ getModule().addModuleFlag(
+ llvm::Module::AppendUnique, "riscv-isa",
+ llvm::MDNode::get(
+ Ctx, llvm::MDString::get(Ctx, (*ParseResult)->toString(;
}
if (CodeGenOpts.SanitizeCfiCrossDso) {
diff --git a/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
b/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
index 897edbc6450af..b11c2ca010e7c 100644
--- a/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
+++ b/clang/test/CodeGen/RISCV/ntlh-intrinsics/riscv32-zihintntl.c
@@ -28,190 +28,190 @@ vint8m1_t *scvc1, *scvc2;
// clang-format off
void ntl_all_sizes() { // CHECK-LABEL:
ntl_all_sizes
- uc = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
- sc = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i8{{.*}}align 1, !nontemporal !4, !riscv-nontemporal-domain !5
- us = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
- ss = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i16{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
- ui = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !5
- si = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i32{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !5
- ull = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !5
- sll = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
i64{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !5
- h1 = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
half{{.*}}align 2, !nontemporal !4, !riscv-nontemporal-domain !5
- f1 = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
float{{.*}}align 4, !nontemporal !4, !riscv-nontemporal-domain !5
- d1 = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); // CHECK: load
double{{.*}}align 8, !nontemporal !4, !riscv-nontemporal-domain !5
- v4si1 = __riscv_ntl_load(, __RISCV_NTLH_INNERMOST_PRIVATE); //
CHECK: load <4 x i32>{{.*}}align 16, !nontemporal !4,
[llvm-branch-commits] [llvm] [workflows] Rework pre-commit CI for the release branch (PR #91550)
tstellar wrote: This PR is for testing purposes only, the main PR is here: #92058 https://github.com/llvm/llvm-project/pull/91550 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [llvm] release/18.x: [InstCombine] Drop nuw flag when CtlzOp is a sub nuw (#91776) (PR #91917)
@@ -284,6 +284,42 @@ define <4 x i32> @bit_ceil_v4i32(<4 x i32> %x) {
ret <4 x i32> %sel
}
+define i32 @pr91691(i32 %0) {
+; CHECK-LABEL: @pr91691(
+; CHECK-NEXT:[[TMP2:%.*]] = sub i32 -2, [[TMP0:%.*]]
+; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:[[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
+; CHECK-NEXT:[[TMP5:%.*]] = and i32 [[TMP4]], 31
+; CHECK-NEXT:[[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
+; CHECK-NEXT:ret i32 [[TMP6]]
+;
+ %2 = sub nuw i32 -2, %0
+ %3 = tail call i32 @llvm.ctlz.i32(i32 %2, i1 false)
+ %4 = sub i32 32, %3
+ %5 = shl i32 1, %4
+ %6 = icmp ult i32 %0, -2
+ %7 = select i1 %6, i32 %5, i32 1
+ ret i32 %7
+}
+
+define i32 @pr91691_keep_nsw(i32 %0) {
+; CHECK-LABEL: @pr91691_keep_nsw(
+; CHECK-NEXT:[[TMP2:%.*]] = sub nsw i32 -2, [[TMP0:%.*]]
+; CHECK-NEXT:[[TMP3:%.*]] = tail call range(i32 0, 33) i32
@llvm.ctlz.i32(i32 [[TMP2]], i1 false)
+; CHECK-NEXT:[[TMP4:%.*]] = sub nsw i32 0, [[TMP3]]
+; CHECK-NEXT:[[TMP5:%.*]] = and i32 [[TMP4]], 31
+; CHECK-NEXT:[[TMP6:%.*]] = shl nuw i32 1, [[TMP5]]
+; CHECK-NEXT:ret i32 [[TMP6]]
+;
+ %2 = sub nsw i32 -2, %0
+ %3 = tail call i32 @llvm.ctlz.i32(i32 %2, i1 false)
+ %4 = sub i32 32, %3
+ %5 = shl i32 1, %4
+ %6 = icmp ult i32 %0, -2
+ %7 = select i1 %6, i32 %5, i32 1
+ ret i32 %7
+}
+
tstellar wrote:
It doesn't work, because we use fine-grained tokens, and it requires a
'classic' token to work.
https://github.com/llvm/llvm-project/pull/91917
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[llvm-branch-commits] [lld] [llvm] release/18.x: [RISCV][lld] Set the type of TLSDESC relocation's referenced local symbol to STT_NOTYPE (PR #91678)
tstellar wrote: @ilovepi (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91678 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] [llvm] release/18.x: [RISCV][lld] Set the type of TLSDESC relocation's referenced local symbol to STT_NOTYPE (PR #91678)
https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/91678 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
[llvm-branch-commits] [lld] 6cfa40e - [RISCV][lld] Set the type of TLSDESC relocation's referenced local symbol to STT_NOTYPE
Author: Paul Kirth
Date: 2024-05-13T18:08:07-07:00
New Revision: 6cfa40e450cfe7980a0c4aa0e17a8367b89f8d39
URL:
https://github.com/llvm/llvm-project/commit/6cfa40e450cfe7980a0c4aa0e17a8367b89f8d39
DIFF:
https://github.com/llvm/llvm-project/commit/6cfa40e450cfe7980a0c4aa0e17a8367b89f8d39.diff
LOG: [RISCV][lld] Set the type of TLSDESC relocation's referenced local symbol
to STT_NOTYPE
When adding fixups for RISCV_TLSDESC_ADD_LO and RISCV_TLSDESC_LOAD_LO,
the local label added for RISCV TLSDESC relocations have STT_TLS set,
which is incorrect. Instead, these labels should have `STT_NOTYPE`.
This patch stops adding such fixups and avoid setting the STT_TLS on
these symbols. Failing to do so can cause LLD to emit an error `has an
STT_TLS symbol but doesn't have an SHF_TLS section`. We additionally,
adjust how LLD services these relocations to avoid errors with
incompatible relocation and symbol types.
Reviewers: topperc, MaskRay
Reviewed By: MaskRay
Pull Request: https://github.com/llvm/llvm-project/pull/85817
(cherry picked from commit dfe4ca9b7f4a422500d78280dc5eefd1979939e6)
Added:
Modified:
lld/ELF/Relocations.cpp
lld/test/ELF/riscv-tlsdesc-relax.s
lld/test/ELF/riscv-tlsdesc.s
llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp
Removed:
diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp
index 619fbaf5dc545..92a1b9baaca3d 100644
--- a/lld/ELF/Relocations.cpp
+++ b/lld/ELF/Relocations.cpp
@@ -1480,7 +1480,10 @@ template void
RelocationScanner::scanOne(RelTy *) {
// Process TLS relocations, including TLS optimizations. Note that
// R_TPREL and R_TPREL_NEG relocations are resolved in processAux.
- if (sym.isTls()) {
+ //
+ // Some RISCV TLSDESC relocations reference a local NOTYPE symbol,
+ // but we need to process them in handleTlsRelocation.
+ if (sym.isTls() || oneof(expr)) {
if (unsigned processed =
handleTlsRelocation(type, sym, *sec, offset, addend, expr)) {
i += processed - 1;
diff --git a/lld/test/ELF/riscv-tlsdesc-relax.s
b/lld/test/ELF/riscv-tlsdesc-relax.s
index fb24317e6535c..5718d4175be11 100644
--- a/lld/test/ELF/riscv-tlsdesc-relax.s
+++ b/lld/test/ELF/riscv-tlsdesc-relax.s
@@ -33,12 +33,14 @@
# GD64-NEXT: c.add a0, tp
# GD64-NEXT: jal {{.*}}
## &.got[c]-. = 0x20c0+8 - 0x1020 = 0x10a8
+# GD64-LABEL: <.Ltlsdesc_hi1>:
# GD64-NEXT: 1020: auipc a4, 0x1
# GD64-NEXT: ld a5, 0xa8(a4)
# GD64-NEXT: addia0, a4, 0xa8
# GD64-NEXT: jalrt0, 0x0(a5)
# GD64-NEXT: c.add a0, tp
## &.got[c]-. = 0x20c0+8 - 0x1032 = 0x1096
+# GD64-LABEL: <.Ltlsdesc_hi2>:
# GD64-NEXT: 1032: auipc a6, 0x1
# GD64-NEXT: ld a7, 0x96(a6)
# GD64-NEXT: addia0, a6, 0x96
@@ -64,6 +66,7 @@
# LE64-NEXT: jal {{.*}}
# LE64-NEXT: R_RISCV_JAL foo
# LE64-NEXT: R_RISCV_RELAX *ABS*
+# LE64-LABEL: <.Ltlsdesc_hi1>:
# LE64-NEXT: addia0, zero, 0x7ff
# LE64-NEXT: R_RISCV_TLSDESC_HI20 b
# LE64-NEXT: R_RISCV_RELAX *ABS*
@@ -71,6 +74,7 @@
# LE64-NEXT: R_RISCV_TLSDESC_ADD_LO12 .Ltlsdesc_hi1
# LE64-NEXT: R_RISCV_TLSDESC_CALL .Ltlsdesc_hi1
# LE64-NEXT: c.add a0, tp
+# LE64-LABEL: <.Ltlsdesc_hi2>:
# LE64-NEXT: addizero, zero, 0x0
# LE64-NEXT: R_RISCV_TLSDESC_HI20 b
# LE64-NEXT: addizero, zero, 0x0
@@ -93,9 +97,11 @@
# LE64A-NEXT: addia0, a0, -0x479
# LE64A-NEXT: c.add a0, tp
# LE64A-NEXT: jal {{.*}}
+# LE64A-LABEL: <.Ltlsdesc_hi1>:
# LE64A-NEXT: lui a0, 0x2
# LE64A-NEXT: addia0, a0, -0x479
# LE64A-NEXT: c.add a0, tp
+# LE64A-LABEL: <.Ltlsdesc_hi2>:
# LE64A-NEXT: addizero, zero, 0x0
# LE64A-NEXT: addizero, zero, 0x0
# LE64A-NEXT: lui a0, 0x2
@@ -115,10 +121,12 @@
# IE64-NEXT: c.add a0, tp
# IE64-NEXT: jal {{.*}}
## &.got[c]-. = 0x120e0+8 - 0x11018 = 0x10d0
+# IE64-LABEL: <.Ltlsdesc_hi1>:
# IE64-NEXT: 11018: auipc a0, 0x1
# IE64-NEXT: ld a0, 0xd0(a0)
# IE64-NEXT: c.add a0, tp
## &.got[c]-. = 0x120e0+8 - 0x1102a = 0x10be
+# IE64-LABEL: <.Ltlsdesc_hi2>:
# IE64-NEXT: addizero, zero, 0x0
# IE64-NEXT: addizero, zero, 0x0
# IE64-NEXT: 1102a: auipc a0, 0x1
diff --git a/lld/test/ELF/riscv-tlsdesc.s b/lld/test/ELF/riscv-tlsdesc.s
index c583e15cf30ce..935ecbddfbfff 100644
--- a/lld/test/ELF/riscv-tlsdesc.s
+++ b/lld/test/ELF/riscv-tlsdesc.s
@@ -29,11 +29,13 @@
# RUN: ld.lld -e 0 -z now a.32.o c.32.so -o a.32.ie
# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -h -d a.32.ie | FileCheck
%s --check-prefix=IE32
-# RUN: llvm-mc -triple=riscv64 -filetype=obj d.s -o d.64.o
-# RUN: not ld.lld -shared
[llvm-branch-commits] [lld] [llvm] release/18.x: [RISCV][lld] Set the type of TLSDESC relocation's referenced local symbol to STT_NOTYPE (PR #91678)
https://github.com/tstellar updated
https://github.com/llvm/llvm-project/pull/91678
>From 6cfa40e450cfe7980a0c4aa0e17a8367b89f8d39 Mon Sep 17 00:00:00 2001
From: Paul Kirth
Date: Fri, 22 Mar 2024 12:27:41 -0700
Subject: [PATCH] [RISCV][lld] Set the type of TLSDESC relocation's referenced
local symbol to STT_NOTYPE
When adding fixups for RISCV_TLSDESC_ADD_LO and RISCV_TLSDESC_LOAD_LO,
the local label added for RISCV TLSDESC relocations have STT_TLS set,
which is incorrect. Instead, these labels should have `STT_NOTYPE`.
This patch stops adding such fixups and avoid setting the STT_TLS on
these symbols. Failing to do so can cause LLD to emit an error `has an
STT_TLS symbol but doesn't have an SHF_TLS section`. We additionally,
adjust how LLD services these relocations to avoid errors with
incompatible relocation and symbol types.
Reviewers: topperc, MaskRay
Reviewed By: MaskRay
Pull Request: https://github.com/llvm/llvm-project/pull/85817
(cherry picked from commit dfe4ca9b7f4a422500d78280dc5eefd1979939e6)
---
lld/ELF/Relocations.cpp | 5 +++-
lld/test/ELF/riscv-tlsdesc-relax.s| 8 ++
lld/test/ELF/riscv-tlsdesc.s | 27 +++
.../Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp | 2 --
4 files changed, 28 insertions(+), 14 deletions(-)
diff --git a/lld/ELF/Relocations.cpp b/lld/ELF/Relocations.cpp
index 619fbaf5dc545..92a1b9baaca3d 100644
--- a/lld/ELF/Relocations.cpp
+++ b/lld/ELF/Relocations.cpp
@@ -1480,7 +1480,10 @@ template void
RelocationScanner::scanOne(RelTy *) {
// Process TLS relocations, including TLS optimizations. Note that
// R_TPREL and R_TPREL_NEG relocations are resolved in processAux.
- if (sym.isTls()) {
+ //
+ // Some RISCV TLSDESC relocations reference a local NOTYPE symbol,
+ // but we need to process them in handleTlsRelocation.
+ if (sym.isTls() || oneof(expr)) {
if (unsigned processed =
handleTlsRelocation(type, sym, *sec, offset, addend, expr)) {
i += processed - 1;
diff --git a/lld/test/ELF/riscv-tlsdesc-relax.s
b/lld/test/ELF/riscv-tlsdesc-relax.s
index fb24317e6535c..5718d4175be11 100644
--- a/lld/test/ELF/riscv-tlsdesc-relax.s
+++ b/lld/test/ELF/riscv-tlsdesc-relax.s
@@ -33,12 +33,14 @@
# GD64-NEXT: c.add a0, tp
# GD64-NEXT: jal {{.*}}
## &.got[c]-. = 0x20c0+8 - 0x1020 = 0x10a8
+# GD64-LABEL: <.Ltlsdesc_hi1>:
# GD64-NEXT: 1020: auipc a4, 0x1
# GD64-NEXT: ld a5, 0xa8(a4)
# GD64-NEXT: addia0, a4, 0xa8
# GD64-NEXT: jalrt0, 0x0(a5)
# GD64-NEXT: c.add a0, tp
## &.got[c]-. = 0x20c0+8 - 0x1032 = 0x1096
+# GD64-LABEL: <.Ltlsdesc_hi2>:
# GD64-NEXT: 1032: auipc a6, 0x1
# GD64-NEXT: ld a7, 0x96(a6)
# GD64-NEXT: addia0, a6, 0x96
@@ -64,6 +66,7 @@
# LE64-NEXT: jal {{.*}}
# LE64-NEXT: R_RISCV_JAL foo
# LE64-NEXT: R_RISCV_RELAX *ABS*
+# LE64-LABEL: <.Ltlsdesc_hi1>:
# LE64-NEXT: addia0, zero, 0x7ff
# LE64-NEXT: R_RISCV_TLSDESC_HI20 b
# LE64-NEXT: R_RISCV_RELAX *ABS*
@@ -71,6 +74,7 @@
# LE64-NEXT: R_RISCV_TLSDESC_ADD_LO12 .Ltlsdesc_hi1
# LE64-NEXT: R_RISCV_TLSDESC_CALL .Ltlsdesc_hi1
# LE64-NEXT: c.add a0, tp
+# LE64-LABEL: <.Ltlsdesc_hi2>:
# LE64-NEXT: addizero, zero, 0x0
# LE64-NEXT: R_RISCV_TLSDESC_HI20 b
# LE64-NEXT: addizero, zero, 0x0
@@ -93,9 +97,11 @@
# LE64A-NEXT: addia0, a0, -0x479
# LE64A-NEXT: c.add a0, tp
# LE64A-NEXT: jal {{.*}}
+# LE64A-LABEL: <.Ltlsdesc_hi1>:
# LE64A-NEXT: lui a0, 0x2
# LE64A-NEXT: addia0, a0, -0x479
# LE64A-NEXT: c.add a0, tp
+# LE64A-LABEL: <.Ltlsdesc_hi2>:
# LE64A-NEXT: addizero, zero, 0x0
# LE64A-NEXT: addizero, zero, 0x0
# LE64A-NEXT: lui a0, 0x2
@@ -115,10 +121,12 @@
# IE64-NEXT: c.add a0, tp
# IE64-NEXT: jal {{.*}}
## &.got[c]-. = 0x120e0+8 - 0x11018 = 0x10d0
+# IE64-LABEL: <.Ltlsdesc_hi1>:
# IE64-NEXT: 11018: auipc a0, 0x1
# IE64-NEXT: ld a0, 0xd0(a0)
# IE64-NEXT: c.add a0, tp
## &.got[c]-. = 0x120e0+8 - 0x1102a = 0x10be
+# IE64-LABEL: <.Ltlsdesc_hi2>:
# IE64-NEXT: addizero, zero, 0x0
# IE64-NEXT: addizero, zero, 0x0
# IE64-NEXT: 1102a: auipc a0, 0x1
diff --git a/lld/test/ELF/riscv-tlsdesc.s b/lld/test/ELF/riscv-tlsdesc.s
index c583e15cf30ce..935ecbddfbfff 100644
--- a/lld/test/ELF/riscv-tlsdesc.s
+++ b/lld/test/ELF/riscv-tlsdesc.s
@@ -29,11 +29,13 @@
# RUN: ld.lld -e 0 -z now a.32.o c.32.so -o a.32.ie
# RUN: llvm-objdump --no-show-raw-insn -M no-aliases -h -d a.32.ie | FileCheck
%s --check-prefix=IE32
-# RUN: llvm-mc -triple=riscv64 -filetype=obj d.s -o d.64.o
-# RUN: not ld.lld -shared -soname=d.64.so -o d.64.so d.64.o 2>&1 | FileCheck
%s
[llvm-branch-commits] [llvm] release/18.x: [PPCMergeStringPool] Avoid replacing constant with instruction (#88846) (PR #91557)
tstellar wrote: @nikic (or anyone else). If you would like to add a note about this fix in the release notes (completely optional). Please reply to this comment with a one or two sentence description of the fix. When you are done, please add the release:note label to this PR. https://github.com/llvm/llvm-project/pull/91557 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits
