Re: [PATCH] target/riscv: zvbb implies zvkb

[Jerry ZJ]

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Re: [PATCH] target/riscv: zvbb implies zvkb

[Jerry Zhang Jian]

Sorry, I had the bad mail client setting. Please ignore the previous email,
and I will resubmit the patch.

--
Jerry

Jerry ZJ  於 2024年5月28日 週二 下午8:12寫道：

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Re: [PATCH] target/riscv: zvbb implies zvkb

[Alistair Francis]

On Thu, May 16, 2024 at 10:35 PM Jerry Zhang Jian
 wrote:
>
> - According to RISC-V crypto spec, Zvkb extension is a proper subset of the 
> Zvbb extension.
>
> - Reference: 
> https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10
>
> Signed-off-by: Jerry Zhang Jian 

Do you mind rebasing on
https://github.com/alistair23/qemu/tree/riscv-to-apply.next?

Alistair

> ---
>  target/riscv/tcg/tcg-cpu.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 40054a391a..f1a1306ab2 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -658,6 +658,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, 
> Error **errp)
>  cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
>  }
>
> +if (cpu->cfg.ext_zvbb) {
> +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
> +}
> +
>  /*
>   * In principle Zve*x would also suffice here, were they supported
>   * in qemu
> --
> 2.42.0
>
>

Re: [PATCH] target/riscv: zvbb implies zvkb

[Alistair Francis]

On Thu, May 16, 2024 at 10:35 PM Jerry Zhang Jian
 wrote:
>
> - According to RISC-V crypto spec, Zvkb extension is a proper subset of the 
> Zvbb extension.
>
> - Reference: 
> https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10
>
> Signed-off-by: Jerry Zhang Jian 

Reviewed-by: Alistair Francis 

Alistair

> ---
>  target/riscv/tcg/tcg-cpu.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 40054a391a..f1a1306ab2 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -658,6 +658,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, 
> Error **errp)
>  cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
>  }
>
> +if (cpu->cfg.ext_zvbb) {
> +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
> +}
> +
>  /*
>   * In principle Zve*x would also suffice here, were they supported
>   * in qemu
> --
> 2.42.0
>
>

Re: [PATCH] target/riscv: zvbb implies zvkb

[Frank Chang]

Reviewed-by: Frank Chang 

On Thu, May 16, 2024 at 8:34 PM Jerry Zhang Jian 
wrote:

> - According to RISC-V crypto spec, Zvkb extension is a proper subset of
> the Zvbb extension.
>
> - Reference:
> https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10
>
> Signed-off-by: Jerry Zhang Jian 
> ---
>  target/riscv/tcg/tcg-cpu.c | 4 
>  1 file changed, 4 insertions(+)
>
> diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
> index 40054a391a..f1a1306ab2 100644
> --- a/target/riscv/tcg/tcg-cpu.c
> +++ b/target/riscv/tcg/tcg-cpu.c
> @@ -658,6 +658,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu,
> Error **errp)
>  cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
>  }
>
> +if (cpu->cfg.ext_zvbb) {
> +cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
> +}
> +
>  /*
>   * In principle Zve*x would also suffice here, were they supported
>   * in qemu
> --
> 2.42.0
>
>

[PATCH] target/riscv: zvbb implies zvkb

[Jerry Zhang Jian]

- According to RISC-V crypto spec, Zvkb extension is a proper subset of the 
Zvbb extension.

- Reference: 
https://github.com/riscv/riscv-crypto/blob/1769c2609bf4535632e0c0fd715778f212bb272e/doc/vector/riscv-crypto-vector-zvkb.adoc?plain=1#L10

Signed-off-by: Jerry Zhang Jian 
---
 target/riscv/tcg/tcg-cpu.c | 4 
 1 file changed, 4 insertions(+)

diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c
index 40054a391a..f1a1306ab2 100644
--- a/target/riscv/tcg/tcg-cpu.c
+++ b/target/riscv/tcg/tcg-cpu.c
@@ -658,6 +658,10 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, 
Error **errp)
 cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvbc), true);
 }
 
+if (cpu->cfg.ext_zvbb) {
+cpu_cfg_ext_auto_update(cpu, CPU_CFG_OFFSET(ext_zvkb), true);
+}
+
 /*
  * In principle Zve*x would also suffice here, were they supported
  * in qemu
-- 
2.42.0