Re: [XEN PATCH v1 3/7] x86/MCE: guard access to Intel/AMD-specific MCA MSRs

[Jan Beulich]

On 23.04.2024 10:52, Sergiy Kibrik wrote:
> --- a/xen/arch/x86/cpu/mcheck/vmce.c
> +++ b/xen/arch/x86/cpu/mcheck/vmce.c
> @@ -141,12 +141,14 @@ static int bank_mce_rdmsr(const struct vcpu *v, 
> uint32_t msr, uint64_t *val)
>  case X86_VENDOR_CENTAUR:
>  case X86_VENDOR_SHANGHAI:
>  case X86_VENDOR_INTEL:
> -ret = vmce_intel_rdmsr(v, msr, val);
> +ret = IS_ENABLED(CONFIG_INTEL) ?
> +  vmce_intel_rdmsr(v, msr, val) : -ENODEV;
>  break;
>  
>  case X86_VENDOR_AMD:
>  case X86_VENDOR_HYGON:
> -ret = vmce_amd_rdmsr(v, msr, val);
> +ret = IS_ENABLED(CONFIG_AMD) ?
> +  vmce_amd_rdmsr(v, msr, val) : -ENODEV;
>  break;

Why -ENODEV when ...

>  default:

... below here 0 is put into "ret"? And why not have the default case take
care of unsupported/unrecognized vendors uniformly?

Jan

Re: [XEN PATCH v1 3/7] x86/MCE: guard access to Intel/AMD-specific MCA MSRs

[Stefano Stabellini]

On Tue, 23 Apr 2024, Sergiy Kibrik wrote:
> Add build-time checks for newly introduced INTEL/AMD config options when
> calling vmce_{intel/amd}_{rdmsr/wrmsr}() routines.
> This way a platform-specific code can be omitted in vmce code, if this
> platform is disabled in config.
> 
> Signed-off-by: Sergiy Kibrik 

Reviewed-by: Stefano Stabellini 

[XEN PATCH v1 3/7] x86/MCE: guard access to Intel/AMD-specific MCA MSRs

[Sergiy Kibrik]

Add build-time checks for newly introduced INTEL/AMD config options when
calling vmce_{intel/amd}_{rdmsr/wrmsr}() routines.
This way a platform-specific code can be omitted in vmce code, if this
platform is disabled in config.

Signed-off-by: Sergiy Kibrik 
---
 xen/arch/x86/cpu/mcheck/vmce.c | 12 
 1 file changed, 8 insertions(+), 4 deletions(-)

diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c
index c437f62c0a..be229684a4 100644
--- a/xen/arch/x86/cpu/mcheck/vmce.c
+++ b/xen/arch/x86/cpu/mcheck/vmce.c
@@ -141,12 +141,14 @@ static int bank_mce_rdmsr(const struct vcpu *v, uint32_t 
msr, uint64_t *val)
 case X86_VENDOR_CENTAUR:
 case X86_VENDOR_SHANGHAI:
 case X86_VENDOR_INTEL:
-ret = vmce_intel_rdmsr(v, msr, val);
+ret = IS_ENABLED(CONFIG_INTEL) ?
+  vmce_intel_rdmsr(v, msr, val) : -ENODEV;
 break;
 
 case X86_VENDOR_AMD:
 case X86_VENDOR_HYGON:
-ret = vmce_amd_rdmsr(v, msr, val);
+ret = IS_ENABLED(CONFIG_AMD) ?
+  vmce_amd_rdmsr(v, msr, val) : -ENODEV;
 break;
 
 default:
@@ -272,12 +274,14 @@ static int bank_mce_wrmsr(struct vcpu *v, uint32_t msr, 
uint64_t val)
 switch ( boot_cpu_data.x86_vendor )
 {
 case X86_VENDOR_INTEL:
-ret = vmce_intel_wrmsr(v, msr, val);
+ret = IS_ENABLED(CONFIG_INTEL) ?
+  vmce_intel_wrmsr(v, msr, val) : -ENODEV;
 break;
 
 case X86_VENDOR_AMD:
 case X86_VENDOR_HYGON:
-ret = vmce_amd_wrmsr(v, msr, val);
+ret = IS_ENABLED(CONFIG_AMD) ?
+  vmce_amd_wrmsr(v, msr, val) : -ENODEV;
 break;
 
 default:
-- 
2.25.1