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@@ -23,8 +26,8 @@ struct B : A {
void g(A *a) { a->foo(); }
// CHECK1-LABEL: define{{.*}} void @_ZN5test14fooAEv()
-// CHECK1: call void @_ZN5test11AC1Ev(ptr
-// CHECK1: %[[VTABLE:.*]] = load ptr addrspace(1), ptr %{{.*}}
+// CHECK1: call{{.*}} void @_ZN5test11AC1Ev(ptr
@@ -6088,6 +6088,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
StringRef Prefix =
llvm::Triple::getArchTypePrefix(getTarget().getTriple().getArch());
if (!Prefix.empty()) {
+if (Prefix == "spv" &&
+
@@ -6088,6 +6088,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
StringRef Prefix =
llvm::Triple::getArchTypePrefix(getTarget().getTriple().getArch());
if (!Prefix.empty()) {
+if (Prefix == "spv" &&
+
https://github.com/AlexVlx commented:
> @AlexVlx, do you think it's worth promoting
> [SPV_INTEL_inline_assembly](https://github.com/intel/llvm/blob/sycl/sycl/doc/design/spirv-extensions/SPV_INTEL_inline_assembly.asciidoc)
> and
>
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/89796
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https://github.com/AlexVlx commented:
> Please fix the commit message before you merge; otherwise LGTM
For the commit message I was thinking something along the following lines: `At
the moment, Clang is rather liberal in assuming that 0 (and by extension
unqualified) is always a safe
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/7] Add initial support for AMDGCN flavoured SPIRV.
---
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/7] Add initial support for AMDGCN flavoured SPIRV.
---
@@ -0,0 +1,111 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -fsyntax-only -verify %s
+
+#pragma OPENCL EXTENSION cl_khr_fp64 : enable
+
+kernel void test () {
+
+ int sgpr = 0, vgpr = 0, imm = 0;
+
+ // sgpr constraints
+ __asm__
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/7] Add initial support for AMDGCN flavoured SPIRV.
---
@@ -0,0 +1,111 @@
+// REQUIRES: amdgpu-registered-target
+// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -fsyntax-only -verify %s
+
+#pragma OPENCL EXTENSION cl_khr_fp64 : enable
+
+kernel void test () {
+
+ int sgpr = 0, vgpr = 0, imm = 0;
+
+ // sgpr constraints
+ __asm__
https://github.com/AlexVlx approved this pull request.
This looks fine to me (I do hate that macro being defined on the host though,
so I am biased). Thanks!
https://github.com/llvm/llvm-project/pull/91478
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@@ -23,8 +26,8 @@ struct B : A {
void g(A *a) { a->foo(); }
// CHECK1-LABEL: define{{.*}} void @_ZN5test14fooAEv()
-// CHECK1: call void @_ZN5test11AC1Ev(ptr
-// CHECK1: %[[VTABLE:.*]] = load ptr addrspace(1), ptr %{{.*}}
+// CHECK1: call{{.*}} void @_ZN5test11AC1Ev(ptr
@@ -1,14 +1,17 @@
// RUN: %clang_cc1 %s -triple=amdgcn-amd-amdhsa -std=c++11 -emit-llvm -o %t.ll
-O1 -disable-llvm-passes -fms-extensions -fstrict-vtable-pointers
+// RUN: %clang_cc1 %s -triple i686-pc-win32 -emit-llvm -o %t.ms.ll -O1
-disable-llvm-passes -fms-extensions
https://github.com/AlexVlx edited
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https://github.com/AlexVlx commented:
> Would be good to fold
> clang/test/CodeGenCXX/vtable-assume-load-nonzero-default-address-space.cpp
> into one of the files it was copied from, otherwise LGTM.
Apologies for the delay, I was away; should be sorted now.
@@ -1370,7 +1370,7 @@ let IntrProperties = [IntrNoMem, IntrSpeculatable,
IntrWillReturn] in {
// The result of eh.typeid.for depends on the enclosing function, but inside a
// given function it is 'const' and may be CSE'd etc.
-def int_eh_typeid_for :
@@ -0,0 +1,288 @@
+// RUN: %clang_cc1 %s -triple=spirv64-unknown-unknown -fsycl-is-device
-std=c++11 -emit-llvm -o %t.ll -O1 -disable-llvm-passes -fms-extensions
-fstrict-vtable-pointers
+// FIXME: Assume load should not require -fstrict-vtable-pointers
+
+// RUN: FileCheck
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/7] Add initial support for AMDGCN flavoured SPIRV.
---
@@ -309,7 +309,45 @@ StringRef AMDGPU::getCanonicalArchName(const Triple ,
StringRef Arch) {
void AMDGPU::fillAMDGPUFeatureMap(StringRef GPU, const Triple ,
StringMap ) {
// XXX - What does the member GPU mean if device name string passed
@@ -54,3 +56,76 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+static const AMDGPUTargetInfo AMDGPUTI(llvm::Triple("amdgcn-amd-amdhsa"), {});
+
+ArrayRef
@@ -309,7 +309,45 @@ StringRef AMDGPU::getCanonicalArchName(const Triple ,
StringRef Arch) {
void AMDGPU::fillAMDGPUFeatureMap(StringRef GPU, const Triple ,
StringMap ) {
// XXX - What does the member GPU mean if device name string passed
@@ -6088,6 +6088,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
StringRef Prefix =
llvm::Triple::getArchTypePrefix(getTarget().getTriple().getArch());
if (!Prefix.empty()) {
+if (Prefix == "spv" &&
+
@@ -6088,6 +6088,9 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl
GD, unsigned BuiltinID,
StringRef Prefix =
llvm::Triple::getArchTypePrefix(getTarget().getTriple().getArch());
if (!Prefix.empty()) {
+if (Prefix == "spv" &&
+
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/6] Add initial support for AMDGCN flavoured SPIRV.
---
@@ -54,3 +56,77 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+namespace {
+const AMDGPUTargetInfo AMDGPUTI(llvm::Triple("amdgcn-amd-amdhsa"), {});
+
+} //
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/5] Add initial support for AMDGCN flavoured SPIRV.
---
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/4] Add initial support for AMDGCN flavoured SPIRV.
---
@@ -0,0 +1,294 @@
+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple spirv64-amd-amdhsa -x hip \
+// RUN: -aux-triple x86_64-unknown-linux-gnu -fcuda-is-device -emit-llvm %s \
+// RUN: -o - | FileCheck %s
+
+// RUN:
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/4] Add initial support for AMDGCN flavoured SPIRV.
---
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/3] Add initial support for AMDGCN flavoured SPIRV.
---
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/2] Add initial support for AMDGCN flavoured SPIRV.
---
@@ -2216,7 +2216,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy =
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/88182
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https://github.com/AlexVlx commented:
> This adds a third copy of the same test, can we just merge them add add three
> RUN lines with different CHECK prefixes?
I've merged the address-space related ones, but I've left the basic one in
place.
https://github.com/llvm/llvm-project/pull/88182
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 01/10] Start migrating away from the embedded assumption that
the
@@ -2216,7 +2216,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy =
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/9] Start migrating away from the embedded assumption that
the
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/8] Start migrating away from the embedded assumption that
the
AlexVlx wrote:
> > > How much of this is actually different from the existing target info for
> > > AMDGCN? Seems like we're doing a lot of redundant stuff like defining
> > > macros or features.
> >
> >
> > That's part of the point, it's not actually supposed to differ in those
> >
@@ -54,3 +56,289 @@ void SPIRV64TargetInfo::getTargetDefines(const LangOptions
,
BaseSPIRVTargetInfo::getTargetDefines(Opts, Builder);
DefineStd(Builder, "SPIRV64", Opts);
}
+
+static constexpr Builtin::Info BuiltinInfo[] = {
+#define BUILTIN(ID, TYPE, ATTRS)
AlexVlx wrote:
> How much of this is actually different from the existing target info for
> AMDGCN? Seems like we're doing a lot of redundant stuff like defining macros
> or features.
That's part of the point, it's not actually supposed to differ in those
particular regards, up to the point
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/8] Start migrating away from the embedded assumption that
the
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/89796
>From 662f160418c704f45e57e751168903d774b74303 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Tue, 23 Apr 2024 17:41:25 +0100
Subject: [PATCH 1/2] Add initial support for AMDGCN flavoured SPIRV.
---
https://github.com/AlexVlx created
https://github.com/llvm/llvm-project/pull/89796
This change seeks to add support for vendor flavoured SPIRV - more
specifically, AMDGCN flavoured SPIRV. The aim is to generate SPIRV that carries
some extra bits of information that are only usable by AMDGCN
https://github.com/AlexVlx approved this pull request.
LGTM, please have a peek at the comment if possible.
https://github.com/llvm/llvm-project/pull/88939
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AlexVlx wrote:
a) Thanks!; b) apologies for the noise; c) this was actually done on purpose, I
actively eschewed changing Logical SPIRV because it wasn't actually clear to me
if in the long run it'd have the same AS map / would use numerical 1 for
globals. If Logical SPIRV is going to go with
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/8] Start migrating away from the embedded assumption that
the
@@ -3581,8 +3582,10 @@ ConstantAddress
CodeGenModule::GetAddrOfTemplateParamObject(
isExternallyVisible(TPO->getLinkageAndVisibility().getLinkage())
? llvm::GlobalValue::LinkOnceODRLinkage
: llvm::GlobalValue::InternalLinkage;
- auto *GV = new
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/8] Start migrating away from the embedded assumption that
the
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/7] Start migrating away from the embedded assumption that
the
AlexVlx wrote:
Merged, thanks everyone for the reviews!
https://github.com/llvm/llvm-project/pull/88455
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https://github.com/AlexVlx closed
https://github.com/llvm/llvm-project/pull/88455
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https://github.com/AlexVlx commented:
> > Thanks @AlexVlx for this change. This should work fine for
> > SPIRV-LLVM-Translator (and SPIR-V backend). Adding @michalpaszkowski for
> > input from SPIR-V backend side. Recently, this restriction on LLVM IR input
> > to our translator was
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/88455
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https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88455
>From 6d9e979f09802b94310017901b5b6b58bfa05c1c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Fri, 12 Apr 2024 00:21:02 +0100
Subject: [PATCH 1/3] Add AS 1 for Globals in the SPIR & SPIRV datalayout
strings.
https://github.com/AlexVlx commented:
> Please also fix llvm/lib/Target/SPIRV/SPIRVTargetMachine.cpp
Done.
https://github.com/llvm/llvm-project/pull/88455
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https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88455
>From 6d9e979f09802b94310017901b5b6b58bfa05c1c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Fri, 12 Apr 2024 00:21:02 +0100
Subject: [PATCH 1/2] Add AS 1 for Globals in the SPIR & SPIRV datalayout
strings.
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88455
>From 6d9e979f09802b94310017901b5b6b58bfa05c1c Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Fri, 12 Apr 2024 00:21:02 +0100
Subject: [PATCH] Add AS 1 for Globals in the SPIR & SPIRV datalayout strings.
---
AlexVlx wrote:
> Thanks @AlexVlx for this change. This should work fine for
> SPIRV-LLVM-Translator (and SPIR-V backend). Adding @michalpaszkowski for
> input from SPIR-V backend side. Recently, this restriction on LLVM IR input
> to our translator was docuemnted:
>
@@ -3581,8 +3582,10 @@ ConstantAddress
CodeGenModule::GetAddrOfTemplateParamObject(
isExternallyVisible(TPO->getLinkageAndVisibility().getLinkage())
? llvm::GlobalValue::LinkOnceODRLinkage
: llvm::GlobalValue::InternalLinkage;
- auto *GV = new
AlexVlx wrote:
> The change seems reasonable.
>
> > CodeGen/LLVM will default to AS0 in this case, which produces Globals that
> > end up in the private address space for e.g. OCL, HIPSPV or SYCL.
>
> Can we add a test checking LLVM address space for globals emitted from
> OCL/HIPSPV/SYCL,
https://github.com/AlexVlx created
https://github.com/llvm/llvm-project/pull/88455
Currently neither the SPIR nor the SPIRV targets specify the AS for globals in
their datalayout strings. This is problematic because CodeGen/LLVM will default
to AS0 in this case, which produces Globals that
@@ -3581,8 +3582,10 @@ ConstantAddress
CodeGenModule::GetAddrOfTemplateParamObject(
isExternallyVisible(TPO->getLinkageAndVisibility().getLinkage())
? llvm::GlobalValue::LinkOnceODRLinkage
: llvm::GlobalValue::InternalLinkage;
- auto *GV = new
@@ -2216,7 +2216,7 @@ static llvm::Value *EmitTypeidFromVTable(CodeGenFunction
, const Expr *E,
}
llvm::Value *CodeGenFunction::EmitCXXTypeidExpr(const CXXTypeidExpr *E) {
- llvm::Type *PtrTy = llvm::PointerType::getUnqual(getLLVMContext());
+ llvm::Type *PtrTy =
@@ -4551,6 +4554,7 @@ llvm::Constant *CodeGenModule::GetOrCreateLLVMFunction(
llvm::Function *F =
llvm::Function::Create(FTy, llvm::Function::ExternalLinkage,
+ getDataLayout().getProgramAddressSpace(),
AlexVlx wrote:
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/7] Start migrating away from the embedded assumption that
the
AlexVlx wrote:
> > I'm not quite sure how to parse this comment, could you explain what you
> > have in mind here? The problem is precisely that the FE assumes 0 is fine /
> > picks it by default, which ends up into dangerzones when e.g. a target
> > happened to use 0 to point to private
AlexVlx wrote:
> > I'm not quite sure how to parse this comment, could you explain what you
> > have in mind here? The problem is precisely that the FE assumes 0 is fine /
> > picks it by default, which ends up into dangerzones when e.g. a target
> > happened to use 0 to point to private
https://github.com/AlexVlx commented:
> > querying a modules global AS from the target, rather than from the data
> > layout (some DL's are incomplete, e.g. SPIRV's)
That is a bug in those DataLayouts
Do we spell out the requirement somewhere? I am only asking because, for
example, [neither
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/88182
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https://github.com/AlexVlx commented:
> It's very uncommon for LLVM to need to come up with an address space on its
> own, as opposed to just propagating the original address space of some memory
> / operation as chosen by the frontend. LLVM occasionally creates new storage
> allocations,
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https://github.com/AlexVlx commented:
> Why can't we just declare that the "generic" address-space must always be 0?
> The specific numbers we use for address-spaces are completely arbitrary
> anyway.
If we were to do this, some targets would need to change to accomodate it; it
would also
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/6] Start migrating away from the embedded assumption that
the
https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/88182
>From 426e74cabb003eb5dc83adf347a5800d49bc87b7 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Mon, 18 Mar 2024 11:49:12 +
Subject: [PATCH 1/5] Start migrating away from the embedded assumption that
the
https://github.com/AlexVlx created
https://github.com/llvm/llvm-project/pull/88182
At the moment, Clang is rather liberal in assuming that 0 (and by extension
unqualified) is always a safe default. This does not work for targets that
actually use a different value for the default / generic
AlexVlx wrote:
Thank you everyone for the reviews.
https://github.com/llvm/llvm-project/pull/85460
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https://github.com/AlexVlx closed
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AlexVlx wrote:
> CI looks unhappy, mlir also seems to need updates:
>
> MLIR :: Target/LLVMIR/llvmir.mlir MLIR :: mlir-cpu-runner/x86-varargs.mlir
Done.
https://github.com/llvm/llvm-project/pull/85460
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@@ -1318,16 +1318,16 @@ define void @instructions.va_arg(i8* %v, ...) {
%ap2 = bitcast i8** %ap to i8*
call void @llvm.va_start(i8* %ap2)
- ; CHECK: call void @llvm.va_start(ptr %ap2)
+ ; CHECK: call void @llvm.va_start.p0(ptr %ap2)
va_arg i8* %ap2, i32
; CHECK:
@@ -700,10 +700,13 @@ class MSBuiltin {
//===--- Variable Argument Handling Intrinsics
===//
//
-def int_vastart : DefaultAttrsIntrinsic<[], [llvm_ptr_ty], [],
"llvm.va_start">;
-def int_vacopy : DefaultAttrsIntrinsic<[], [llvm_ptr_ty,
@@ -700,10 +700,13 @@ class MSBuiltin {
//===--- Variable Argument Handling Intrinsics
===//
//
-def int_vastart : DefaultAttrsIntrinsic<[], [llvm_ptr_ty], [],
"llvm.va_start">;
-def int_vacopy : DefaultAttrsIntrinsic<[], [llvm_ptr_ty,
@@ -700,10 +700,13 @@ class MSBuiltin {
//===--- Variable Argument Handling Intrinsics
===//
//
-def int_vastart : DefaultAttrsIntrinsic<[], [llvm_ptr_ty], [],
"llvm.va_start">;
-def int_vacopy : DefaultAttrsIntrinsic<[], [llvm_ptr_ty,
@@ -1713,7 +1716,7 @@ def int_coro_subfn_addr : DefaultAttrsIntrinsic<
///===-- Other Intrinsics
--===//
//
-// TODO: We should introduce a new memory kind fo traps (and other side
effects
+// TODO: We should introduce a new
@@ -0,0 +1,22 @@
+// REQUIRES: spirv-registered-target
AlexVlx wrote:
I was not certain and erred on the side of caution. You are correct (as far as
I can tell), and have removed the requirement. Thank you for pointing it out!
@@ -0,0 +1,22 @@
+// REQUIRES: spirv-registered-target
+// RUN: %clang_cc1 -triple spirv64-unknown-unknown -fcuda-is-device -emit-llvm
-o - %s | FileCheck %s
+struct x {
+ double b;
+ long a;
+};
+
+void testva(int n, ...) {
+ __builtin_va_list ap;
+ __builtin_va_start(ap,
@@ -0,0 +1,22 @@
+// REQUIRES: spirv-registered-target
+// RUN: %clang_cc1 -triple spirv64-unknown-unknown -fcuda-is-device -emit-llvm
-o - %s | FileCheck %s
+struct x {
AlexVlx wrote:
Done.
https://github.com/llvm/llvm-project/pull/85460
@@ -139,10 +139,10 @@ bool
AMDGPURemoveIncompatibleFunctions::checkFunction(Function ) {
const GCNSubtarget *ST =
static_cast(TM->getSubtargetImpl(F));
- // Check the GPU isn't generic. Generic is used for testing only
- // and we don't want this pass to interfere
@@ -49,6 +49,11 @@ constexpr uint32_t VersionMajorV5 = 1;
/// HSA metadata minor version for code object V5.
constexpr uint32_t VersionMinorV5 = 2;
+/// HSA metadata major version for code object V6.
+constexpr uint32_t VersionMajorV6 = 1;
+/// HSA metadata minor version for
https://github.com/AlexVlx edited
https://github.com/llvm/llvm-project/pull/76955
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https://github.com/AlexVlx approved this pull request.
LGTM in general, versioning seems fine; I had a pair of very minor
nits/questions, but they're not blocking concerns. Thanks!
https://github.com/llvm/llvm-project/pull/76955
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https://github.com/AlexVlx closed
https://github.com/llvm/llvm-project/pull/78915
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https://github.com/AlexVlx updated
https://github.com/llvm/llvm-project/pull/78915
>From 37453ff13fd7a61f2072069cf94615497c748089 Mon Sep 17 00:00:00 2001
From: Alex Voicu
Date: Sun, 21 Jan 2024 21:52:52 +
Subject: [PATCH 1/2] Add automated inclusion for the forwarding header
packaged
https://github.com/AlexVlx created
https://github.com/llvm/llvm-project/pull/78915
The forwarding header used by `hipstdpar` on AMDGPU targets is now pacakged
with `rocThrust`. This change augments the ROCm Driver component so that it can
automatically pick up the packaged header iff the user
@@ -209,6 +210,13 @@ void AMDGCN::Linker::ConstructJob(Compilation , const
JobAction ,
if (JA.getType() == types::TY_LLVM_BC)
return constructLlvmLinkCommand(C, JA, Inputs, Output, Args);
+ if (Args.getLastArgValue(options::OPT_mcpu_EQ) == "generic") {
+
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