https://github.com/Bryce-MW closed
https://github.com/llvm/llvm-project/pull/81656
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https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/81656
>From 9bea6282aae73372a80aa3d0532ae0532b4ca948 Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 9 Feb 2024 16:56:57 -0600
Subject: [PATCH 1/3] [clang] Allow builtin addc/subc to be constant evaluated
---
Bryce-MW wrote:
I swear I had meant to add tests! I did see a place that looks good to add them
before so I've done that. Which allowed me to find out that I had not done my
implementation correctly so I fixed that up.
https://github.com/llvm/llvm-project/pull/81656
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/81656
>From 9bea6282aae73372a80aa3d0532ae0532b4ca948 Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 9 Feb 2024 16:56:57 -0600
Subject: [PATCH 1/2] [clang] Allow builtin addc/subc to be constant evaluated
---
@@ -12696,6 +12696,56 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const
CallExpr *E,
return BuiltinOp == Builtin::BI__atomic_always_lock_free ?
Success(0, E) : Error(E);
}
+ case Builtin::BI__builtin_addcb:
+ case Builtin::BI__builtin_addcs:
+ case
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/81656
>From 9bea6282aae73372a80aa3d0532ae0532b4ca948 Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 9 Feb 2024 16:56:57 -0600
Subject: [PATCH] [clang] Allow builtin addc/subc to be constant evaluated
---
@@ -12691,6 +12691,56 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const
CallExpr *E,
return BuiltinOp == Builtin::BI__atomic_always_lock_free ?
Success(0, E) : Error(E);
}
+ case Builtin::BI__builtin_addcb:
+ case Builtin::BI__builtin_addcs:
+ case
@@ -12691,6 +12691,56 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const
CallExpr *E,
return BuiltinOp == Builtin::BI__atomic_always_lock_free ?
Success(0, E) : Error(E);
}
+ case Builtin::BI__builtin_addcb:
+ case Builtin::BI__builtin_addcs:
+ case
@@ -12691,6 +12691,56 @@ bool IntExprEvaluator::VisitBuiltinCallExpr(const
CallExpr *E,
return BuiltinOp == Builtin::BI__atomic_always_lock_free ?
Success(0, E) : Error(E);
}
+ case Builtin::BI__builtin_addcb:
+ case Builtin::BI__builtin_addcs:
+ case
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/81656
>From 9bea6282aae73372a80aa3d0532ae0532b4ca948 Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 9 Feb 2024 16:56:57 -0600
Subject: [PATCH] [clang] Allow builtin addc/subc to be constant evaluated
---
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/81656
>From 6663b6269aad51ebf8cc0703d8594f0216cf5610 Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 9 Feb 2024 16:56:57 -0600
Subject: [PATCH] [clang] Allow builtin addc/subc to be constant evaluated
---
https://github.com/Bryce-MW created
https://github.com/llvm/llvm-project/pull/81656
There is some overlap with `*_overflow` which have the same result as these
functions with a carry in of zero, but the type inference and way of returning
results is different so it didn't seem worth handling
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/16] [X86] Use RORX over SHR imm
---
Bryce-MW wrote:
I spent some time trying out something much more complex: starting at the user
of flags that has other inputs (ADC, SBB, CMOVcc are the main ones), trace back
the non-flags inputs to see if the node producing the flags inputs is along
their paths then check the path from there
https://github.com/Bryce-MW ready_for_review
https://github.com/llvm/llvm-project/pull/77964
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https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/16] [X86] Use RORX over SHR imm
---
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/16] [X86] Use RORX over SHR imm
---
Bryce-MW wrote:
I think the fail on Windows is not related. Hopefully a merge fixes it...
https://github.com/llvm/llvm-project/pull/77964
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https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/15] [X86] Use RORX over SHR imm
---
@@ -4216,6 +4217,97 @@ MachineSDNode *X86DAGToDAGISel::emitPCMPESTR(unsigned
ROpc, unsigned MOpc,
return CNode;
}
+// When the consumer of a right shift (arithmetic or logical) wouldn't notice
+// the difference if the instruction was a rotate right instead (because the
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/15] [X86] Use RORX over SHR imm
---
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/14] [X86] Use RORX over SHR imm
---
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/14] [X86] Use RORX over SHR imm
---
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/13] [X86] Use RORX over SHR imm
---
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/11] [X86] Use RORX over SHR imm
---
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/11] [X86] Use RORX over SHR imm
---
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 01/10] [X86] Use RORX over SHR imm
---
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 1/9] [X86] Use RORX over SHR imm
---
https://github.com/Bryce-MW updated
https://github.com/llvm/llvm-project/pull/77964
>From d4c312b9dbf447d0a53dda0e6cdc482bd908430b Mon Sep 17 00:00:00 2001
From: Bryce Wilson
Date: Fri, 12 Jan 2024 16:01:32 -0600
Subject: [PATCH 1/8] [X86] Use RORX over SHR imm
---
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