"fsl,imx8qxp-cm4" and "fsl,imx8qm-cm4" need minimum 2 power domains. Other
platform doesn't require 'power-domain'.
Signed-off-by: Frank Li
---
Notes:
Change from v2 to v3
- only imx8qxp and imx8qm need power-domain, other platform don't need it.
- u
On Fri, Jun 07, 2024 at 09:32:26AM +0200, Krzysztof Kozlowski wrote:
> On 06/06/2024 17:00, Frank Li wrote:
> > "fsl,imx8qxp-cm4" and "fsl,imx8qm-cm4" need minimum 2 power domains. Keep
> > the same restriction for other compatible string.
> >
> >
ion that
> got affected by the fundamental reset like BAR, DMA etc...
>
> This change also warrants skipping the cleanups in unbind() if already done
> in epc_deinit().
>
> Reviewed-by: Niklas Cassel
> Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Frank Li
> ---
ly from glue
> drivers.
>
> Suggested-by: Bjorn Helgaas
> Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Frank Li
> ---
> drivers/pci/controller/dwc/pci-dra7xx.c | 2 +-
> drivers/pci/controller/dwc/pci-imx6.c | 2 +-
> drivers/pci/contro
lgaas
> Closes: https://lore.kernel.org/linux-pci/20240528195539.GA458945@bhelgaas/
> Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Frank Li
> ---
> drivers/pci/controller/dwc/pci-layerscape-ep.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drive
"fsl,imx8qxp-cm4" and "fsl,imx8qm-cm4" need minimum 2 power domains. Keep
the same restriction for other compatible string.
Signed-off-by: Frank Li
---
Notes:
Change from v1 to v2
- set minitem to 2 at top
- Add imx8qm compatible string also
- use not logic
"fsl,imx8qxp-cm4" just need 2 power domains. Keep the same restriction for
other compatible string.
Signed-off-by: Frank Li
---
Notes:
pass dt_binding_check.
make ARCH=arm64 CROSS_COMPILE=aarch64-linux-gnu- -j8 dt_binding_check
DT_SCHEMA_FILES=fsl,imx-rproc.yaml
On Fri, May 24, 2024 at 07:27:00PM +0100, Dave Stevenson wrote:
> From: Phil Elwell
>
> Slave addresses for DMA are meant to be supplied as physical addresses
> (contrary to what struct snd_dmaengine_dai_dma_data does).
Can you use the same content for patch 14-17?
Frank
>
> Signed-off-by:
On Fri, May 24, 2024 at 07:26:55PM +0100, Dave Stevenson wrote:
> There is a need to account for dma-ranges and iommus in the
> dma mapping process, and the public API for handling that is
> dma_map_resource.
what's means?
>
> Add support for mapping addresses to the DMA driver.
>
>
On Fri, May 24, 2024 at 07:26:53PM +0100, Dave Stevenson wrote:
> The code handling DMA mapping is currently incorrect and
> needs a sequence of fixups.
Can you descript what incorrect here?
> Move the mapping out into a separate function and structure
> to allow for those fixes to be applied
On Fri, May 24, 2024 at 07:26:52PM +0100, Dave Stevenson wrote:
> From: Stefan Wahren
>
> In preparation to support more platforms pass the dma_chan to the
> generic functions. This provides access to the DMA device and possible
> platform specific data.
why need this change? you can easy
On Fri, May 24, 2024 at 07:26:51PM +0100, Dave Stevenson wrote:
> From: Stefan Wahren
>
> The parameters info and finalextrainfo are platform specific. So drop
> them by generating them within bcm2835_dma_create_cb_chain().
Drop 'info' and 'finalextrainfo' because these can be generated by
On Fri, May 24, 2024 at 07:26:50PM +0100, Dave Stevenson wrote:
> From: Stefan Wahren
>
> Actually the criteria to increment source & destination address doesn't
> based on platform specific bits. It's just the DMA transfer direction which
> is translated into the info bits. So introduce two new
On Fri, May 24, 2024 at 07:26:49PM +0100, Dave Stevenson wrote:
> From: Stefan Wahren
>
> Similar to the info generation, generate the final extra info with a
> separate function. This is necessary to introduce other platforms
> with different info bits.
Each patch commit is independent.
On Fri, May 24, 2024 at 07:26:48PM +0100, Dave Stevenson wrote:
> From: Stefan Wahren
>
> Actually the generation of the Control Block info follows some simple
> rules. So handle this with a separate function to avoid open coding
> for every DMA operation. Another advantage is that we can easier
On Fri, May 24, 2024 at 07:26:46PM +0100, Dave Stevenson wrote:
> From: Stefan Wahren
>
> Nowadays there is a generic property for dma-channel-mask in the DMA
> controller binding. So prefer this one instead of the old vendor specific
> one. Print a warning in case the old one is used. Btw use
On Mon, Jun 03, 2024 at 10:09:36AM +0200, Amelie Delaunay wrote:
> On 5/31/24 22:21, Frank Li wrote:
> > On Fri, May 31, 2024 at 05:07:05PM +0200, Amelie Delaunay wrote:
> > > STM32 DMA3 driver supports the 3 hardware configurations of the STM32 DMA3
> > > controller:
&
On Fri, May 31, 2024 at 05:07:05PM +0200, Amelie Delaunay wrote:
> STM32 DMA3 driver supports the 3 hardware configurations of the STM32 DMA3
> controller:
> - LPDMA (Low Power): 4 channels, no FIFO
> - GPDMA (General Purpose): 16 channels, FIFO from 8 to 32 bytes
> - HPDMA (High Performance): 16
On Mon, May 20, 2024 at 05:49:42PM +0200, Amelie Delaunay wrote:
> Add DMA_CYCLIC capability and relative device_prep_dma_cyclic ops with
> stm32_dma3_prep_dma_cyclic(). It reuses stm32_dma3_chan_prep_hw() and
> stm32_dma3_chan_prep_hwdesc() helpers.
>
> Signed-off-by: Amelie Delaunay
> ---
>
On Mon, May 20, 2024 at 05:49:41PM +0200, Amelie Delaunay wrote:
> STM32 DMA3 driver supports the 3 hardware configurations of the STM32 DMA3
> controller:
> - LPDMA (Low Power): 4 channels, no FIFO
> - GPDMA (General Purpose): 16 channels, FIFO from 8 to 32 bytes
> - HPDMA (High Performance): 16
On Fri, May 17, 2024 at 11:42:17AM +0200, Amelie Delaunay wrote:
> On 5/16/24 19:09, Frank Li wrote:
> > On Thu, May 16, 2024 at 05:25:58PM +0200, Amelie Delaunay wrote:
> > > On 5/15/24 20:56, Frank Li wrote:
> > > > On Tue, Apr 23, 2024 at 02:32:55PM +0200, Amelie D
On Thu, May 16, 2024 at 05:25:58PM +0200, Amelie Delaunay wrote:
> On 5/15/24 20:56, Frank Li wrote:
> > On Tue, Apr 23, 2024 at 02:32:55PM +0200, Amelie Delaunay wrote:
> > > STM32 DMA3 driver supports the 3 hardware configurations of the STM32 DMA3
> > > controller:
On Tue, Apr 23, 2024 at 02:32:55PM +0200, Amelie Delaunay wrote:
> STM32 DMA3 driver supports the 3 hardware configurations of the STM32 DMA3
> controller:
> - LPDMA (Low Power): 4 channels, no FIFO
> - GPDMA (General Purpose): 16 channels, FIFO from 8 to 32 bytes
> - HPDMA (High Performance): 16
On Mon, May 13, 2024 at 11:21:18AM +0200, Amelie Delaunay wrote:
> Hi Frank,
>
> On 5/7/24 22:26, Frank Li wrote:
> > On Tue, May 07, 2024 at 01:33:31PM +0200, Amelie Delaunay wrote:
> > > Hi Vinod,
> > >
> > > Thanks for the review.
> > >
>
On Tue, May 07, 2024 at 01:33:31PM +0200, Amelie Delaunay wrote:
> Hi Vinod,
>
> Thanks for the review.
>
> On 5/4/24 14:40, Vinod Koul wrote:
> > On 23-04-24, 14:32, Amelie Delaunay wrote:
> > > STM32 DMA3 driver supports the 3 hardware configurations of the STM32 DMA3
> > > controller:
> > > -
On Thu, Apr 18, 2024 at 06:53:02PM -0700, Dexuan Cui wrote:
> There has been an effort to make the pci-hyperv driver support
> async-probing to reduce the boot time. With async-probing, multiple
> kernel threads can be running hv_pci_probe() -> create_root_hv_pci_bus() ->
>
he notification
> before the EPF drivers bind() and in those cases the EPF drivers will miss
> the event. To accommodate this, EPC core is now caching the state of the
> EPC initialization in 'init_complete' flag and pci-ep-cfs driver sends the
> notification to EPF drivers based
().
>
> With this change, the check for 'core_init_notifier' flag can now be
> dropped from dw_pcie_ep_init() API. This will also allow us to remove the
> 'core_init_notifier' flag completely in the later commits.
>
> Reviewed-by: Yoshihiro Shimoda
> Reviewed-by: Niklas Cassel
Revie
-by: Frank Li
---
drivers/pci/controller/dwc/pci-layerscape-ep.c | 7 ++-
drivers/pci/controller/dwc/pci-layerscape.c| 7 ++-
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape-ep.c
b/drivers/pci/controller/dwc/pci-layerscape-ep.c
On Tue, Feb 27, 2024 at 06:02:30PM +0530, Manivannan Sadhasivam wrote:
> On Mon, Feb 26, 2024 at 12:20:41PM -0500, Frank Li wrote:
> > On Sat, Feb 24, 2024 at 12:24:15PM +0530, Manivannan Sadhasivam wrote:
> > > Now that the API is available, let's make use of i
On Tue, Feb 27, 2024 at 05:51:41PM +0530, Manivannan Sadhasivam wrote:
> On Mon, Feb 26, 2024 at 12:04:33PM -0500, Frank Li wrote:
> > On Sat, Feb 24, 2024 at 12:24:12PM +0530, Manivannan Sadhasivam wrote:
> > > Currently, dw_pcie_ep_init_registers() API is directly
On Tue, Feb 27, 2024 at 06:00:24PM +0530, Manivannan Sadhasivam wrote:
> On Mon, Feb 26, 2024 at 12:18:18PM -0500, Frank Li wrote:
> > On Sat, Feb 24, 2024 at 12:24:14PM +0530, Manivannan Sadhasivam wrote:
> > > The PCIe link can go to LINK_DOWN state in one of the f
On Sat, Feb 24, 2024 at 12:24:16PM +0530, Manivannan Sadhasivam wrote:
> All of the APIs are missing the Kernel-doc comments. Hence, add them.
>
> Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Frank Li
> ---
> drivers/pci/controller/dwc/pcie-desig
On Sat, Feb 24, 2024 at 12:24:15PM +0530, Manivannan Sadhasivam wrote:
> Now that the API is available, let's make use of it. It also handles the
> reinitialization of DWC non-sticky registers in addition to sending the
> notification to EPF drivers.
>
> Signed-off-by: Manivannan Sadhasivam
>
On Sat, Feb 24, 2024 at 12:24:14PM +0530, Manivannan Sadhasivam wrote:
> The PCIe link can go to LINK_DOWN state in one of the following scenarios:
>
> 1. Fundamental (PERST#)/hot/warm reset
> 2. Link transition from L2/L3 to L0
>From L0 to L2/l3
>
> In those cases, LINK_DOWN causes some
e drivers requiring refclk from host will
> send the notification once refclk is received, while others will send it
> during probe time itself.
>
> Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Frank Li
> ---
> drivers/pci/controller/dwc/pci-dra7xx.c | 2 ++
On Sat, Feb 24, 2024 at 12:24:12PM +0530, Manivannan Sadhasivam wrote:
> Currently, dw_pcie_ep_init_registers() API is directly called by the glue
> drivers requiring active refclk from host. But for the other drivers, it is
> getting called implicitly by dw_pcie_ep_init(). This is due to the fact
es confusion. So,
> let's rename it to dw_pcie_ep_init_registers() to make it clear that it
> initializes the DWC specific registers.
>
> Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Frank Li
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 6 +++---
>
refclk is received from host. For the rest
> of the drivers that gets the refclk locally, this API will be called
> within dw_pcie_ep_init().
>
> Fixes: e966f7390da9 ("PCI: dwc: Refactor core initialization code for EP
> mode")
> Co-developed-by: Vidya Sa
API that could be called by these
> drivers to cleanup the DWC specific resources. Currently, it just removes
> eDMA.
>
> Reported-by: Niklas Cassel
> Closes: https://lore.kernel.org/linux-pci/ZWYmX8Y%2F7Q9WMxES@x1-carbon
> Signed-off-by: Manivannan Sadhasivam
Reviewed-by
) to make the
> purpose of this API clear. This also aligns with the DWC host driver.
>
> Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Frank Li
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 4 ++--
> drivers/pci/controller/dwc/pcie-designware.h| 4 ++--
> d
r_gen4_remove_dw_pcie_ep().
>
> This simplifies the DWC layer.
>
> Signed-off-by: Manivannan Sadhasivam
Reviewed-by: Frank Li
> ---
> drivers/pci/controller/dwc/pcie-designware-ep.c | 9 +
> drivers/pci/controller/dwc/pcie-designware.h| 1 -
> driv
On Sat, Jan 20, 2024 at 01:14:52AM +0100, Paul Cercueil wrote:
> Hi Frank,
>
> Le vendredi 19 janvier 2024 à 16:49 -0500, Frank Li a écrit :
> > On Wed, Jan 17, 2024 at 01:26:43PM +0100, Paul Cercueil wrote:
> > > Add a new 'sg_was_mapped' field to the struct usb_r
On Wed, Jan 17, 2024 at 01:26:43PM +0100, Paul Cercueil wrote:
> Add a new 'sg_was_mapped' field to the struct usb_request. This field
> can be used to indicate that the scatterlist associated to the USB
> transfer has already been mapped into the DMA space, and it does not
> have to be done
From: Li Yang
Update the node name to be align with binding document.
Signed-off-by: Li Yang
Signed-off-by: Frank Li
---
arch/powerpc/boot/dts/fsl/bsc9131rdb.dts| 2 +-
arch/powerpc/boot/dts/fsl/bsc9132qds.dts| 2 +-
arch/powerpc/boot/dts/fsl/c293pcie.dts | 2 +-
arch/powerpc
From: Li Yang
Update dts to match dts binding document.
Signed-off-by: Li Yang
Signed-off-by: Frank Li
---
arch/powerpc/boot/dts/fsl/b4si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/bsc9131si-post.dtsi | 2 +-
arch/powerpc/boot/dts/fsl/bsc9132si-post.dtsi | 2 +-
arch/powerpc/boot/dts
not work because of the pcie@0 node fixup will be
overwrited by p1010si-post.dtsi file, so we move the pcie@0 node fixup
to p1010rdb-pb.dts and p1010rdb-pb_36b.dts.
Signed-off-by: Xiaowei Bao
Signed-off-by: Li Yang
Signed-off-by: Frank Li
---
arch/powerpc/boot/dts/fsl/p1010rdb-pb.dts | 16
From: Ran Wang
Enable Power Management feature on device tree, including MPC8536,
MPC8544, MPC8548, MPC8572, P1010, P1020, P1021, P1022, P2020, P2041,
P3041, T104X, T1024.
Signed-off-by: Zhao Chenhui
Signed-off-by: Ran Wang
Signed-off-by: Frank Li
---
arch/powerpc/boot/dts/fsl/mpc8536si
On Mon, Dec 04, 2023 at 11:08:29AM -0500, Frank Li wrote:
> Add suspend/resume support for Layerscape LS1043a.
>
> In the suspend path, PME_Turn_Off message is sent to the endpoint to
> transition the link to L2/L3_Ready state. In this SoC, there is no way to
> check if the
.
Acked-by: Roy Zang
Reviewed-by: Manivannan Sadhasivam
Signed-off-by: Frank Li
---
Notes:
Chagne from v5 to v6
- none
Change from v4 to v5
- update commit message
- use comments
/* Reset the PEX wrapper to bring the link out of L2 */
Change from v3 to v4
'pf' and 'lut' is just difference name in difference chips, but basic it is
a MMIO base address plus an offset.
Rename it to avoid duplicate pf_* and lut_* in driver.
Reviewed-by: Manivannan Sadhasivam
Acked-by: Roy Zang
Signed-off-by: Frank Li
---
Notes:
pf_lut is better than pf_
.
Acked-by: Roy Zang
Reviewed-by: Manivannan Sadhasivam
Signed-off-by: Frank Li
---
Notes:
Change from v5 to v6
- remove reduntant pci->pp.ops = _pcie_host_ops;
Change from v4 to v5
- update comit message
- remove a empty line
- use comments
/* Reset the PEX wrap
esume flow.
Acked-by: Roy Zang
Reviewed-by: Manivannan Sadhasivam
Signed-off-by: Frank Li
---
Notes:
Change from v4 to v6
- none
Change from v3 to v4
- update commit message
Add mani's review by tag
Change from v2 to v3
- fixed according to mani's feedback
1. upd
Add suspend/resume support for ls1043 and ls1021.
Change log see each patch
Frank Li (4):
PCI: layerscape: Add function pointer for exit_from_l2()
PCI: layerscape: Add suspend/resume for ls1021a
PCI: layerscape(ep): Rename pf_* as pf_lut_*
PCI: layerscape: Add suspend/resume for ls1043a
.
Signed-off-by: Frank Li
---
Notes:
Change from v4 to v5
- update commit message
- use comments
/* Reset the PEX wrapper to bring the link out of L2 */
Change from v3 to v4
- Call scfg_pcie_send_turnoff_msg() shared with ls1021a
- update commit message
'pf' and 'lut' is just difference name in difference chips, but basic it is
a MMIO base address plus an offset.
Rename it to avoid duplicate pf_* and lut_* in driver.
Signed-off-by: Frank Li
---
Notes:
pf_lut is better than pf_* or lut* because some chip use 'pf', some chip
use 'lut
.
Signed-off-by: Frank Li
---
Notes:
Change from v4 to v5
- update comit message
- remove a empty line
- use comments
/* Reset the PEX wrapper to bring the link out of L2 */
- pci->pp.ops = pcie->drvdata->ops,
ls_pcie_host_ops to the "ops" member of
esume flow.
Reviewed-by: Manivannan Sadhasivam
Signed-off-by: Frank Li
---
Notes:
Change from v4 to v5
- none
Change from v3 to v4
- update commit message
Add mani's review by tag
Change from v2 to v3
- fixed according to mani's feedback
1. update commit messa
Add suspend/resume support for ls1043 and ls1021.
Change log see each patch
Frank Li (4):
PCI: layerscape: Add function pointer for exit_from_l2()
PCI: layerscape: Add suspend/resume for ls1021a
PCI: layerscape(ep): Rename pf_* as pf_lut_*
PCI: layerscape: Add suspend/resume for ls1043a
On Thu, Nov 30, 2023 at 03:17:39PM -0500, Frank Li wrote:
> On Thu, Nov 30, 2023 at 10:21:00PM +0530, Manivannan Sadhasivam wrote:
> > On Wed, Nov 29, 2023 at 04:44:12PM -0500, Frank Li wrote:
> > > In the suspend path, PME_Turn_Off message is sent to the endpoint to
> &g
On Thu, Nov 30, 2023 at 10:21:00PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Nov 29, 2023 at 04:44:12PM -0500, Frank Li wrote:
> > In the suspend path, PME_Turn_Off message is sent to the endpoint to
> > transition the link to L2/L3_Ready state. In this SoC, there is no w
for
PCIE_PME_TO_L2_TIMEOUT_US before asserting the SoC specific PMXMTTURNOFF
bit to complete the PME_Turn_Off handshake. This link would then enter
L2/L3 state depending on the VAUX supply.
In the resume path, the link is brought back from L2 to L0 by doing a
software reset.
Signed-off-by: Frank Li
---
Notes:
Change
'pf' and 'lut' is just difference name in difference chips, but basic it is
a MMIO base address plus an offset.
Rename it to avoid duplicate pf_* and lut_* in driver.
Signed-off-by: Frank Li
---
Notes:
pf_lut is better than pf_* or lut* because some chip use 'pf', some chip
use 'lut
-by: Frank Li
---
Notes:
Change from v3 to v4
- update commit message.
- it is reset a glue logic part for PCI controller.
- use regmap_write_bits() to reduce code change.
Change from v2 to v3
- update according to mani's feedback
change from v1 to v2
- change
esume flow.
Reviewed-by: Manivannan Sadhasivam
Signed-off-by: Frank Li
---
Notes:
Change from v3 to v4
- update commit message
Add mani's review by tag
Change from v2 to v3
- fixed according to mani's feedback
1. update commit message
2. move dw_pcie_host_ops to
Add a API for dwc suspend/resume.
In layerscape platform call this api.
Frank Li (4):
PCI: layerscape: Add function pointer for exit_from_l2()
PCI: layerscape: Add suspend/resume for ls1021a
PCI: layerscape: Rename pf_* as pf_lut_*
PCI: layerscape: Add suspend/resume for ls1043a
drivers
On Thu, Nov 02, 2023 at 11:09:00PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Oct 17, 2023 at 03:31:45PM -0400, Frank Li wrote:
> > ls1043a add suspend/resume support.
> > Implement ls1043a_pcie_send_turnoff_msg() to send PME_Turn_Off message.
> > Implement ls1043a_pcie_e
On Thu, Nov 02, 2023 at 11:03:14PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Oct 17, 2023 at 03:31:44PM -0400, Frank Li wrote:
> > 'pf' and 'lut' is just difference name in difference chips, but basic it is
> > a MMIO base address plus an offset.
> >
> > Renam
On Thu, Nov 02, 2023 at 10:58:09PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Oct 17, 2023 at 03:31:43PM -0400, Frank Li wrote:
> > ls1021a add suspend/resume support.
> >
> > Implement callback ls1021a_pcie_send_turnoff_msg(), which write scfg's
> > SCFG_PEXP
On Thu, Nov 02, 2023 at 10:28:08PM +0530, Manivannan Sadhasivam wrote:
> On Tue, Oct 17, 2023 at 03:31:42PM -0400, Frank Li wrote:
> > Since difference SoCs require different sequence for exiting L2, let's add
> > a separate "exit_from_l2()" callback. This callback can b
On Tue, Oct 17, 2023 at 03:31:41PM -0400, Frank Li wrote:
> Add suspend/resume support for ls1043 and ls1021.
> Change log see each patch
>
> Frank Li (4):
> PCI: layerscape: Add function pointer for exit_from_l2()
> PCI: layerscape: Add suspend/resume for ls1021a
> PC
ls1043a add suspend/resume support.
Implement ls1043a_pcie_send_turnoff_msg() to send PME_Turn_Off message.
Implement ls1043a_pcie_exit_from_l2() to exit from L2 state.
Signed-off-by: Frank Li
---
Notes:
Change from v2 to v3
- Remove ls_pcie_lut_readl(writel) function
Change
'pf' and 'lut' is just difference name in difference chips, but basic it is
a MMIO base address plus an offset.
Rename it to avoid duplicate pf_* and lut_* in driver.
Signed-off-by: Frank Li
---
Notes:
change from v1 to v3
- new patch at v3
drivers/pci/controller/dwc/pci-layerscape.c
ls1021a add suspend/resume support.
Implement callback ls1021a_pcie_send_turnoff_msg(), which write scfg's
SCFG_PEXPMWRCR to issue PME_Turn_off message.
Implement ls1021a_pcie_exit_from_l2() to let controller exit L2 state.
Signed-off-by: Frank Li
---
Notes:
Change from v2 to v3
Since difference SoCs require different sequence for exiting L2, let's add
a separate "exit_from_l2()" callback. This callback can be used to execute
SoC specific sequence.
Signed-off-by: Frank Li
---
Notes:
Change from v2 to v3
- fixed according to mani's feedback
Add suspend/resume support for ls1043 and ls1021.
Change log see each patch
Frank Li (4):
PCI: layerscape: Add function pointer for exit_from_l2()
PCI: layerscape: Add suspend/resume for ls1021a
PCI: layerscape: Rename pf_* as pf_lut_*
PCI: layerscape: Add suspend/resume for ls1043a
On Mon, Oct 16, 2023 at 10:28:24PM +0530, Manivannan Sadhasivam wrote:
> On Fri, Sep 15, 2023 at 02:43:05PM -0400, Frank Li wrote:
> > ls1021a add suspend/resume support.
> >
>
> Please add what the driver is doing during suspend/resume.
>
> > Signed-off-by: Fran
On Mon, Oct 16, 2023 at 11:25:12AM -0500, Bjorn Helgaas wrote:
> On Mon, Oct 16, 2023 at 12:11:04PM -0400, Frank Li wrote:
> > On Mon, Oct 16, 2023 at 10:22:11AM -0500, Bjorn Helgaas wrote:
>
> > > Obviously Lorenzo *could* edit all your subject lines on your behal
ls1043a add suspend/resume support.
Signed-off-by: Frank Li
---
Notes:
Change from v1 to v2
- Change subject 'a' to 'A'
drivers/pci/controller/dwc/pci-layerscape.c | 91 -
1 file changed, 90 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci
ls1021a add suspend/resume support.
Signed-off-by: Frank Li
---
Notes:
change from v1 to v2
- change subject 'a' to 'A'
drivers/pci/controller/dwc/pci-layerscape.c | 88 -
1 file changed, 87 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci
Difference layerscape chip have not difference exit_from_l2() method.
Using function pointer for ls1028. It prepare for other layerscape
suspend/resume support.
Signed-off-by: Frank Li
---
Notes:
Change from v1 to v2
- change subject 'a' to 'A'
drivers/pci/controller/dwc/pci
On Mon, Oct 16, 2023 at 10:22:11AM -0500, Bjorn Helgaas wrote:
> On Mon, Oct 16, 2023 at 10:45:25AM -0400, Frank Li wrote:
> > On Tue, Oct 10, 2023 at 06:02:36PM +0200, Lorenzo Pieralisi wrote:
> > > On Tue, Oct 10, 2023 at 10:20:12AM -0400, Frank Li wrote:
>
> >
On Tue, Oct 10, 2023 at 06:02:36PM +0200, Lorenzo Pieralisi wrote:
> On Tue, Oct 10, 2023 at 10:20:12AM -0400, Frank Li wrote:
> > On Wed, Oct 04, 2023 at 10:23:51AM -0400, Frank Li wrote:
> > > On Fri, Sep 15, 2023 at 02:43:05PM -0400, Frank Li wrote:
> > > > ls10
On Tue, Oct 10, 2023 at 05:44:23PM +0200, Lorenzo Pieralisi wrote:
> On Tue, 26 Sep 2023 10:04:45 -0400, Frank Li wrote:
> > Set DMA mask and coherent DMA mask to enable 64-bit addressing.
> >
> >
>
> Read this:
> https://lore.kernel.org/linux-pci/2
On Wed, Oct 04, 2023 at 10:23:51AM -0400, Frank Li wrote:
> On Fri, Sep 15, 2023 at 02:43:05PM -0400, Frank Li wrote:
> > ls1021a add suspend/resume support.
> >
> > Signed-off-by: Frank Li
> > ---
>
> ping
>
> Frank
Ping
Frank
>
> >
On Wed, Sep 27, 2023 at 02:46:21PM +0200, Manivannan Sadhasivam wrote:
> On Tue, Sep 26, 2023 at 10:04:45AM -0400, Frank Li wrote:
> > From: Guanhua Gao
> >
> > Set DMA mask and coherent DMA mask to enable 64-bit addressing.
> >
> > Signed-off-by: Guanhua Gao
On Fri, Sep 15, 2023 at 02:43:05PM -0400, Frank Li wrote:
> ls1021a add suspend/resume support.
>
> Signed-off-by: Frank Li
> ---
ping
Frank
> drivers/pci/controller/dwc/pci-layerscape.c | 88 -
> 1 file changed, 87 insertions(+), 1 deletion(-)
>
&
From: Guanhua Gao
Set DMA mask and coherent DMA mask to enable 64-bit addressing.
Signed-off-by: Guanhua Gao
Signed-off-by: Hou Zhiqiang
Signed-off-by: Frank Li
---
Notes:
change from v2 to v3
- remove check return value of dma_set_mask_and_coherent. 64bit mask always
return
On Tue, Sep 26, 2023 at 12:27:32AM -0700, Christoph Hellwig wrote:
> > + /* set 64-bit DMA mask and coherent DMA mask */
> > + ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
>
> The comment is a bit silly :)
>
> > + if (ret)
> > + return ret;
>
> Also no need to check
From: Guanhua Gao
Set DMA mask and coherent DMA mask to enable 64-bit addressing.
Signed-off-by: Guanhua Gao
Signed-off-by: Hou Zhiqiang
Signed-off-by: Frank Li
---
Notes:
change from v1 to v2
- Remove 32bit DMA mask set.
drivers/pci/controller/dwc/pci-layerscape-ep.c | 5 +
1
On Thu, Sep 21, 2023 at 10:04:31PM +0200, Christophe JAILLET wrote:
> Le 21/09/2023 à 20:35, Frank Li a écrit :
> > On Thu, Sep 21, 2023 at 07:59:51PM +0200, Christophe JAILLET wrote:
> > > Le 21/09/2023 à 17:37, Frank Li a écrit :
> > > > From: Guanhua Gao
On Thu, Sep 21, 2023 at 07:59:51PM +0200, Christophe JAILLET wrote:
> Le 21/09/2023 à 17:37, Frank Li a écrit :
> > From: Guanhua Gao
> >
> > Set DMA mask and coherent DMA mask to enable 64-bit addressing.
> >
> > Signed-off-by: Guanhua Gao
> > Sign
From: Guanhua Gao
Set DMA mask and coherent DMA mask to enable 64-bit addressing.
Signed-off-by: Guanhua Gao
Signed-off-by: Hou Zhiqiang
Signed-off-by: Frank Li
---
drivers/pci/controller/dwc/pci-layerscape-ep.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/drivers/pci/controller
ls1043a add suspend/resume support.
Signed-off-by: Frank Li
---
drivers/pci/controller/dwc/pci-layerscape.c | 91 -
1 file changed, 90 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape.c
b/drivers/pci/controller/dwc/pci-layerscape.c
index
ls1021a add suspend/resume support.
Signed-off-by: Frank Li
---
drivers/pci/controller/dwc/pci-layerscape.c | 88 -
1 file changed, 87 insertions(+), 1 deletion(-)
diff --git a/drivers/pci/controller/dwc/pci-layerscape.c
b/drivers/pci/controller/dwc/pci-layerscape.c
index
Difference layerscape chip have not difference exit_from_l2() method.
Using function pointer for ls1028. It prepare for other layerscape
suspend/resume support.
Signed-off-by: Frank Li
---
drivers/pci/controller/dwc/pci-layerscape.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions
On Wed, Aug 16, 2023 at 11:53:16AM -0400, Frank Li wrote:
> On Mon, Jul 31, 2023 at 11:06:31AM -0400, Frank Li wrote:
> > On Thu, Jul 20, 2023 at 09:58:33AM -0400, Frank Li wrote:
> > > Add support to pass Link down notification to Endpoint function driver
> > > so t
On Mon, Jul 31, 2023 at 11:06:31AM -0400, Frank Li wrote:
> On Thu, Jul 20, 2023 at 09:58:33AM -0400, Frank Li wrote:
> > Add support to pass Link down notification to Endpoint function driver
> > so that the LINK_DOWN event can be processed by the function.
> >
>
On Thu, Jul 20, 2023 at 09:58:33AM -0400, Frank Li wrote:
> Add support to pass Link down notification to Endpoint function driver
> so that the LINK_DOWN event can be processed by the function.
>
> Acked-by: Manivannan Sadhasivam
> Signed-off-by: Frank Li
> ---
@Lorenzo
event.
Fixes: a805770d8a22 ("PCI: layerscape: Add EP mode support")
Acked-by: Manivannan Sadhasivam
Signed-off-by: Xiaowei Bao
Signed-off-by: Hou Zhiqiang
Signed-off-by: Frank Li
---
change from v3 to v4
- fix wrong commit a debug code, change pr_err to pr_dbg
change from v2 to v3
- f
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