https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/91965
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momchil-velikov wrote:
Rebased.
https://github.com/llvm/llvm-project/pull/91965
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https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/91965
>From b1b69ffcaf4525a66dde1ae7f1a022c85204a579 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 20 May 2024 16:25:43 +0100
Subject: [PATCH 1/2] [Clang][AArch64][SVE] Allow write to SVE vector
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/92778
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@@ -4180,8 +4180,10 @@ LValue CodeGenFunction::EmitArraySubscriptExpr(const
ArraySubscriptExpr *E,
// If the base is a vector type, then we are forming a vector element lvalue
// with this subscript.
- if (E->getBase()->getType()->isVectorType() &&
-
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/92778
None
>From 435f3104e68ef278196417c293093131258c549d Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 20 May 2024 15:43:31 +0100
Subject: [PATCH] [Clang][Sema] Refactor handling of vector
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/91965
>From 435f3104e68ef278196417c293093131258c549d Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 20 May 2024 15:43:31 +0100
Subject: [PATCH 1/3] [Clang][Sema] Refactor handling of vector
@@ -2939,59 +2922,18 @@ MachineBasicBlock
*AArch64TargetLowering::EmitInstrWithCustomInserter(
TII->get(MI.getOpcode()).TSFlags & AArch64::SMEMatrixTypeMask;
switch (SMEMatrixType) {
case (AArch64::SMEMatrixArray):
- return EmitZAInstr(SMEOrigInstr,
momchil-velikov wrote:
```
if (HasTile) {
MIB.addReg(BaseReg + MI.getOperand(0).getImm(), RegState::Define);
MIB.addReg(BaseReg + MI.getOperand(0).getImm());
StartIdx = 1;
} else
MIB.addReg(BaseReg, RegState::Define).addReg(BaseReg);
}
```
Needs extra braces
@@ -2883,19 +2883,28 @@ MachineBasicBlock
*AArch64TargetLowering::EmitZTInstr(MachineInstr ,
MachineBasicBlock *
AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg,
- MachineInstr ,
-
@@ -0,0 +1,29 @@
+// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -verify
-emit-llvm %s
momchil-velikov wrote:
Thanks!
https://github.com/llvm/llvm-project/pull/91606
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@@ -88,3 +88,13 @@ float subscript_float32(svfloat32_t a, size_t b) {
double subscript_float64(svfloat64_t a, size_t b) {
return a[b];
}
+
+// CHECK-LABEL: @subscript_write_float32(
+// CHECK-NEXT: entry:
+// CHECK-NEXT:[[VECINS:%.*]] = insertelement
[[A:%.*]], float
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/91965
>From fd4a31c1eb48db410f5445f45243dfbc1d9d22ab Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 13 May 2024 14:27:51 +0100
Subject: [PATCH 1/2] [Clang][AArch64][SVE] Allow write to SVE vector
@@ -4180,8 +4180,10 @@ LValue CodeGenFunction::EmitArraySubscriptExpr(const
ArraySubscriptExpr *E,
// If the base is a vector type, then we are forming a vector element lvalue
// with this subscript.
- if (E->getBase()->getType()->isVectorType() &&
-
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/91965
>From 2e081d74e87ad14fdf6d950d3e3da6bed07ee723 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 13 May 2024 14:27:51 +0100
Subject: [PATCH] [Clang][AArch64][SVE] Allow write to SVE vector
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/91965
The patch at https://reviews.llvm.org/D122732 introduced using the array
subscript operator for SVE vectors, however it also causes an ICE when the
subscripting expression is used as an lvalue.
This
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/91606
>From 43fb20b7492307740c437e85c3f73af068d093cf Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 9 May 2024 15:56:31 +0100
Subject: [PATCH] [AArch64] Add intrinsics for multi-vector to ZA array
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/91606
>From d3e381ac645d08b6f3b01283d47344556a163605 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Thu, 9 May 2024 15:56:31 +0100
Subject: [PATCH] [AArch64] Add intrinsics for multi-vector to ZA array
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/88105
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https://github.com/momchil-velikov commented:
LGTM, cheers!
https://github.com/llvm/llvm-project/pull/90105
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https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/88105
>From 8a63b17711d36cfeb4aab591853163119f5f167d Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 9 Apr 2024 10:52:41 +0100
Subject: [PATCH 1/4] [AArch64] Add intrinsics for non-widening
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/91606
[Recommit of e88ba6d975d887ca001cae30bfa0c53d91165148]
According to the specification in
https://github.com/ARM-software/acle/pull/309 this adds the intrinsics
void_svadd_za16_vg1x2_f16(uint32_t slice,
momchil-velikov wrote:
> Thanks for the quick revert!
>
> Is the failure due to a conflict with another commit that landed?
Perhaps, e.g. https://github.com/llvm/llvm-project/pull/91140
https://github.com/llvm/llvm-project/pull/88266
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https://github.com/llvm/llvm-project/pull/91597
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https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/91597
Reverts llvm/llvm-project#88266 due to test failures
error: 'expected-error' diagnostics seen but not expected:
(frontend): '-fsyntax-only' action ignored; '-emit-llvm' action specified
previously
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/88266
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@@ -2883,19 +2883,28 @@ MachineBasicBlock
*AArch64TargetLowering::EmitZTInstr(MachineInstr ,
MachineBasicBlock *
AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg,
- MachineInstr ,
-
@@ -2883,19 +2883,28 @@ MachineBasicBlock
*AArch64TargetLowering::EmitZTInstr(MachineInstr ,
MachineBasicBlock *
AArch64TargetLowering::EmitZAInstr(unsigned Opc, unsigned BaseReg,
- MachineInstr ,
-
@@ -2930,17 +2939,59 @@ MachineBasicBlock
*AArch64TargetLowering::EmitInstrWithCustomInserter(
TII->get(MI.getOpcode()).TSFlags & AArch64::SMEMatrixTypeMask;
switch (SMEMatrixType) {
case (AArch64::SMEMatrixArray):
- return EmitZAInstr(SMEOrigInstr,
momchil-velikov wrote:
Typo in commit message: `bflaot16`
> Variations other than bfloat16 had been already supported.
-> Variations other than bfloat16 are already supported.
https://github.com/llvm/llvm-project/pull/90105
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https://github.com/llvm/llvm-project/pull/88105
>From 74ee4857a76bc7eb5353dc22311e766ec5356514 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 9 Apr 2024 10:52:41 +0100
Subject: [PATCH 1/3] [AArch64] Add intrinsics for non-widening
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/88266
>From cafe0a8b70ad0189b638ec377e7d8cba9e786ecb Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Wed, 10 Apr 2024 11:25:50 +0100
Subject: [PATCH] [AArch64] Add intrinsics for multi-vector to ZA array
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/88105
>From 3ea7ee0aaf7f8be8c2ee42af92ba3b13b8212645 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 9 Apr 2024 10:52:41 +0100
Subject: [PATCH 1/3] [AArch64] Add intrinsics for non-widening
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/88105
>From 3ea7ee0aaf7f8be8c2ee42af92ba3b13b8212645 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 9 Apr 2024 10:52:41 +0100
Subject: [PATCH 1/2] [AArch64] Add intrinsics for non-widening
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/88266
>From 09167c5df2b50476a5073ff2e527503d090e7995 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Wed, 10 Apr 2024 11:25:50 +0100
Subject: [PATCH] [AArch64] Add intrinsics for multi-vector to ZA array
@@ -3373,7 +3373,7 @@ let TargetPrefix = "aarch64" in {
// Multi-vector min/max
//
- foreach ty = ["f", "s", "u"] in {
+ foreach ty = ["bf", "f", "s", "u"] in {
momchil-velikov wrote:
You could just omit that part. Then the `bfloat` intrinsics would
@@ -3387,7 +3387,7 @@ let TargetPrefix = "aarch64" in {
// Multi-vector floating point min/max number
//
- foreach instr = ["fmaxnm", "fminnm"] in {
+ foreach instr = ["fmaxnm", "bfmaxnm", "fminnm", "bfminnm"] in {
momchil-velikov wrote:
Likewise here.
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/88499
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@@ -104,6 +104,13 @@ class sme2_move_to_tile_pseudo
+: SMEPseudo2Instr,
momchil-velikov wrote:
This is not needed.
https://github.com/llvm/llvm-project/pull/88499
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@@ -2832,6 +2832,23 @@ AArch64TargetLowering::EmitTileLoad(unsigned Opc,
unsigned BaseReg,
return BB;
}
+MachineBasicBlock *
+AArch64TargetLowering::EmitTileMovaz(unsigned Opc, unsigned BaseReg,
momchil-velikov wrote:
This function looks almost identical
@@ -458,6 +458,40 @@ let TargetGuard = "sme2,sme-f64f64" in {
def SVMLS_LANE_VG1x4_F64 : Inst<"svmls_lane_za64[_{d}]_vg1x4", "vm4di", "d",
MergeNone, "aarch64_sme_fmls_lane_vg1x4", [IsStreaming, IsInOutZA],
[ImmCheck<3, ImmCheck0_1>]>;
}
+let TargetGuard =
@@ -1985,6 +1986,34 @@ void AArch64DAGToDAGISel::SelectMultiVectorMove(SDNode
*N, unsigned NumVecs,
CurDAG->RemoveDeadNode(N);
}
+template
+void AArch64DAGToDAGISel::SelectMultiVectorMoveZ(SDNode *N, unsigned NumVecs,
momchil-velikov wrote:
The real
@@ -286,14 +286,26 @@ multiclass sme_outer_product_fp64
def : SME_ZA_Tile_TwoPred_TwoVec_Pat;
}
-multiclass sme2p1_fmop_tile_fp16 op,
ZPRRegOp zpr_ty>{
- def NAME : sme_fp_outer_product_inst {
+multiclass sme2p1_fmop_tile_f8f16 op> {
+ def NAME :
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/88105
>From 2b0befb9078f8c9116ad52be937c8722045708ef Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 9 Apr 2024 10:52:41 +0100
Subject: [PATCH 1/2] [AArch64] Add intrinsics for non-widening
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/88553
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@@ -674,3 +674,27 @@ let TargetGuard = "sme2" in {
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
def
@@ -815,8 +815,8 @@ defm FMLS_VG4_M4Z2Z_H :
sme2_dot_mla_add_sub_array_vg4_multi<"fmls", 0b0100011,
defm FCVT_2ZZ_H : sme2p1_fp_cvt_vector_vg2_single<"fcvt", 0b0>;
defm FCVTL_2ZZ_H : sme2p1_fp_cvt_vector_vg2_single<"fcvtl", 0b1>;
-defm FMOPA_MPPZZ_H :
@@ -674,3 +674,27 @@ let TargetGuard = "sme2" in {
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
def
@@ -674,3 +674,27 @@ let TargetGuard = "sme2" in {
def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i",
"cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming,
IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>;
def
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/88105
>From 2b0befb9078f8c9116ad52be937c8722045708ef Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 9 Apr 2024 10:52:41 +0100
Subject: [PATCH] [AArch64] Add intrinsics for non-widening FMOPA/FMOPS
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/88266
According to the specification in
https://github.com/ARM-software/acle/pull/309 this adds the intrinsics
void_svadd_za16_vg1x2_f16(uint32_t slice, svfloat16x2_t zn) __arm_streaming
@@ -2148,6 +2148,11 @@ let TargetGuard = "sme2" in {
def SVSCLAMP_X4 : SInst<"svclamp[_single_{d}_x4]", "44dd", "csil",
MergeNone, "aarch64_sve_sclamp_single_x4", [IsStreaming], []>;
def SVUCLAMP_X4 : SInst<"svclamp[_single_{d}_x4]", "44dd", "UcUsUiUl",
momchil-velikov wrote:
> I noticed that file names and file location are using sme2 as prefix.
> Shouldn't we use sme2p1 prefix for this intrinsic ?
None of instructions seem to require `FEAT_SME2p1`:
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/88105
According to the specification in
https://github.com/ARM-software/acle/pull/309 this adds the intrinsics
void svmopa_za16[_f16]_m(uint64_t tile, svbool_t pn, svbool_t pm,
@@ -10007,6 +10007,16 @@ multiclass sve2p1_dupq {
bits<1> index;
let Inst{20} = index;
}
+
+ def : SVE_2_Op_Imm_Pat(NAME # _B)>;
momchil-velikov wrote:
Change them to `_timm`.
https://github.com/llvm/llvm-project/pull/83260
https://github.com/momchil-velikov approved this pull request.
https://github.com/llvm/llvm-project/pull/76844
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@@ -81,6 +81,15 @@ static bool DecodeAArch64Features(const Driver , StringRef
text,
else
return false;
+// +jsconv and +complxnum implies +neon and +fp-armv8
momchil-velikov wrote:
According to the latest Arm ARM
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/75596
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@@ -2086,7 +2086,7 @@ let TargetGuard = "sve2p1|sme2" in {
def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone,
"aarch64_sve_cntp_{d}", [IsOverloadNone, IsStreamingCompatible], [ImmCheck<1,
ImmCheck2_4_Mul2>]>;
}
-let TargetGuard = "sve2p1,b16b16" in {
@@ -2086,7 +2086,7 @@ let TargetGuard = "sve2p1|sme2" in {
def SVCNTP_COUNT : SInst<"svcntp_{d}", "n}i", "QcQsQiQl", MergeNone,
"aarch64_sve_cntp_{d}", [IsOverloadNone, IsStreamingCompatible], [ImmCheck<1,
ImmCheck2_4_Mul2>]>;
}
-let TargetGuard = "sve2p1,b16b16" in {
momchil-velikov wrote:
Rebased the clear the test run.
https://github.com/llvm/llvm-project/pull/75596
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https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75596
>From 04a03eae3fcbdd57257ce3867615ec6be9d84e53 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 15 Dec 2023 12:18:53 +
Subject: [PATCH 1/2] [AArch64] Update target feature requirements of
@@ -2066,7 +2066,7 @@ let TargetGuard = "sve2p1|sme2" in {
def SVPFALSE_COUNT_ALIAS : SInst<"svpfalse_c", "}v", "", MergeNone, "",
[IsOverloadNone, IsStreamingCompatible]>;
}
-let TargetGuard = "sve2p1,b16b16" in {
+let TargetGuard = "(sve2|sme2),b16b16" in {
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75596
>From fc5c82e61efef3f1cd2f6606b12c358637a687f5 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Fri, 15 Dec 2023 12:18:53 +
Subject: [PATCH 1/2] [AArch64] Update target feature requirements of
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/75200
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https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75200
>From d97312680eff280210f588ef22416f845d31d2ef Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 12 Dec 2023 15:08:33 +
Subject: [PATCH 1/4] [Clang][SVE2.1] Make the part of the name optional
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75117
>From 979b240d2a084eb87db43d3fabfffa8d3351d294 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 11 Dec 2023 23:25:07 +
Subject: [PATCH 1/2] [Clang][SVE2.1] Add floating-point variants of
https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/75107
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https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75200
>From bb881371fb036819a1d6489a9779e2c5ac7e7d3c Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 12 Dec 2023 15:08:33 +
Subject: [PATCH 1/4] [Clang][SVE2.1] Make the part of the name optional
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75117
>From e11897d680dbb892aa645a6fc7f63f91fde3bd7c Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 11 Dec 2023 23:25:07 +
Subject: [PATCH 1/2] [Clang][SVE2.1] Add floating-point variants of
@@ -1702,6 +1705,62 @@ void SVEEmitter::createSMERangeChecks(raw_ostream ) {
OS << "#endif\n\n";
}
+void SVEEmitter::createStreamingAttrs(raw_ostream , ACLEKind Kind) {
+ std::vector RV = Records.getAllDerivedDefinitions("Inst");
+ SmallVector, 128> Defs;
+ for (auto *R
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/75596
According to the latest update of the ISA
https://developer.arm.com/documentation/ddi0602/2023-09/?lang=en all of the
affected instruction encodings now require
(FEAT_SVE2 or FEAT_SME2) and
@@ -1,12 +1,20 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu
@@ -148,10 +151,10 @@ void test_svpmov_lane(){
svuint64_t zn_u64;
svbool_t pn;
- svpmov_lane_u8(zn_u8, -1); // expected-error {{argument value -1 is outside
the valid range [0, 0]}}
- svpmov_lane_u16(zn_u16, -1); // expected-error {{argument value -1 is
outside the
@@ -1,12 +1,20 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu
@@ -1,12 +1,20 @@
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve2p1 -S
-O1 -Werror -Wall -emit-llvm -o - %s | FileCheck %s
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu
@@ -1341,6 +1341,26 @@ def SVWHILEHS_U32 : SInst<"svwhilege_{d}[_{1}]", "Pmm",
"PUcPUsPUiPUl", MergeNon
def SVWHILEHS_U64 : SInst<"svwhilege_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl",
MergeNone, "aarch64_sve_whilehs", [IsOverloadWhile]>;
}
+let TargetGuard = "sve2p1|sme2" in {
+
@@ -1950,19 +1950,17 @@ let TargetGuard = "sve2p1|sme2" in {
//FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when
available
def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1,
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75200
>From bb881371fb036819a1d6489a9779e2c5ac7e7d3c Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 12 Dec 2023 15:08:33 +
Subject: [PATCH 1/3] [Clang][SVE2.1] Make the part of the name optional
https://github.com/momchil-velikov edited
https://github.com/llvm/llvm-project/pull/75200
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@@ -1950,19 +1950,17 @@ let TargetGuard = "sve2p1|sme2" in {
//FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when
available
def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1,
@@ -1950,19 +1950,17 @@ let TargetGuard = "sve2p1|sme2" in {
//FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when
available
def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1,
@@ -1950,19 +1950,17 @@ let TargetGuard = "sve2p1|sme2" in {
//FIXME: Replace IsStreamingCompatible with IsStreamingOrHasSVE2p1 when
available
def SVPEXT_SINGLE : SInst<"svpext_lane_{d}", "P}i", "QcQsQiQl", MergeNone,
"aarch64_sve_pext", [IsStreamingCompatible], [ImmCheck<1,
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75200
>From bb881371fb036819a1d6489a9779e2c5ac7e7d3c Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 12 Dec 2023 15:08:33 +
Subject: [PATCH 1/2] [Clang][SVE2.1] Make the part of the name optional
https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/75200
>From bb881371fb036819a1d6489a9779e2c5ac7e7d3c Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 12 Dec 2023 15:08:33 +
Subject: [PATCH] [Clang][SVE2.1] Make the part of the name optional for
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/75200
The `_s64`/`_u64` part can be omitted now. It's inferred from the argument
types.
>From 1cab2e8cfb0427e5d97e0f306460d1d83123d78b Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Tue, 12 Dec 2023
@@ -1341,6 +1341,26 @@ def SVWHILEHS_U32 : SInst<"svwhilege_{d}[_{1}]", "Pmm",
"PUcPUsPUiPUl", MergeNon
def SVWHILEHS_U64 : SInst<"svwhilege_{d}[_{1}]", "Pnn", "PUcPUsPUiPUl",
MergeNone, "aarch64_sve_whilehs", [IsOverloadWhile]>;
}
+let TargetGuard = "sve2p1|sme2" in {
https://github.com/momchil-velikov created
https://github.com/llvm/llvm-project/pull/75117
None
>From 4fe606a2cf764ae4281789727d241c91c3cb9c39 Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Mon, 11 Dec 2023 23:25:07 +
Subject: [PATCH] [Clang][SVE2.1] Add floating-point variants of
momchil-velikov wrote:
I thought the suggestion was to add a few lines to
https://github.com/llvm/llvm-project/blob/main/clang/docs/ReleaseNotes.rst
https://github.com/llvm/llvm-project/pull/73326
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https://github.com/momchil-velikov closed
https://github.com/llvm/llvm-project/pull/70565
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https://github.com/momchil-velikov updated
https://github.com/llvm/llvm-project/pull/70565
>From 66a84fffb5d1b5c34eea9ecdb83a88afb0b627ff Mon Sep 17 00:00:00 2001
From: Momchil Velikov
Date: Sat, 28 Oct 2023 15:01:36 +0100
Subject: [PATCH 1/4] [Verifier] Check function attributes related to
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