Re: [PATCH V2] Middle-end: Change order of LEN_MASK_LOAD/LEN_MASK_STORE arguments

> Similar to LEN_MASK_LOAD/STORE, their orders are consistent now after > this patch. Ah right, apologies. Regards Robin

Re: [PATCH V2] Middle-end: Change order of LEN_MASK_LOAD/LEN_MASK_STORE arguments

Hi Juzhe, when changing the argument order for LEN_LOAD/LEN_STORE, you will also need to adjust rs6000's and s390's expanders. Regards Robin

Re: [PATCH 2/2] ifcvt: Allow more operations in multiple set if conversion

Hi Manolis, that looks like a nice enhancement of what's already possible. The concern I had some years back already was that this function would eventually grow and cannibalize on some of what the other functions in ifcvt already do :) At some point we really should unify but that's not within

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

On 7/3/23 10:45, juzhe.zh...@rivai.ai wrote: > We can apply it but not sure why the patchwork shows it's rejected. I believe it also failed for me locally because the order of patterns in autovec-opt.md was somehow different. The one attached worked for me though after some minor merge

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

> We failed to merge it since it's been rejected. > https://patchwork.sourceware.org/project/gcc/patch/20230628041512.188243-1-juzhe.zh...@rivai.ai/ > > >   Err, who rejected? Or is this about

Re: [PATCH v1] RISC-V: Fix one typo of FRM dynamic definition

> Thanks for fixing it. LGTM. > I think you can merge it when Robin is ok since this is a simple typo > fix. Yes, that's definitely simple enough :) Regards Robin

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

> Thanks. Ok for trunk？ OK from my side. As agreed with Jeff, I'm going to get back to this and revisit/change if needed in the future. Regards Robin

Re: [PATCH] RISC-V: Support vfwnmacc/vfwmsac/vfwnmsac combine lowering

To reiterate, this is OK from my side. As discussed in the other thread, Jeff would like to have more info on whether a bridge pattern is needed at all and I agreed to get back to it in a while. Until then, we can merge this. Regards Robin

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

> There has to be some kind of mismatch between the patch or testcase > or what we're looking at to judge success. Yeah I think the initially posted example was misleading because it contained an already working example. > While I really don't see the need to have the bridge pattern, I'm > still

Re: [PATCH] RISC-V: Support vfwmul.vv combine lowering

> The explicit conversions I see are because we need the output of the > conversion in multiple vfmul instructions. That won't be helped by > the patch you've proposed. FWIW on my local branch and the patch applied I see that the vfwmuls are being generated (all of the vfmuls are replaced). >

Re: [PATCH V2] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern

> I am not sure why you mention 'len' in bytes. The 'trick' for then len_load/len_store patterns is to allow a QImode/byte-only length rather than elements. Regards Robin

Re: [PATCH] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern

> I personally prefer **NOT** to include BIAS in the gather/scatter > since I don't known how it will be used. It was not my intention to suggest to add BIAS here. This can be done by the respective targets when/if they support mask_*, not by you. What I meant is that I'm unsure whether to add

Re: [PATCH] Machine Description: Add LEN_MASK_{GATHER_LOAD, SCATTER_STORE} pattern

Hi Juzhe, just looking at the documentation changes. > +@cindex @code{len_mask_gather_load@var{m}@var{n}} instruction pattern > +@item @samp{len_mask_gather_load@var{m}@var{n}} > +Like @samp{gather_load@var{m}@var{n}}, but takes an extra len operand > +as operand 5 and an extra mask operand as

Re: [PATCH V3] RISC-V: Fix bug of pre-calculated const vector mask for VNx1BI, VNx2BI and VNx4BI

>> Hi Robin: >> >>> diff --git a/gcc/lto/lto-lang.cc b/gcc/lto/lto-lang.cc >>> index 52d7626e92e..14d419c2013 100644 >>> --- a/gcc/lto/lto-lang.cc >>> +++ b/gcc/lto/lto-lang.cc >>> @@ -1050,7 +1050,7 @@ lto_type_for_mode (machine_mode mode, int unsigned_p) >>>else if (GET_MODE_CLASS (mode) ==

Re: [PATCH V3] RISC-V: Fix bug of pre-calculated const vector mask for VNx1BI, VNx2BI and VNx4BI

to take a while, various aarch compile farm machines are down? Regards Robin >From ef919a27f4a156afeca6b4825e6029d9f44be556 Mon Sep 17 00:00:00 2001 From: Robin Dapp Date: Wed, 28 Jun 2023 20:59:29 +0200 Subject: [PATCH] mode_bitsize -> precision. bitsize -> precision. --- gcc/c-fami

Re: [PATCH] Prevent TYPE_PRECISION on VECTOR_TYPEs

>> Since nobody else has provided a patch yet, is the attached OK as long >> as x86 bootstrap and testsuite are clean? > > Yes. Bootstrap and testsuite are good. Going to commit. Thanks. Regards Robin

Re: [PATCH] Prevent TYPE_PRECISION on VECTOR_TYPEs

Ah, the one sub-thread continued before you were CC'ed. Sorry about that. Regards Robin

Re: [PATCH] Prevent TYPE_PRECISION on VECTOR_TYPEs

> Currently, I have no ideal how to walk around this ICE in RISC-V port. > Do you have any suggestions? I'm already bootstrapping this patch: https://gcc.gnu.org/pipermail/gcc-patches/2023-June/623184.html I replied to all but it seems you got lost in the thread? Regards Robin

Re: [PATCH] Prevent TYPE_PRECISION on VECTOR_TYPEs

rovided a patch yet, is the attached OK as long as x86 bootstrap and testsuite are clean? Regards Robin >From 5ac3bb96cae0af99cefeaa225806de67e268e8f5 Mon Sep 17 00:00:00 2001 From: Robin Dapp Date: Thu, 29 Jun 2023 11:35:02 +0200 Subject: [PATCH] ssa-math-opts: Use element_precision. The rec

Re: [PATCH V3] RISC-V: Fix bug of pre-calculated const vector mask for VNx1BI, VNx2BI and VNx4BI

> Yeah, that part is OK, and was the case I was thinking about when > I said OK yesterday. But now that we allow BITSIZE != PRECISION, > it's possible for BITSIZE - PRECISION to be more than a full byte, > in which case the new loop would not initialise every byte of > the mode. Ah, I see, so

Re: [PATCH V3] RISC-V: Fix bug of pre-calculated const vector mask for VNx1BI, VNx2BI and VNx4BI

>>> are we absolutely sure this is the only problem we will have >>> with precision != bitsize and it is confined to the backend? > Yes. With vinfo.vector_mode == VNx4SI mask_type = get_mask_type_for_scalar_type (vinfo, int) mask_type is: vector(4) I.e. the precision is 2. This is definitely

Re: [PATCH V3] RISC-V: Fix bug of pre-calculated const vector mask for VNx1BI, VNx2BI and VNx4BI

I grep'ed a bit and found several more instances of the same pattern which would probably all have to be adjusted (frontend-related mostly but also in native_encode_rtx). Most likely they would all have to be adjusted? > Sorry, only realised later, but: if the precision can cover fewer > bytes

Re: [PATCH V3] RISC-V: Fix bug of pre-calculated const vector mask for VNx1BI, VNx2BI and VNx4BI

Hi Juzhe, I find the bug description rather confusing. What I can see is that the constant in the literal pool is indeed wrong but how would DSE or so play a role there? Particularly only for the smaller modes? My suspicion would be that the constant in the literal/constant pool is wrong from

Re: [PATCH] match.pd: Use element_mode instead of TYPE_MODE.

> You can put it into the original one. Bootstrap and testsuite run were successful. I'm going to push the attached, thanks. Regards Robin diff --git a/gcc/match.pd b/gcc/match.pd index 33ccda3e7b6..83bcefa914b 100644 --- a/gcc/match.pd +++ b/gcc/match.pd @@ -7454,10 +7454,12 @@

Re: [PATCH] match.pd: Use element_mode instead of TYPE_MODE.

> so I suggest to do a similar VECTOR_MODE_P check and your original test. > So > > && (!VECTOR_MODE_P (TYPE_MODE (newtype)) > || target_supports_op_p (newtype, op, optab_default)) > > OK with that change. Separate patch or into the original one? We needed element_mode because

Re: [PATCH] match.pd: Use element_mode instead of TYPE_MODE.

> Yeah, the optab should already have the fallback of WIDENing here? > So why does that fail? We reach if (CLASS_HAS_WIDER_MODES_P (mclass)) which returns false because mclass == MODE_VECTOR_FLOAT. CLASS_HAS_WIDER_MODES_P only handles non-vector classes? Same for FOR_EACH_WIDER_MODE that

Re: [PATCH] match.pd: Use element_mode instead of TYPE_MODE.

> Why does the expander not have a fallback here? If we put up > restrictions like this like we do for vector operations (after > vector lowering!), we need to document this. Your check covers > more than just FP16 types as well which I think is undesirable. I'm not sure I follow. What would

Re: [PATCH] match.pd: Use element_mode instead of TYPE_MODE.

> Can you push the element_mode change separately please? OK. > I'd like to hear more reasoning of why target_supports_op_p is wanted > here. Doesn't target_supports_op_p return false if this is for example > a soft-fp target? So if at all, shouldn't the test only be carried > out if the

[PATCH] RISC-V: Add autovect widening/narrowing Integer/FP conversions.

Hi, this patch implements widening and narrowing float-to-int and int-to-float autovec conversions and adds tests. Regards Robin gcc/ChangeLog: * config/riscv/autovec.md (2): New expander. (2): Dito. (2): Dito. (2): Dito. *

[PATCH] RISC-V: Add autovec FP widening/narrowing.

Hi, this patch adds FP widening and narrowing autovec expanders as well as tests. Conceptually similar to integer extension/truncation, we emulate _Float16 -> double by two vfwcvts and double -> _Float16 by two vfncvts. Optimizations to create widening operations will be added separately.

[PATCH] RISC-V: Add autovec FP int->float conversion.

Hi, this patch adds the autovec expander for vfcvt.f.x.v and tests for it. In addition, it modifies the zfhmin-1 test so it doesn't scan for "no vectorization" but rather check that we do not emit any (RTL) vector operations (other than float/float conversions) with a VNx..HFmode. Regards Robin

[PATCH] match.pd: Use element_mode instead of TYPE_MODE.

Hi, this patch changes TYPE_MODE into element_mode in a match.pd simplification. As the simplification can be called with vector types real_can_shorten_arithmetic would ICE in REAL_MODE_FORMAT which expects a scalar mode. Therefore, use element_mode instead of TYPE_MODE. Additionally, check if

Re: [PATCH] RISC-V: Enhance RVV VLA SLP auto-vectorization

Hi Juzhe, > Currently, we are able to generate step vector with base == 0: > { 0, 0, 2, 2, 4, 4, ... } > > ASM: > > vid > vand > > However, we do wrong for step vector with base != 0: > { 1, 1, 3, 3, 5, 5, ... } > > Before this patch, such case will run fail. > > After this patch, we are

Re: [PATCH] RISC-V: Split VF iterators for Zvfh(min).

> Just curious about the combine pass you mentioned, not very sure my > understand is correct but it looks like the combine pass totally > ignore the iterator requirement? > > It is sort of surprise to me as the combine pass may also need the > information of iterators. combine tries to match

Re: [PATCH] RISC-V: Split VF iterators for Zvfh(min).

> I don't understand why it is necessary to bother "VF". "VF” should > not be changed since intrinsic stuff is quite stable and any > unreasonable changes are unacceptable. Ok, I hear your concern. My argument is: Currently our mechanism of disabling instructions is incorrect and if any of the

Re: [PATCH] RISC-V: Split VF iterators for Zvfh(min).

> You change "VF" constraint as "TARGET_ZVFH" which is incorrect since > we a lot of instructions are valid in "TARGET_ZVFHMIN" in vector.md > but you disabled them in this patch. You disabled them unexpectedly. Yes that was kind of the point :) IMHO all the :VF insns are actually only valid in

[PATCH] RISC-V: Split VF iterators for Zvfh(min).

Hi, when working on FP widening/narrowing I realized the Zvfhmin handling is not ideal right now: We use the "enabled" insn attribute to disable instructions not available with Zvfhmin (but only with Zvfh). However, "enabled == 0" only disables insn alternatives, in our case all of them when

Re: LTO: buffer overflow in lto_output_init_mode_table

Hi Jivan, I think Pan is already on this problem. Please see this thread: https://gcc.gnu.org/pipermail/gcc-patches/2023-June/622129.html Regards Robin

[PATCH v2] RISC-V: Implement autovec copysign.

Hi, changes from v1: - Removed UNSPEC_VNCOPYSIGN - Adjusted xorsign test expectation. Regards Robin This adds vector copysign, ncopysign and xorsign as well as the accompanying tests. gcc/ChangeLog: * config/riscv/autovec.md (copysign3): Add expander. (xorsign3): Dito.

Re: [PATCH] RISC-V: Support RVV floating-point ternary auto-vectorization

Hi Juzhe, LGTM apart from a tiny nit: > + /* We have a maximum of 11 operands for RVV instruction patterns according > to > + * vector.md. */ > + insn_expander<11> e (/*OP_NUM*/ op_num, /*HAS_DEST_P*/ true, Seems like you copied this from the non-fp ternary part but the rest of the file

Re: [PATCH] RISC-V: Implement autovec copysign.

> You should remove all "unspec" related of "n" ncopysign including  > riscv-vector-builtins-bases.cc > vector.md/ vector-iterators.md  Ah, there was indeed one stray UNSPEC_VNCOPYSIGN in the iterators, thanks. Any other comments before I sent V2? Regards Robin

Re: [PATCH] RISC-V: convert the mulh with 0 to mov 0 to the reg.

Hi Yanzhang, while I appreciate the optimization, I'm a bit wary about just adding a special case for "0". Is that so common? Wouldn't we also like to have * pow2_p (val) == << val and others? * 1 should also be covered. Regards Robin

Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

Hi, I'm going to commit the attached. Thanks Lehua for reporting. Regards Robin >From 1a4dfe90f251e38e27104f2fa11feecd3b04c4c1 Mon Sep 17 00:00:00 2001 From: Robin Dapp Date: Tue, 20 Jun 2023 15:52:16 +0200 Subject: [PATCH] RISC-V: testsuite: Add missing -mabi=lp64d. This fixes more ca

Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

> By the way, shouldn't these cases have the `-mabi=lp64d` option added, > otherwise I get the following failure message when I run tests on RV32 GCC. > >   FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/vec_set-1.c -std=c99 -O3 > -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test

Re: [PATCH] RISC-V: Fix compiler warning of riscv_arg_has_vector

> Could you merge it ? Committed. Regards Robin

Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

in for a bit :) 51795b910737 (Robin Dapp 2023-06-01 14:18:57 +0200 1) /* { dg-do compile } */ I thought something is special about them that they somehow didn't run on your machine or so. But no need for a new patch, thanks. I already have it and will commit it soon. Regards Robin

[PATCH] RISC-V: Implement autovec copysign.

Hi, this adds vector copysign, ncopysign and xorsign as well as the accompanying tests. In order to easily match the ncopysign patterns I changed the builtin implementation slightly. Juzhe might want to comment on that. For now I kept the attribute's name even though it doesn't emit an "n"

Re: [PATCH] RISC-V: Fix vmul test expectation.

I just noticed there is also a -ffast-math missing in vadd-run.c as well as one redundant in vrem-rv32gcv.c and added it to the patch. Going to commit the attached as obvious. Regards Robin Subject: [PATCH] RISC-V: testsuite: Fix vmul test expectation and fix -ffast-math. I forgot to check

Re: [PATCH] RISC-V: Add tuple vector mode psABI checking and simplify code

> Committed, thanks Jeff. The vec_set/vec_extract tests FAIL since this commit. I'm going to commit the attached as obvious. Lehua, would they not show up in your test runs? You fixed several other tests but these somehow not? Regards Robin Subject: [PATCH] RISC-V: testsuite: Add -Wno-psabi

Re: [PATCH] RISC-V: Fix compiler warning of riscv_arg_has_vector

> Could you merge it ? > By the way, could Lehua get the write access? IMHO nothing stands in the way but I'll defer to Jeff to have the "official seal" :) Once he ACKs Lehua needs to go the usual way of requesting sourceware access via https://sourceware.org/cgi-bin/pdw/ps_form.cgi. Regards

Re: [PATCH] RISC-V: Fix compiler warning of riscv_arg_has_vector

> This little patch fixes a compile warning issue that my previous > patch introduced, sorry for introducing this issue. OK and obvious enough to push directly. Regards Robin

Re: [PATCH V3] RISC-V: Optimize codegen of VLA SLP

LGTM. Regards Robin

Re: [PATCH] RISC-V: Optimize codegen of VLA SLP

> Ok. Just sent V2. I will adjust comment and send V3 again :) Sorry, was too slow. Regards Robin

Re: [PATCH] RISC-V: Optimize codegen of VLA SLP

> + /* Step 2: VID AND -NPATTERNS: > + { 0&-4, 1&-4, 2&-4, 3 &-4, 4 &-4, 5 &-4, 6 &-4, 7 &-4, ... } > + */ Before that, just add something simple like: We want to create a pattern where value[ix] = floor (ix / NPATTERNS). As NPATTERNS is always a power of two we

Re: [PATCH] RISC-V: Optimize codegen of VLA SLP

> This is a nice improvement. Even though we're in the SLP realm I would > still add an assert that documents that we're indeed operating with > pow2_p (NPATTERNS) and some comment as to why we can use AND. > Sure we're doing exact_log2 et al later anyway, just to make things > clearer. Actually

[PATCH] RISC-V: Fix vmul test expectation.

Hi, I forgot to check for vfmul in the multiplication tests. Fix this. Regards Robin gcc/testsuite/ChangeLog: * gcc.target/riscv/rvv/autovec/binop/vmul-rv32gcv.c: Check for vfmul. * gcc.target/riscv/rvv/autovec/binop/vmul-rv64gcv.c: Dito. ---

Re: [PATCH] RISC-V: Optimize codegen of VLA SLP

Hi Juzhe, > Case 1: > void > f (uint8_t *restrict a, uint8_t *restrict b) > { > for (int i = 0; i < 100; ++i) > { > a[i * 8] = b[i * 8 + 37] + 1; > a[i * 8 + 1] = b[i * 8 + 37] + 2; > a[i * 8 + 2] = b[i * 8 + 37] + 3; > a[i * 8 + 3] = b[i * 8 + 37] + 4; > a[i *

Re: [PATCH V7] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs

>> Bootstrap and Regreesion on X86 passed. >> Jeff and Richi approved. >> >> Let's wait for Richard S final approve. > > No need to wait. Thanks, I pushed it in Juzhe's stead, fixing the LEN_LOAD/LEN_STORE documentation (+ vs -) as r14-1932. Regards Robin

Re: [PATCH V6] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs

>>>If the pattern is not allowed to fail, then what code enforces the bias >>>argument's restrictions?  I don't see it in the generic expander code. > > I have no ideal since this is just copied from len_load/len_store which is  > s390 target dependent stuff.  > > I have sent V7 patch with

[PATCH v2] RISC-V: Implement vec_set and vec_extract.

Hi, with the recent changes that we also pass the return value via stack this is can go forward now. Changes in V2: - Remove redundant force_reg. - Change target selectors to those introduced in the binop patch. Regards Robin This implements the vec_set and vec_extract patterns for integer

[PATCH v3] RISC-V: Add autovec FP unary operations.

Hi, changes from V2: - No longer dependent on testsuite changes. - Add zvfhmin-1.c unary test cases. Regards Robin This patch adds floating-point autovec expanders for vfneg, vfabs as well as vfsqrt and the accompanying tests. Similary to the binop tests, there are flavors for zvfh now.

[PATCH v3] RISC-V: Add autovec FP binary operations.

Hi, changes in v3: - No longer "dependent" on testsuite changes. Just the zvfh run testcases use riscv_zvfh_hw, i.e. require that we can compile, link the code as well as execute the resulting binary. - Renamed rounding modes (floating_point_rounding_mode feels a bit long-winded but well...)

Re: [PATCH v2] RISC-V: Add autovec FP binary operations.

> Why do we need '-ffast-math' with the tests? Normally we would use the COND_ADD to mask out possibly trapping vector elements and the likes but COND_ADD works with normal vector masking. What we currently have is no masking but the LEN_LOAD/LEN_STORE machinery i.e. length-controlled loops.

Re: [PATCH v1] RISC-V: Fix one warning of maybe-uninitialized in riscv-vsetvl.cc

> This patch would like to fix one maybe-uninitialized warning. Aka: > > riscv-vsetvl.cc:4354:3: error: 'vsetvl_rinsn' may be used uninitialized > [-Werror=maybe-uninitialized] > > Signed-off-by: Pan Li IMHO obvious enough that it doesn't need a maintainer's OK, so go ahead. We should make

Re: [PATCH V4] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs

> <= (operand 2 + operand 4) are used." Sorry it's really minor (and my mistake) but it should be < and not <=, right? Mask index 0 is inactive when the length is 0. > +Perform a masked store (operand 2 + operand 4) Even more minor but as mentioned the "of" is still missing ;) Same with

Re: [PATCH V4] VECT: Support LEN_MASK_{LOAD,STORE} ifn && optabs

Hi Juzhe, > +@cindex @code{len_maskload@var{m}@var{n}} instruction pattern > +@item @samp{len_maskload@var{m}@var{n}} > +Perform a masked load (operand 2 - operand 4) elements from vector memory > +operand 1 into vector register operand 0, setting the other elements of > +operand 0 to undefined

Re: [PATCH v2] RISC-V: Add autovec FP binary operations.

Yes, already did that and will send next version soon. Just still looking at a lot of test failures with -march=rv64gc_zvfhmin (note, no rv64gcv) that are somewhat independent of this patch. Regards Robin

[PATCH v2] RISC-V: Add autovec FP unary operations.

Hi, changes from V1: - Use VF_AUTO iterator. - Don't mention vfsqrt7. This patch adds floating-point autovec expanders for vfneg, vfabs as well as vfsqrt and the accompanying tests. Similary to the binop tests, there are flavors for zvfh now. gcc/ChangeLog: *

[PATCH v2] RISC-V: Add autovec FP binary operations.

Hi, changes from V1: - Add VF_AUTO iterator and use it. - Ensured we don't ICE with -march=rv64gcv_zfhmin. this implements the floating-point autovec expanders for binary operations: vfadd, vfsub, vfdiv, vfmul, vfmax, vfmin and adds tests. The existing tests are split up into non-_Float16 and

[PATCH v2] RISC-V: testsuite: Add vector_hw and zvfh_hw checks.

Hi, Changes from v1: - Revamped the target selectors again. - Fixed some syntax as well as caching errors that were still present. - Adjusted some test cases I missed. The current situation with target selectors is improvable at best. We definitely need to discern between being able to build

Re: [PATCH] RISC-V: Add autovec FP unary operations.

> Btw. I'm currently running the testsuite with rv64gcv_zfhmin > default march and see some additional FAILs. Will report back. Reporting back - the FAILs are a combination of an older qemu version and not fully comprehensive target selectors. I'm going to send a V2 for the testsuite patch as

Re: [PATCH V2] VECT: Support LEN_MASK_ LOAD/STORE to support flow control for length loop control

> the minus in 'operand 2 - operand 3' should be a plus if the > bias is really zero or -1. I suppose Yes, that somehow got lost from when the bias was still +1. Maybe Juzhe can fix this in the course of his patch. > that's quite conservative. I think you can do better when the > loads are

Re: [PATCH V2] VECT: Support LEN_MASK_ LOAD/STORE to support flow control for length loop control

On 6/15/23 11:18, Robin Dapp wrote: >> Meh, PoP is now behind a paywall, trying to get through ... I wonder >> if there's a nice online html documenting the s390 len_load/store >> instructions to better understand the need for the bias. This is z16, but obviously no changes f

Re: [PATCH V2] VECT: Support LEN_MASK_ LOAD/STORE to support flow control for length loop control

> Meh, PoP is now behind a paywall, trying to get through ... I wonder > if there's a nice online html documenting the s390 len_load/store > instructions to better understand the need for the bias. https://publibfp.dhe.ibm.com/epubs/pdf/a227832c.pdf Look for vector load with length (store). The

Re: [PATCH V2] VECT: Support LEN_MASK_ LOAD/STORE to support flow control for length loop control

>>> Can you try using the same wording for length and mask operands >>> as for len_load and maskload? Also len_load has the "bias" >>> operand which you omit here - IIRC that was added for s390 which >>> for unknown reason behaves a little different than power. If >>> len support for s390 ever

Re: [PATCH] RISC-V: Add autovec FP unary operations.

Hi Juzhe, I like the iterator solution better, I added it to the binops V2 patch with a comment and will post it in a while. Also realized there is already a testcase and the "enabled" attribute is set properly now but I hadn't rebased to the current master branch in a while... Btw. I'm

[PATCH] RISC-V: Add autovec FP unary operations.

Hi, this patch adds floating-point autovec expanders for vfneg, vfabs as well as vfsqrt and the accompanying tests. vfrsqrt7 will be added at a later time. Similary to the binop tests, there are flavors for zvfh now. Prerequisites as before. Regards Robin gcc/ChangeLog: *

[PATCH] RISC-V: Add autovec FP binary operations.

Hi, this implements the floating-point autovec expanders for binary operations: vfadd, vfsub, vfdiv, vfmul, vfmax, vfmin and adds tests. The existing tests are amended and split up into non-_Float16 and _Float16 flavors as we cannot rely on the zvfh extension being present. As long as we do not

Re: [PATCH] RISC-V: Use merge approach to optimize vector permutation

Hi Juzhe, the general method seems sane and useful (it's not very complicated). I was just distracted by > Selector = { 0, 17, 2, 19, 4, 21, 6, 23, 8, 9, 10, 27, 12, 29, 14, 31 }, the > common expression: > { 0, nunits + 1, 1, nunits + 2, 2, nunits + 3, ... } > > For this selector, we can use

[PATCH] RISC-V: testsuite: Add vector_hw and zvfh_hw checks.

Hi, this introduces new checks for run tests. Currently we have riscv_vector as well as rv32 and rv64 which all check if GCC (with the current configuration) can build (not execute) the respective tests. Many tests specify e.g. a different -march for vector, though. So the check fails even

Re: [PATCH V2] RISC-V: Ensure vector args and return use function stack to pass [PR110119]

> Oh. I see Robin's email is also wrong. CC Robin too for you  It still arrived via the mailing list ;) > Good to see a Fix patch of the ICE before Vector ABI patch. > Let's wait for more comments. LGTM, this way I don't even need to rewrite my tests. Regards Robin

Re: [PATCH] RISC-V: Ensure vector args and return use function stack to pass [PR110119]

Hi, > Thanks for fixing this. > > This patch let RVV type (both vector and tuple) return in memory by > default when there is no vector ABI support. It makes sens to me. > > CC more RISC-V folks to comments. so this is intended to fix the PR as well as unblock while we continue with the

Re: [PATCH v2] RISC-V: Bugfix for vec_init repeating auto vectorization in RV32

Hi Pan, > This patch would like to fix one bug exported by RV32 test case > multiple_rgroup_run-2.c. The mask should be restricted by elen in > vector, and the condition between the vmv.s.x and the vmv.v.x should > take inner_bits_size rather than constants. exported -> exposed. How about

[PATCH] RISC-V: Add (u)int8_t to binop tests.

Hi, this patch adds the missing (u)int8_t types to the binop tests. I suggest in the future we have the testsuite pass -march=rv32gcv as well as -march=rv64gcv as options to each test case instead of essentially duplicate the files as we do now. Regards Robin gcc/testsuite/ChangeLog:

Re: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split

> I am not sure. These testcases were added by kito long time ago. > Frankly, I am not familiar with GCC test framework. Ok, I'm going to have a look. Need to verify the zvfh things anyway. Regards Robin

Re: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split

Yes, I agree with the general assessment (and didn't mean to insinuate that the FAILs are compiler's or a fault of the patch. > So these 2 failures in RV32 are not the compile's bugs. I have seen: > /* { dg-do run { target { { {riscv_vector} && {rv64} } } } } */ in > these testcases which can not

Re: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split

> I don't have a proper sim environment setup yet.  How long does the > testsuite take > with spike?  Have you tried qemu as well? Any numbers on this Pan? How many cores do you use for running the testsuite? Regards Robin

Re: [PATCH v1] RISC-V: Align the predictor style for define_insn_and_split

Hi Pan, these failures were present before the patch I suppose? They don't look related. Is this what you meant by "the same as upstream"? > FAIL: gcc.target/riscv/rvv/autovec/vls-vlmax/full-vec-move1.c -std=c99 -O3 > -ftree-vectorize --param riscv-autovec-preference=fixed-vlmax (test for >

Re: [PATCH] RISC-V: Fix bug of VLA SLP auto-vectorization

Hi Juzhe, LGTM. You could also add the aarch64 test disclaimer here again, but no need for a V2. Regards Robin

Re: [PATCH V3] RISC-V: Add more SLP tests

Hi Juzhe, thanks, works for me as is. I just hope somebody is going to take on the task of making different LMUL SLP variants "scannable" at some point because it would definitely increase our test coverage with these tests. (Or split the tests manually and not iterate over LMUL) Regards Robin

Re: [PATCH] RISC-V: Add more SLP tests

Hi Juzhe, as the tests are mostly directly from aarch64's testsuite I would advise comments on where they were taken from as well as a TODO that they should become common tests for a specific target selector (vect_scalable_supported or something). How about some assembly checks for the non-run

Re: [PATCH v1] RISC-V: Fix one typo in full-vec-movel test

> Oh. Sorry. Since I want to commit my patch so I asked Pan to commit > your test as well. I think you can resend a fix of this testcase and > drop this patch. No problem, will fix it another time. Pan can just go ahead with this fix now, no need to wait for a maintainer, it's obvious enough.

Re: [PATCH v1] RISC-V: Fix one typo in full-vec-movel test

> This patch would like to fix one typo when checking assembly of > full-vec-movel. OK. (I actually intended to commit this myself adding some more comments to the iterator change as well as fix the tests, but well...) Regards Robin

Re: [PATCH] RISC-V: Implement vec_set and vec_extract.

> I suggest we implement vector calling convention even though it is not > ratified yet. > We can allow calling convention to be enabled only when > --param=riscv-autovec-preference=fixed-vlmax. > We have such issue: > https://gcc.gnu.org/bugzilla/show_bug.cgi?id=110119 >

Re: [PATCH] RISC-V: Implement vec_set and vec_extract.

> +  /* If the slide offset fits into 5 bits we can > + use the immediate variant instead of the register variant. > + The expander's operand[2] is ops[3] here. */ > +  if (!satisfies_constraint_K (ops[3])) > +    ops[3] = force_reg (Pmode, ops[3]); > > I don't think we need this.

Re: [PATCH] RISC-V: Add sign-extending variants for vmv.x.s.

> Change  > > +(define_insn "@pred_extract_first_sextdi" > > into  > > (define_insn "*pred_extract_first_sextdi" Yeah, I was thinking about this as well right after sending. We will probably never call this directly. Regards Robin

[PATCH] RISC-V: Add sign-extending variants for vmv.x.s.

Hi, when the destination register of a vmv.x.s needs to be sign extended to XLEN we currently emit an sext insn. Since vmv.x.s performs this implicitly this patch adds two instruction patterns (intended for combine et al.) that include sign_extend for the destination operand. The tests extend

[PATCH] RISC-V: Implement vec_set and vec_extract.

Hi, this implements the vec_set and vec_extract patterns for integer and floating-point data types. For vec_set we broadcast the insert value to a vector register and then perform a vslideup with effective length 1 to the requested index. vec_extract is done by sliding down the requested

Re: [PATCH] RISC-V: Enhance RVV VLA SLP auto-vectorization with decompress operation

Hi Juzhe, seems a nice improvement, looks good to me. While reading I was wondering if vzext could help synthesize some (zero-based) patterns as well (e.g. 0 3 0 3...). However the sequences I could come up with were not shorter than what we are already emitting, so probably not. Regards Robin

Re: [PATCH] RISC-V: Fix V_WHOLE && V_FRACT iterator requirement

> +  (VNx16QI "TARGET_MIN_VLEN <= 128") > +  (VNx32QI "TARGET_MIN_VLEN <= 256") > +  (VNx64QI "TARGET_MIN_VLEN >= 64 && TARGET_MIN_VLEN <= 512") > +  (VNx128QI "TARGET_MIN_VLEN >= 128 && TARGET_MIN_VLEN <= 1024") > > This not correct, we always use VNx16QI as LMUL = m1 for min_vlen >= 128. >

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