dtcxzyw wrote:
My CI detected some significant regressions caused by this patch:
https://github.com/dtcxzyw/llvm-ci/pull/839#issuecomment-1836976355
https://github.com/llvm/llvm-project/pull/73662
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https://github.com/dtcxzyw approved this pull request.
The implementation looks good to me. Waiting for the result of my CI.
https://github.com/dtcxzyw/llvm-ci/actions/runs/7066692655
@goldsteinn Any comments?
https://github.com/llvm/llvm-project/pull/73662
@@ -75,7 +75,8 @@ define void @idom_sign_bit_check_edge_dominates_select(i64
%a, i64 %b) {
; CHECK: land.lhs.true:
; CHECK-NEXT:br label [[LOR_END:%.*]]
; CHECK: lor.rhs:
-; CHECK-NEXT:[[CMP3_NOT:%.*]] = icmp eq i64 [[A]], [[B:%.*]]
+; CHECK-NEXT:
@@ -0,0 +1,74 @@
+//===- DomConditionCache.cpp
--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM
Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier:
@@ -2840,6 +2841,46 @@ static Instruction *matchFunnelShift(Instruction ,
InstCombinerImpl ) {
return nullptr;
FShiftArgs = {ShVal0, ShVal1, ShAmt};
+ } else if (isa(Or0) || isa(Or1)) {
+// If there are two 'or' instructions concat variables in opposite order,
https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/70845
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https://github.com/dtcxzyw approved this pull request.
LGTM. Thank you!
Do you have the access to merge PR?
https://github.com/llvm/llvm-project/pull/70845
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@@ -0,0 +1,145 @@
+; RUN: opt < %s --O3 -S | FileCheck %s
dtcxzyw wrote:
My command: `bin/opt -S -O3 -print-changed min_max.ll`
Then I got IR after the SROA pass :)
https://github.com/llvm/llvm-project/pull/70845
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https://github.com/dtcxzyw commented:
LGTM
https://github.com/llvm/llvm-project/pull/70845
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@@ -0,0 +1,111 @@
+; RUN: opt < %s -O3 -S | FileCheck %s
+; See issue #55013 and PR #70845 for more details.
+; This test comes from the following C program, compiled with clang
+;
+;; short vecreduce_smin_v2i16(int n, short* v)
+;; {
+;; short p = 0;
+;; for (int i = 0; i <
https://github.com/dtcxzyw edited
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@@ -0,0 +1,112 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 3
+; RUN: opt < %s -O3 -S | FileCheck %s
+; See issue #55013 and PR #70845 for more details.
+; This test comes from the following C program, compiled with clang
+;
dtcxzyw wrote:
> Oh nice, I'm running into something similar in #71657. Are all these dead
> ADDIs coming from the backwards local postpass?
Yes. I believe this PR can address the issue.
https://github.com/llvm/llvm-project/pull/65934
___
@@ -0,0 +1,145 @@
+; RUN: opt < %s --O3 -S | FileCheck %s
dtcxzyw wrote:
```
define i16 @vecreduce_smin_v2i16(i32 %n, ptr %v) {
entry:
br label %for.cond
for.cond:
%p.0 = phi i16 [ 0, %entry ], [ %conv8, %for.inc ]
%i.0 = phi i32 [ 0, %entry ], [ %inc,
https://github.com/dtcxzyw requested changes to this pull request.
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@@ -0,0 +1,145 @@
+; RUN: opt < %s --O3 -S | FileCheck %s
dtcxzyw wrote:
```suggestion
; RUN: opt < %s -O3 -S | FileCheck %s
```
https://github.com/llvm/llvm-project/pull/70845
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@@ -0,0 +1,145 @@
+; RUN: opt < %s --O3 -S | FileCheck %s
dtcxzyw wrote:
Could you please:
1. Convert this IR into SSA form as @nikic mentioned.
2. Drop unused attributes.
3. Re-generate tests with `llvm/utils/update_test_checks.py`.
https://github.com/dtcxzyw edited
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dtcxzyw wrote:
Reduced test case: https://godbolt.org/z/d4ETPhbno
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@@ -0,0 +1,175 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 3
+; See PR-70845 for more details
+; RUN: opt < %s -S -passes=instcombine | FileCheck %s
+
+
+define signext i32 @sext_sext(i16 %x, i16 %y) {
@@ -0,0 +1,175 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
UTC_ARGS: --version 3
+; See PR-70845 for more details
+; RUN: opt < %s -S -passes=instcombine | FileCheck %s
+
+
+define signext i32 @sext_sext(i16 %x, i16 %y) {
+; CHECK-LABEL: define
https://github.com/dtcxzyw requested changes to this pull request.
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@@ -0,0 +1,126 @@
+; RUN: opt < %s --O3 -S | FileCheck %s
+
+define signext i16 @vecreduce_smax_v2i16(i32 noundef %0, ptr noundef %1) #0 {
dtcxzyw wrote:
Could you please reduce the test case and move it into `InstCombine`?
https://github.com/dtcxzyw edited
https://github.com/llvm/llvm-project/pull/70845
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@@ -5587,11 +5587,20 @@ Instruction
*InstCombinerImpl::foldICmpWithZextOrSext(ICmpInst ) {
return new ICmpInst(ICmp.getPredicate(), Builder.CreateOr(X, Y),
Constant::getNullValue(X->getType()));
+ // Treat "zext nneg" as "sext"
+
https://github.com/dtcxzyw approved this pull request.
LGTM. Thanks!
We can improve the compile time by adding `nneg` flag during the zext creation
(e.g., `cttz(zext(x)) -> zext nneg(cttz(x))`).
https://github.com/llvm/llvm-project/pull/71534
___
dtcxzyw wrote:
Please also update existing uses in `lldb`.
Buildbot failure: https://lab.llvm.org/buildbot/#/builders/68/builds/63101
https://github.com/llvm/llvm-project/pull/71029
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https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/70294
>From 1222b8bda348af58f4921a45d8cddca726875bb9 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Thu, 26 Oct 2023 13:47:39 +0800
Subject: [PATCH 1/2] [RISCV] Add processor definition for XiangShan-NanHu
dtcxzyw wrote:
Ping. @preames Any more comments?
https://github.com/llvm/llvm-project/pull/70294
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dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65934
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dtcxzyw wrote:
Rebased on top of #70241.
https://github.com/llvm/llvm-project/pull/70232
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https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/70232
>From b34055dca42c23682bb9f0e9e022f17e9dbf2aca Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 28 Oct 2023 20:46:37 +0800
Subject: [PATCH] [RISCV] Add sched model for XiangShan-NanHu
Co-authored-by:
dtcxzyw wrote:
Any more questions about XiangShan? If there is no question, I will merge this
PR tomorrow.
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dtcxzyw wrote:
> LGTM in general, except one question: will zicbom and zicboz be in the final
> RTL?
You can find the full implementation of `zicbom` and `zicboz` here:
https://github.com/OpenXiangShan/XiangShan/commit/ca18a0b47b0e4089fd0dd1c085091cb90bf98f25.
cc @poemonsense
@@ -20,6 +20,17 @@
// MCPU-SYNTACORE-SCR1-MAX: "-target-feature" "+zicsr" "-target-feature"
"+zifencei"
// MCPU-SYNTACORE-SCR1-MAX: "-target-abi" "ilp32"
+// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=xiangshan-nanhu |
FileCheck -check-prefix=MCPU-XIANGSHAN-NANHU %s
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/70294
>From a4e46c81c5235754bf7b4e0b3dd3ff8805b3e56d Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Thu, 26 Oct 2023 13:47:39 +0800
Subject: [PATCH 1/2] [RISCV] Add processor definition for XiangShan-NanHu
dtcxzyw wrote:
> Can you separate out the basic processor definition (using NoSchedModel), and
> a patch which adds the scheduling model? We can at least get the processor
> definition landed while we iterate on the scheduling related pieces.
>
> edit: For clarity, I'm requesting that the
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/70294
This PR adds the processor definition for XiangShan-NanHu, an open-source
high-performance RISC-V processor.
According to the official
[documentation](https://xiangshan-doc.readthedocs.io/zh-cn/latest/arch/),
@@ -302,7 +302,7 @@ def FSW : FPStore_r<0b010, "fsw", FPR32, WriteFST32>;
} // Predicates = [HasStdExtF]
foreach Ext = FExts in {
- let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32] in {
+ let SchedRW = [WriteFMA32, ReadFMA32, ReadFMA32, ReadFMA32Addend] in {
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/70232
[XiangShan](https://github.com/OpenXiangShan/XiangShan) is an open-source
high-performance RISC-V processor.
This PR adds the schedule model for XiangShan-NanHu, the 2nd Gen core of the
XiangShan processor
https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/69252
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https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/69252
>From 6e34e74e8e8046aaa086869e8a8aecb781dd3b3b Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:17:17 +0800
Subject: [PATCH 1/3] [Clang] Add pre-commit tests for PR69218. NFC.
---
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/69252
>From 8f0ebe5b5cfed069c8274c0761559d6595d4dea8 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:17:17 +0800
Subject: [PATCH 1/3] [Clang] Add pre-commit tests for PR69218. NFC.
---
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/69252
>From 8f0ebe5b5cfed069c8274c0761559d6595d4dea8 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023 05:17:17 +0800
Subject: [PATCH 1/3] [Clang] Add pre-commit tests for PR69218. NFC.
---
dtcxzyw wrote:
@nikic Any comments about this PR?
https://github.com/llvm/llvm-project/pull/67917
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dtcxzyw wrote:
@nikic Any comments about this PR?
https://github.com/llvm/llvm-project/pull/67917
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dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/67917
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dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/67917
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@@ -6411,6 +6411,41 @@ static Value *simplifyBinaryIntrinsic(Function *F, Value
*Op0, Value *Op1,
return Constant::getNullValue(ReturnType);
break;
}
+ case Intrinsic::ptrmask: {
+if (isa(Op0) || isa(Op1))
+ return PoisonValue::get(Op0->getType());
+
+
https://github.com/dtcxzyw created
https://github.com/llvm/llvm-project/pull/69252
This patch handles formatting of real and imaginary parts of complex lvalue.
Fixes #69218.
>From 8f0ebe5b5cfed069c8274c0761559d6595d4dea8 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 17 Oct 2023
dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65934
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Author: Yingwei Zheng
Date: 2023-10-13T15:19:35+08:00
New Revision: 411ceacf4351bd3af9db75b859063864b19e71e1
URL:
https://github.com/llvm/llvm-project/commit/411ceacf4351bd3af9db75b859063864b19e71e1
DIFF:
https://github.com/llvm/llvm-project/commit/411ceacf4351bd3af9db75b859063864b19e71e1.diff
https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/67915
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dtcxzyw wrote:
Gentle ping.
https://github.com/llvm/llvm-project/pull/65934
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dtcxzyw wrote:
Gentle ping.
https://github.com/llvm/llvm-project/pull/65934
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https://github.com/dtcxzyw approved this pull request.
LGTM
https://github.com/llvm/llvm-project/pull/67403
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https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/65852
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https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/67915
>From c4ce28c942c172e5646b5922f0b02b4169197840 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 1 Oct 2023 21:52:47 +0800
Subject: [PATCH 1/2] [InstCombine] Canonicalize `(X +/- Y) & Y` into `~X & Y`
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/67915
>From c4ce28c942c172e5646b5922f0b02b4169197840 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 1 Oct 2023 21:52:47 +0800
Subject: [PATCH 1/2] [InstCombine] Canonicalize `(X +/- Y) & Y` into `~X & Y`
dtcxzyw wrote:
The conflict resolution should be correct now.
https://github.com/llvm/llvm-project/pull/65852
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dtcxzyw wrote:
The conflict resolution should be correct now.
https://github.com/llvm/llvm-project/pull/65852
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https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 01/10] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 01/10] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 01/10] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 01/10] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/67915
>From c4ce28c942c172e5646b5922f0b02b4169197840 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 1 Oct 2023 21:52:47 +0800
Subject: [PATCH 1/2] [InstCombine] Canonicalize `(X +/- Y) & Y` into `~X & Y`
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 01/10] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 01/10] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
https://github.com/dtcxzyw edited
https://github.com/llvm/llvm-project/pull/67917
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@@ -1735,6 +1746,122 @@ ConstantRange ConstantRange::ctlz(bool ZeroIsPoison)
const {
return getNonEmpty(APInt(getBitWidth(), getUnsignedMax().countl_zero()),
APInt(getBitWidth(), getUnsignedMin().countl_zero() + 1));
}
+static ConstantRange
@@ -1735,6 +1746,122 @@ ConstantRange ConstantRange::ctlz(bool ZeroIsPoison)
const {
return getNonEmpty(APInt(getBitWidth(), getUnsignedMax().countl_zero()),
APInt(getBitWidth(), getUnsignedMin().countl_zero() + 1));
}
+static ConstantRange
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/67917
>From b5d134c88a04c524b1d9120a1c1a5dae3722904c Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 1 Oct 2023 22:17:35 +0800
Subject: [PATCH 1/4] [ConstantRange] Handle `Intrinsic::cttz` and
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/67917
>From b5d134c88a04c524b1d9120a1c1a5dae3722904c Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 1 Oct 2023 22:17:35 +0800
Subject: [PATCH 1/4] [ConstantRange] Handle `Intrinsic::cttz` and
@@ -1735,6 +1746,122 @@ ConstantRange ConstantRange::ctlz(bool ZeroIsPoison)
const {
return getNonEmpty(APInt(getBitWidth(), getUnsignedMax().countl_zero()),
APInt(getBitWidth(), getUnsignedMin().countl_zero() + 1));
}
+static ConstantRange
@@ -1735,6 +1746,122 @@ ConstantRange ConstantRange::ctlz(bool ZeroIsPoison)
const {
return getNonEmpty(APInt(getBitWidth(), getUnsignedMax().countl_zero()),
APInt(getBitWidth(), getUnsignedMin().countl_zero() + 1));
}
+static ConstantRange
https://github.com/dtcxzyw edited
https://github.com/llvm/llvm-project/pull/67917
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https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/67917
>From b5d134c88a04c524b1d9120a1c1a5dae3722904c Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 1 Oct 2023 22:17:35 +0800
Subject: [PATCH 1/3] [ConstantRange] Handle `Intrinsic::cttz` and
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/67917
>From b5d134c88a04c524b1d9120a1c1a5dae3722904c Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 1 Oct 2023 22:17:35 +0800
Subject: [PATCH 1/3] [ConstantRange] Handle `Intrinsic::cttz` and
https://github.com/dtcxzyw edited
https://github.com/llvm/llvm-project/pull/67917
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https://github.com/dtcxzyw edited
https://github.com/llvm/llvm-project/pull/67917
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https://github.com/llvm/llvm-project/pull/67917
>From b5d134c88a04c524b1d9120a1c1a5dae3722904c Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 1 Oct 2023 22:17:35 +0800
Subject: [PATCH 1/2] [ConstantRange] Handle `Intrinsic::cttz` and
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/67917
>From b5d134c88a04c524b1d9120a1c1a5dae3722904c Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 1 Oct 2023 22:17:35 +0800
Subject: [PATCH 1/2] [ConstantRange] Handle `Intrinsic::cttz` and
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/67915
>From c4ce28c942c172e5646b5922f0b02b4169197840 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sun, 1 Oct 2023 21:52:47 +0800
Subject: [PATCH] [InstCombine] Canonicalize `(X +/- Y) & Y` into `~X & Y` when
Y
dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65852
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dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65852
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dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65934
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https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/9] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/9] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/9] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/9] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
@@ -6380,7 +6380,71 @@ Instruction
*InstCombinerImpl::foldICmpUsingBoolRange(ICmpInst ) {
Y->getType()->isIntOrIntVectorTy(1) && Pred == ICmpInst::ICMP_ULE)
return BinaryOperator::CreateOr(Builder.CreateIsNull(X), Y);
+ // icmp eq/ne X, (zext/sext (icmp eq/ne X,
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65934
>From 2fe5756dd4d49580d3a23b0ff1b72535f725915e Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 15:51:46 +0800
Subject: [PATCH 1/4] [RISCV] Eliminate dead li after emitting VSETVLIs
---
dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65852
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https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/66740
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>From 85f7911dfe0f1e9112881a9f503bcd68edfde580 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 19 Sep 2023 10:19:46 +0800
Subject: [PATCH 1/3] [InstCombine] Canonicalize `and(zext(A), B)` into `select
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