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@@ -757,7 +757,8 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
bool computeVLVTYPEChanges(const MachineBasicBlock ,
VSETVLIInfo ) const;
void computeIncomingVLVTYPE(const MachineBasicBlock );
- void emitVSETVLIs(MachineBasicBlock
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@@ -757,7 +757,8 @@ class RISCVInsertVSETVLI : public MachineFunctionPass {
bool computeVLVTYPEChanges(const MachineBasicBlock ,
VSETVLIInfo ) const;
void computeIncomingVLVTYPE(const MachineBasicBlock );
- void emitVSETVLIs(MachineBasicBlock
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>From 2fe5756dd4d49580d3a23b0ff1b72535f725915e Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 15:51:46 +0800
Subject: [PATCH 1/4] [RISCV] Eliminate dead li after emitting VSETVLIs
---
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65934
>From 2fe5756dd4d49580d3a23b0ff1b72535f725915e Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 15:51:46 +0800
Subject: [PATCH 1/4] [RISCV] Eliminate dead li after emitting VSETVLIs
---
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>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/8] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/8] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
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@@ -8291,6 +8291,29 @@ static std::optional isImpliedCondICmps(const
ICmpInst *LHS,
if (L0 == R0 && match(L1, m_APInt(LC)) && match(R1, m_APInt(RC)))
return isImpliedCondCommonOperandWithConstants(LPred, *LC, RPred, *RC);
+ // L0 = R0 = L1 + R1, L0 >=u L1 implies R0
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>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/7] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/7] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
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@@ -8291,6 +8291,29 @@ static std::optional isImpliedCondICmps(const
ICmpInst *LHS,
if (L0 == R0 && match(L1, m_APInt(LC)) && match(R1, m_APInt(RC)))
return isImpliedCondCommonOperandWithConstants(LPred, *LC, RPred, *RC);
+ // L0 = R0 = L1 + R1, L0 >=u L1 implies R0
@@ -8291,6 +8291,29 @@ static std::optional isImpliedCondICmps(const
ICmpInst *LHS,
if (L0 == R0 && match(L1, m_APInt(LC)) && match(R1, m_APInt(RC)))
return isImpliedCondCommonOperandWithConstants(LPred, *LC, RPred, *RC);
+ // L0 = R0 = L1 + R1, L0 >=u L1 implies R0
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>From 9bb817aa40dd9bc1bbb18b4cf4bc079145c8ecaa Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 03:58:02 +0800
Subject: [PATCH 1/2] [ValueTracking] Simplify uaddo pattern
---
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65910
>From 9bb817aa40dd9bc1bbb18b4cf4bc079145c8ecaa Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 03:58:02 +0800
Subject: [PATCH 1/2] [ValueTracking] Simplify uaddo pattern
---
@@ -1964,18 +1964,78 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst
) {
break;
}
case Intrinsic::ptrmask: {
+KnownBits Known(DL.getPointerTypeSizeInBits(II->getType()));
+if (SimplifyDemandedInstructionBits(*II, Known))
+ return II;
+
+Value
dtcxzyw wrote:
To avoid backend regressions, I will merge this PR after #66793.
https://github.com/llvm/llvm-project/pull/66740
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dtcxzyw wrote:
> You might want to check whether this also fixes #66740 and if so add a test.
Confirmed. I have added a pre-commit test for 66733 in
1a73a6b80b54cd23ee8380c6fa3304847e5cb5d1.
https://github.com/llvm/llvm-project/pull/66740
___
dtcxzyw wrote:
> You might want to check whether this also fixes #66740 and if so add a test.
Confirmed. I have added a pre-commit test for 66733 in
1a73a6b80b54cd23ee8380c6fa3304847e5cb5d1.
https://github.com/llvm/llvm-project/pull/66740
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>From 85f7911dfe0f1e9112881a9f503bcd68edfde580 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Tue, 19 Sep 2023 10:19:46 +0800
Subject: [PATCH 1/3] [InstCombine] Canonicalize `and(zext(A), B)` into `select
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dtcxzyw wrote:
> We should use rebase instead of merge. And I recommend force push to change
> the code before the review starts.
I am confused with the LLVM GitHub user guide. I witnessed someone mess up by
doing rebase + force push.
Examples: #65853 #65543 #65535
dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65910
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dtcxzyw wrote:
Ping.
https://github.com/llvm/llvm-project/pull/65910
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>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/6] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/6] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
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@@ -366,19 +366,10 @@ define void @simplify_before_foldAndOfICmps(ptr %p) {
; CHECK-LABEL: @simplify_before_foldAndOfICmps(
; CHECK-NEXT:[[A8:%.*]] = alloca i16, align 2
; CHECK-NEXT:[[L7:%.*]] = load i16, ptr [[A8]], align 2
-; CHECK-NEXT:[[TMP1:%.*]] = icmp eq
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>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/5] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
@@ -6380,7 +6380,56 @@ Instruction
*InstCombinerImpl::foldICmpUsingBoolRange(ICmpInst ) {
Y->getType()->isIntOrIntVectorTy(1) && Pred == ICmpInst::ICMP_ULE)
return BinaryOperator::CreateOr(Builder.CreateIsNull(X), Y);
+ ICmpInst::Predicate Pred1, Pred2;
const
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/3] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
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>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH 1/2] [InstCombine] Simplify the pattern `a ne/eq (zext (a
ne/eq
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>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH] [InstCombine] Simplify the pattern `a ne/eq (zext (a ne/eq
c))`
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65852
>From d9d8bcbb98e8f5aecb9733329389d61a489bd731 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 23:07:29 +0800
Subject: [PATCH] [InstCombine] Simplify the pattern `a ne/eq (zext (a ne/eq
c))`
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https://github.com/llvm/llvm-project/pull/65905
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dtcxzyw wrote:
> LGTM, but please cleanup commits.
GitHub will squash commits into a single commit.
https://github.com/llvm/llvm-project/pull/65905
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dtcxzyw wrote:
> LGTM, but please cleanup commits.
GitHub will squash commits into a single commit.
https://github.com/llvm/llvm-project/pull/65905
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>From f178af6d47ce6d982c6568ba6e0db517de124291 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 02:01:12 +0800
Subject: [PATCH 1/2] [InstSimplify] Simplify `icmp X & C1, X & C2` when `(C1 &
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>From f178af6d47ce6d982c6568ba6e0db517de124291 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 02:01:12 +0800
Subject: [PATCH] [InstSimplify] Simplify `icmp X & C1, X & C2` when `(C1 & C2)
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65905
>From f178af6d47ce6d982c6568ba6e0db517de124291 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 02:01:12 +0800
Subject: [PATCH] [InstSimplify] Simplify `icmp X & C1, X & C2` when `(C1 & C2)
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>From 91af70acd72c8e889f542ba6dfff6401b89b2dc5 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 16:47:24 +0800
Subject: [PATCH 1/2] [InstCombine] Fix transforms of select (~a | c), a, b and
https://github.com/dtcxzyw updated
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>From 91af70acd72c8e889f542ba6dfff6401b89b2dc5 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 16:47:24 +0800
Subject: [PATCH 1/2] [InstCombine] Fix transforms of select (~a | c), a, b and
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>From 91af70acd72c8e889f542ba6dfff6401b89b2dc5 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 16:47:24 +0800
Subject: [PATCH] [InstCombine] Fix transforms of select (~a | c), a, b and
select
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65845
>From 91af70acd72c8e889f542ba6dfff6401b89b2dc5 Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Sat, 9 Sep 2023 16:47:24 +0800
Subject: [PATCH] [InstCombine] Fix transforms of select (~a | c), a, b and
select
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65910
>From 9bb817aa40dd9bc1bbb18b4cf4bc079145c8ecaa Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 03:58:02 +0800
Subject: [PATCH] [ValueTracking] Simplify uaddo pattern
---
https://github.com/dtcxzyw updated
https://github.com/llvm/llvm-project/pull/65910
>From 9bb817aa40dd9bc1bbb18b4cf4bc079145c8ecaa Mon Sep 17 00:00:00 2001
From: Yingwei Zheng
Date: Mon, 11 Sep 2023 03:58:02 +0800
Subject: [PATCH] [ValueTracking] Simplify uaddo pattern
---
https://github.com/dtcxzyw closed
https://github.com/llvm/llvm-project/pull/65944
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LGTM
https://github.com/llvm/llvm-project/pull/65944
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@@ -2262,11 +2262,11 @@ defm vmfgt : RVVFloatingMaskOutBuiltinSet;
defm vmfge : RVVFloatingMaskOutBuiltinSet;
}
-// 14.14. Vector Floating-Point Classify Instruction
+// 13.14. Vector Floating-Point Classify Instruction
let Name = "vfclass_v", UnMaskedPolicyScheme =
@@ -1660,29 +1660,29 @@ let HasMasked = false, MaskedPolicyScheme = NonePolicy
in {
defm vmsbc : RVVIntMaskOutBuiltinSet;
}
-// 12.5. Vector Bitwise Logical Instructions
+// 11.5. Vector Bitwise Logical Instructions
let UnMaskedPolicyScheme = HasPassthruOperand in {
defm
@@ -1660,29 +1660,29 @@ let HasMasked = false, MaskedPolicyScheme = NonePolicy
in {
defm vmsbc : RVVIntMaskOutBuiltinSet;
}
-// 12.5. Vector Bitwise Logical Instructions
+// 11.5. Vector Bitwise Logical Instructions
let UnMaskedPolicyScheme = HasPassthruOperand in {
defm
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