Re: [coreboot] Porting Kabylake laptop

On Wed, Jun 27, 2018 at 8:18 AM Nico Huber wrote: > so you are doing UEFI board ports yourself now? I always had the impres- > sion that you merely reuse existing ports and plug in the kernel. This is probably my imprecise language, sorry about that. We take SEC and PEI as a given, and the

Re: [coreboot] Porting Kabylake laptop

On Wed, Jun 27, 2018 at 4:37 AM wrote: > > Doesn't linuxboot also require the FSP blob for memory and silicon > initialization on any Intel board after Ivy Bridge? > > > No. On x86 we do assume UEFI, however. That's a safe assumption. From what I've seen, working with UEFI, as we do in

Re: [coreboot] Porting Kabylake laptop

For a case like this, where your choice is between two binary blobs (FSP or UEFI) I would argue that linuxboot is a better way to go. See github.com/osresearch/heads or linuxboot.org for more info. ron -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] RISC-V HiFive Unleashed board added to coreboot - has PCI-e slots via exp board

On Mon, Jun 25, 2018 at 8:46 AM Peter Stuge wrote: > ron minnich wrote: > > I realize there was a lot of hope in the early days that RISC-V > > implied "openness" but as we can see that is not so. > > I hope that noone had that impression. > Lots of people

Re: [coreboot] RISC-V HiFive Unleashed board added to coreboot - has PCI-e slots via exp board

On Mon, Jun 25, 2018 at 12:55 AM Shawn wrote: > Hi Ron, > > > IIRC, Machine mode in RISC-V is just looking similar to SMM in x86. > But it can do more than what SMM does. > that's in my view not good, since in many cases, M mode code is part of firmware, not the kernel image. Kernels don't get

Re: [coreboot] RISC-V HiFive Unleashed board added to coreboot - has PCI-e slots via exp board

I'm still interested in risc-v, just not hifive. In saying I've lost interest, I'm definitely not saying anyone is a bad person. The sifive people are wonderful, personally and professionally, and I wish them the best success. But sifive had to make some decisions to get to what they thought

Re: [coreboot] RISC-V HiFive Unleashed board added to coreboot - has PCI-e slots via exp board

On Sun, Jun 24, 2018 at 11:47 AM Jonathan Neuschäfer wrote: > > > "While we’d love to provide you with this information, we believe we > cannot. However, we can’t prevent anyone from disassembling the fsbl and > copying the values sent to the blackbox DDR register map." > > and ... there ends

Re: [coreboot] RISC-V HiFive Unleashed board added to coreboot - has PCI-e slots via exp board

On Wed, Jun 20, 2018 at 11:03 PM taii...@gmx.com wrote: > > > Whats the deal with SMM? What a shame they thought to add it. > > > It's a huge disappointment. I made some effort a few years ago to try to convince folks this was a bad idea and failed. I'm no longer as optimistic as I was about

Re: [coreboot] RISC-V HiFive Unleashed board added to coreboot - has PCI-e slots via exp board

All this said, note that the HiFive is no more open, today, than your average ARM SOC; and it is much less open than, e.g., Power. I realize there was a lot of hope in the early days that RISC-V implied "openness" but as we can see that is not so. There's blobs in HiFive. Open instruction sets do

Re: [coreboot] Equus "WHITEBOX OPEN" servers ship with Coreboot/LinuxBoot

i'm going to be talking to them. On Thu, Jun 21, 2018 at 11:36 AM David Hendricks wrote: > I'm calling shenanigans on this. Their server datasheets pretty clearly > specify an IBV-provided firmware solution, definitely NOT coreboot or > LinuxBoot and definitely NOT open. I did hear thru the

Re: [coreboot] proposal: coreboot docs in separate repo

On Tue, Jun 12, 2018 at 4:56 PM Leah Rowe wrote: > > > Wait a few years when more pages are added to the docs. Add images. > The repo will start becoming gigabytes in size. > > will do. We'll wait a few years :-) -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] proposal: coreboot docs in separate repo

On Tue, Jun 12, 2018 at 3:17 PM Leah Rowe wrote: > > > That's going to weigh down the repository and make it huge, over the > years. It means that adding images etc is going to be a pain too. > Let's get a number here. Define 'huge'. I just did a quick check and that directory is a tiny

Re: [coreboot] POWER9 / Talos II coreboot support?

aptorcs.com/wiki/File:POWER9_Registers_vol3_version1.2_pub.pdf > > > >> That leaves only the PHB documentation in process at this point. Almost > >> there > > > >> On 05/12/2018 02:34 AM, Timothy Pearson wrote: > >>> On 05/03/

Re: [coreboot] Who is still using a 1980's tty for coreboot development?

laptops are just about all I use, and the 238 cols on my macbook does the trick. On Fri, May 25, 2018 at 5:01 PM Vadim Bendebury wrote: > On Fri, May 25, 2018 at 8:24 AM Patrick Georgi wrote: > >> Am Fr., 25. Mai 2018 um 17:05 Uhr schrieb Vadim

Re: [coreboot] Who is still using a 1980's tty for coreboot development?

ok, but looking at https://review.coreboot.org/#/c/coreboot/+/26512/, is there any single thing in there that stands out as a a problem? Every single change looks better to me. I still don't see the problem with 132. I did a quick check on the Go source tree, where there basically are no limits

Re: [coreboot] Who is still using a 1980's tty for coreboot development?

I've just done an exercise with clang-format and tried 80, 100, 120, and 132 column formatting on the riscv arch code, see here: https://review.coreboot.org/#/c/coreboot/+/26512/ overall, after staring at it a bit, I found 132 the most readable. I find breaking strings and folding parameters to

Re: [coreboot] When does AMD release the fam15 spectre microcode updates?

On Wed, May 23, 2018 at 12:54 PM Rudolf Marek wrote: > Hi all, > > Dne 22.5.2018 v 07:03 taii...@gmx.com napsal(a): > > > > don't they have those in this update? Would it be possible to easily add > > the support flags without microcode for those who use libreboot? > > So

Re: [coreboot] ThinkPad W530 support

Wow, that's really good news :-) On Mon, May 21, 2018 at 8:45 AM Evgeny wrote: > I am pleased to announce a working patch for the W530. > https://review.coreboot.org/#/c/coreboot/+/26136/ > > Regards, > Evgeny Zinoviev > > > -- > coreboot mailing list: coreboot@coreboot.org >

Re: [coreboot] Proposing a change to Coding Style

https://review.coreboot.org/#/c/coreboot/+/26368/ On Fri, May 18, 2018 at 5:55 AM Julien Viard de Galbert < jviarddegalb...@online.net> wrote: > > > Le 16 mai 2018 à 17:15, Patrick Georgi via coreboot > a écrit : > > Hi everybody, > > after just running into an issue on

Re: [coreboot] Why coreboot for riscv does not support multi-core?

On Fri, May 18, 2018 at 3:19 AM Jonathan Neuschäfer wrote: > On Fri, May 18, 2018 at 11:46:54AM +0800, 王翔 wrote: > [...] > > Is coreboot's payload a bootloader running in m-mode ? > > If not, how does the SBI interrupt service be implemented ? > > Previously, coreboot

Re: [coreboot] Thinkpad X230: store the proprietary VGA bios in the blobs repo?

Peter is right. Unless you get a clear statement from the owner of the VGA BIOS you can't put it in the repo. On Wed, May 16, 2018 at 3:17 PM Peter Stuge wrote: > Martin Kepplinger wrote: > > Unfortunately I haven't yet found a license applying to it. I'm > > thankful for hints.

Re: [coreboot] Proposing a change to Coding Style

I like your proposal for a one line else On Wed, May 16, 2018 at 3:20 PM Felix Held wrote: > Hi! > > > I hereby propose that > > going forward, we should always wrap conditional blocks in braces, even > > one-liners. > > I'd also like to have this change, since it

[Cocci] convert if (x) stmt to if (x) {stmt}

we've found another one of these if (x) y z things in firmware that were intended to be if (x) { y z } we're kind of tired of this and want to blanket require {} for all ifs, even one liners. We want to convert the entire code base such that all if (E) S becomes if (E) {S} but of course we

Re: [coreboot] Proposing a change to Coding Style

I sfrongly support this idea. The list of bugs that have occurred due to simple lacking {} is long. It's even harder now that people who use Python and C sometimes glitch when moving back and forth and forget that indentation in C is meaningless. I ran a piece of broken C (multi-line if missing

[coreboot] MX66l51235f

anyone got the incantation to flash this with an sf100 ;-) -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

[flashrom] MX66l51235f

anyone got the incantation to flash this with an sf100 ;-) ___ flashrom mailing list flashrom@flashrom.org https://mail.coreboot.org/mailman/listinfo/flashrom

Re: [coreboot] flashrom on osx ...

not late enough, sadly, and why the heck won't this build from github repo ... uses packagemanager which is no longer a thing. On Fri, May 11, 2018 at 11:07 AM Alberto Bursi <alberto.bu...@outlook.it> wrote: > > On 11/05/2018 19:42, ron minnich wrote: > > if I just want to us

[coreboot] flashrom on osx ...

if I just want to use a dediprog sf100 what's the best way to build flashrom on osx? besides "throw the macbook in the trash and get a real computer" :-) ron -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] POWER9 / Talos II coreboot support?

On Thu, May 3, 2018 at 1:20 PM Timothy Pearson < tpear...@raptorengineering.com> wrote: > -BEGIN PGP SIGNED MESSAGE- > Hash: SHA256 > > I think I was being a bit pessimistic / too careful here. We're close > to getting the docs publicly released, but that doesn't help anyone > wanting

Re: [coreboot] POWER9 / Talos II coreboot support?

"There is no legal issue that we are aware of with using them to develop a libre firmware solution like coreboot; IBM just doesn't want the detailed register manuals distributed verbatim online at this time." This is worrisome. Intel docs used to be the same way in 1999, otherwise LinuxBIOS

Re: [coreboot] [RFH] Status of the Lenovo X201

Yeah I think you want to hunt this stack smash error down, it's not something you want to ignore. On Wed, May 2, 2018 at 11:09 AM Kyösti Mälkki wrote: > On Wed, May 2, 2018 at 8:53 PM, Nico Huber wrote: > > On 02.05.2018 18:37, qtux wrote: > >> Thanks

Re: [coreboot] Thread derailment

We've had to remove people from the list before, and I suppose at some point it might have to happen again. Nobody likes this option. Sometimes there is no choice. I agree that on a technical discussion list there's no place for abusive language. We're all trying to do the best we can in a

Re: Changing Perkeep's config files from JSON to TOML

I do comments in JSON with variables with comment text. But if TOML works better for you then go for it. On Mon, Apr 30, 2018 at 5:00 PM Mike Lloyd wrote: > I'm fine with TOML because it's better than YAML and it's flat, so there's > that. > > I can be okay with

Re: [coreboot] [URGENT] Full List of AMD-based boards that are going to be removed from coreboot unless people cough up a board status update

This is a *personal* opinion, not supported by anyone else I suppose, but: I don't think it's unreasonable to ask that people send in board status 2 times a year. That's it. It makes it easier for potential users, and for people maintaining the tree. Sound ok? ron -- coreboot mailing list:

Re: [coreboot] [URGENT] - The KCMA-D8 is going to be removed from coreboot unless people cough up a board status update

On Wed, Apr 4, 2018 at 3:38 PM taii...@gmx.com wrote: > At the rate things are going soon there will be no non-development > boards that are still in the repos due to the arbitrary increasing of > standards. > I can tell you, based on the 19 years of this project's existence,

Re: perkeepd "Caught panic installer handlers: Done called more than Start"

Lonjaret <mathieu.lonja...@gmail.com> wrote: > Hi Ron, > > There's a summary at https://perkeep.org/doc/compare but I'll try to > explain deeper if you have further questions. > > Cheers, > Mathieu > > > On 24 April 2018 at 09:23, ron minnich <rminn...@g

Re: perkeepd "Caught panic installer handlers: Done called more than Start"

point of confusion for me. what goals of perkeep might overlap or differ from upspin? On Tue, Apr 24, 2018 at 9:14 AM Mathieu Lonjaret wrote: > we fixed that yesterday in 4a562043e02972f4bea19ca476caab1dac1ca078 > Please pull again and you should be fine :-) > > >

Re: [coreboot] BIOS/CoreBoot/UBOOT

At this point, on this platform, I think your fastest bet to mostly open sourcing it all is linuxboot. We recently had an experience where we installed a linux kernel in FLASH on two new boards in two days and most of that was just figuring out how to rearrange the UEFI bits, (i.e. move the

Re: [coreboot] coreboot is going to make kcma-d8 obsolete

On Sat, Apr 7, 2018 at 2:54 AM Leah Rowe wrote: > > > I'll be really upset if D8/D16, or any libreboot-supported hardware, > is removed from coreboot.git. > > > and as David has pointed, it never is or will be. It's always there. I don't understand your point here.

Re: [coreboot] coreboot is going to make kcma-d8 obsolete

On Fri, Apr 6, 2018 at 5:45 PM Thierry Laurion wrote: > I agree. This is wrong. > Kgpe-d16 and alike are the last resorts for x86 blob free hardware. > > This NEEDS to be kept maintained and upstreamed. > > > I like the board too. I have one. I have no time to keep it

[9fans] rbind

I've been looking for source to rbind, and Aki no longer has it. If anyone still has it can you ping me off list and let me know? thanks ron

Re: [coreboot] Fwd: POST cards, I/O ports and M.2 to MiniPCIe

On Tue, Apr 3, 2018 at 2:30 PM Trammell Hudson wrote: > > What ended up working for me was the PC speaker since there is no other > I/O available so early. I'd really like to thank Uwe Hermann and the > other devs of libpayload/speaker.c -- I was able to port their driver >

Re: [coreboot] [RFC] Fix undefined behavior with left shifts in whole code base

I refer you to the following code: https://github.com/hephaex/unix-v6/blob/daa355109625a50e6b1080184dee30c9136549d1/param.h#L72 It's this: /* * structure to access an * integer in bytes */ struct { char lobyte; char hibyte; }; What's the point? The point is code linke this: lpr =

Re: [coreboot] shrdw question

On Thu, Mar 29, 2018 at 3:16 PM Nico Huber <nic...@gmx.de> wrote: > On 29.03.2018 23:58, ron minnich wrote: > > believe it or not that code runs on coreboot simulator, hardware, and > qemu, > > What is `coreboot simulator`? > > > the 8086 one in yabel. So here's

Re: [coreboot] shrdw question

believe it or not that code runs on coreboot simulator, hardware, and qemu, and gets a different answer on each. On Thu, Mar 29, 2018 at 12:54 PM Nico Huber <nic...@gmx.de> wrote: > On 29.03.2018 20:25, ron minnich wrote: > > I have the following code: > > > > movl

[coreboot] shrdw question

I have the following code: movl $0x12345678, %eax movl $0x, %ebx movb $0x10, %cl shrdw %ebx, %eax quiz: what's the value of %ax after this instruction? -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Server systems shipped with coreboot

On Sat, Mar 24, 2018 at 6:22 AM Alberto Bursi wrote: > I was writing within context of this mail thread. > > This mail "thread" is about Coreboot on server systems, and no major > manufacturer I know of, apart from IBM and the board from Raptor > Engineering ever used

Re: [coreboot] Gigabyte MB to Test

we need a bit more than that ... lspci and lspci -xxx and does this thing run UEFI? On Thu, Mar 15, 2018 at 3:34 PM Jeff Ausfeld wrote: > Hi Coreboot Team, > > I have several of the following boards, and it badly needs a Bios overhaul > as I'm trying to get a Compex

Re: [coreboot] inteltool and sys/io.h

why on earth is that test there? what does glibc have to do with whether you have sys/io.h? I suggest removing the guard. On Wed, Feb 14, 2018 at 10:12 AM Trammell Hudson wrote: > When cross compiling inteltool with musl-libc the header > is not included due to this test in

Re: [coreboot] I want to be a contributor(Cloud Dai)

On Tue, Jan 23, 2018 at 11:57 AM taii...@gmx.com wrote: > I would suggest purchasing a USB CH341A programmer, I use it for my > KGPE-D16 and it is great. > > me too. -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Server systems shipped with coreboot

how many cores is that? Does it come with LPAR? On Mon, Jan 22, 2018 at 9:48 PM taii...@gmx.com wrote: > In case anyone wants to know the (non-coreboot) libre firmware TALOS 2 > single CPU/board combo is now only 2.5K. > > I still can't figure out how they managed to make it so

Re: [coreboot] I want to be a contributor (Cloud Dai)

On Sat, Jan 20, 2018 at 11:22 AM taii...@gmx.com wrote: > > Can you explain why this is a bad thing? > And in terms of quality you mean when it comes to the port?, the > facebook OpenBMC? or the IBM OpenBMC? (what is the difference anyway? > why did facebook make their own?) > >

Re: [coreboot] I want to be a contributor (Cloud Dai)

But ... if you've never installed coreboot before, you really want to start with a supported, known working board so you understand all the moving parts, at least that's my belief. On Sat, Jan 20, 2018 at 10:24 AM taii...@gmx.com wrote: > On 01/20/2018 12:44 PM, Kyösti Mälkki

Re: [coreboot] I want to be a contributor (Cloud Dai)

If you're just wanting to get a start on coreboot, with boards that are currently sold, I personally like the PC Engines boards. On Sat, Jan 20, 2018 at 9:45 AM Kyösti Mälkki wrote: > On Fri, Jan 19, 2018 at 8:04 PM, taii...@gmx.com wrote: > > On

[coreboot] x86 validation suite

Anybody out there know of an x86 emulation validation suite? thanks ron -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] free to good home: minnowmax board(s)

and it's gone, sorry all,Philip got here first ... ron On Mon, Jan 15, 2018 at 11:27 AM ron minnich <rminn...@gmail.com> wrote: > anybody want one of these? I have a few but no time to work on them. > -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot

[coreboot] free to good home: minnowmax board(s)

anybody want one of these? I have a few but no time to work on them. -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] How to properly conform with GPLv2 for Coreboot and SeaBIOS on an embedded system

On Fri, Dec 29, 2017 at 5:20 PM Lewis, Ian (Microstar Laboratories) < ile...@mstarlabs.com> wrote: > > > The real problem comes with our potential OEM and VAR customers - the most > valuable customers for our potential product from a turnover perspective. > If we attempt to sell them a GPL

Re: [coreboot] How to properly conform with GPLv2 for Coreboot and SeaBIOS on an embedded system

On Fri, Dec 29, 2017 at 3:55 PM Lewis, Ian (Microstar Laboratories) < ile...@mstarlabs.com> wrote: > > > > First we need to figure out whether we are willing/able to move forward > with a product that includes GPL licensed code at all. > this part I do not understand. There are so many embedded

Re: [coreboot] How to properly conform with GPLv2 for Coreboot and SeaBIOS on an embedded system

suggestion: you might want to figure out what subset of the source you actually use in your product, i.e. what files are used in your build, then create a subset of the coreboot source tree containing only this files, then lzma -9 that file. I suspect it would be pretty small, but if you want to

Re: [coreboot] Coreboot with an UEFI payload to boot (Clover) an Thinkpad X230 Hackintosh

Fred, thanks for the update. I was double checking because, believe it or not, we have had a surprising number of people in the last 18 years ask how they could install coreboot to run under linux ... :-) nice work on getting the x230 as far as you have! -- coreboot mailing list:

Re: [coreboot] Coreboot with an UEFI payload to boot (Clover) an Thinkpad X230 Hackintosh

On Fri, Dec 29, 2017 at 9:15 AM my First name is Test And my last Name is iPation wrote: > > Then I've went through the process of installing Coreboot/Seabios + > Ubuntu on another disk, and it works like a charm too! > this sentence makes no sense to me. You don't

[coreboot] smd work

A friend of mine wants to do some SPI rework. He wants a 16M part in his chromebook, not 8M. (hmm, so do I). Given the huge expertise of this group, I wonder if you have advice about equipment he should get. Soldering irons? hot air guns? magic wands? thanks ron -- coreboot mailing list:

[coreboot] anyone know what happened here?

http://www.theregister.co.uk/2017/12/21/ubuntu_lenovo_bios/ -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Depthcharge License

Is there even a question? Looks like aaron just answered the original question, which boils down to Read The Source? On Tue, Dec 19, 2017 at 7:58 AM Aaron Durbin via coreboot < coreboot@coreboot.org> wrote: > On Tue, Dec 19, 2017 at 8:03 AM, wrote: > >> On 2017-12-15

Re: [coreboot] [LinuxBoot] Move LinuxBoot mailing list to Mailman

at the moment, nobody wanted to move it, since it's working for all of us. We're all short of time. Sorry. On Tue, Dec 5, 2017 at 12:24 AM Paul Menzel < paulepan...@users.sourceforge.net> wrote: > Dear Ron, > > > Am Montag, den 04.12.2017, 15:58 + schrieb ron minnich: >

Re: [coreboot] Early debugging

don't forget, you can write code that runs in user mode and drives the superio. This is a handy way to test superio chips you're not sure about. use iopl(3) to enable arbitrary Io port access, then inb/outb to try to get some idea what's going on. This is obviously a little limited, since the

Re: [coreboot] LinuxBoot (was: [RFC] Revive LinuxBIOS as new project for Linux in flash ROM chip)

On Mon, Dec 4, 2017 at 12:37 AM Paul Menzel < paulepan...@users.sourceforge.net> wrote: > > I can’t find the mailing list. Could you please share the URL (and put > the list in CC)? > > https://groups.google.com/forum/#!forum/linuxboot I sent an invite to you, Paul! > Regarding the content of

Re: [coreboot] freebsd

if you watch netflix, you're using freebsd. It's a very solid piece of software. -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Coreboot Bios Compatibility

I'll also repeat the advice I always give: BEFORE you start a new, untested mainboard, follow the entire process of creating coreboot for a known good mainboard. You'll probably make all the mistakes I still make, and it's much easier to work on a tested mainboard first. This is not like

Re: [coreboot] freebsd

I am a huge fan of freebsd, and a former contributor to that kernel (from the 90s :-) so I am happy to see someone working on it! On Sun, Dec 3, 2017 at 9:30 AM Vincenzo Di Salvo wrote: > Hello guys, > > > > thanks very much for your replies. I've contacted you

Re: [coreboot] [RFC] Revive LinuxBIOS as new project for Linux in flash ROM chip

Over the last few months I discussed reviving the LinuxBIOS name with a number of folks inside and outside the coreboot community. I still pretty much own the name: for old times's sake I kept the LinuxBIOS Inc. corporation and linuxbios.org domain name. There was a strong feeling that using the

[flashrom] winbond 25q128jvfm

any suggestions on making this part work? I have not done this in a while. ___ flashrom mailing list flashrom@flashrom.org https://mail.coreboot.org/mailman/listinfo/flashrom

Re: [coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)

On Fri, Nov 3, 2017 at 5:54 AM Zoran Stojsavljevic < zoran.stojsavlje...@gmail.com> wrote: > > > Your guy Stefan is here, asking for a help. Stefan got the straight > answer: FSP/Coreboot (intermingled), then U_Boot as payload... You got that? > > > Stefan got a suggestion from me that running

Re: [coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)

On Thu, Nov 2, 2017 at 8:44 AM Stefan Roese wrote: > > > In this special case, I might have triggered a bug / issue in the Intel > FSP and solving this might also help the coreboot project / community. > > > Sounds good to me. I have no complaint with what you're doing; the more

Re: [coreboot] BayTrail PCIe problems (hangup) in FSP (in U-Boot)

Simon Glass has done excellent work with making u-boot run as a coreboot payload for at least 5 years now. You might want to talk to him. It might help avoid a lot of unnecessary work. Just a thought. On Thu, Nov 2, 2017 at 7:31 AM Peter Stuge wrote: > Hi Stefan, > > Stefan

Re: [coreboot] a blast from the past

It's weird how this issue never went away. I had forgotten ever giving that talk. And yet everything it says is current 12 years later ... On Sat, Oct 28, 2017 at 8:39 AM Alberto Bursi <alberto.bu...@outlook.it> wrote: > > > On 10/28/2017 03:27 PM, ron minnich wrote: > > 200

[coreboot] riscv talk

https://www.youtube.com/watch?v=HHABypJWMYk from andrew waterman, a good overview. -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

[coreboot] a blast from the past

2005, los alamos, a talk on EFI I had forgotten I had done. https://www.coreboot.org/images/d/d1/Openefi.pdf relevant to the current era. -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

we had a similar problem and we set pci=nocrs which means 'ignore what ACPI tells you and probe it again" It's much less of a big hammer than 'acpi=off' :-) On Thu, Oct 19, 2017 at 7:22 AM Аладышев Константин wrote: > I've found one more parameter that helps me boot

Re: [coreboot] greetings and laptop questions

let's pause this discussion until the new mailing list is up, and then move it there, ok? This is not technical. It's decreasing the signal to noise ratio on this list. Thanks On Tue, Oct 10, 2017 at 8:55 PM Zoran Stojsavljevic < zoran.stojsavlje...@gmail.com> wrote: > > Sorry for that. My last

Re: [coreboot] OCP Winterfell, NERF, Linux and u-root (was: Ability to remotely debug the grub menu in case of boot failure)

Here's a bit more info. NERF is the project I mentioned at the coreboot meeting a few months back. This is my linuxcon talk a few weeks back. https://docs.google.com/presentation/d/1rz6ATJ6PNf_iJeDlqJvLqYZmyuJIN5SMli8halvyovY/edit?usp=sharing HOWTO on the winterfell node, incomplete:

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

[0.376881] ACPI Error: Hardware did not enter ACPI mode (20160831/evxfevnt-113) is this the step where it tries to do an outb to 0xb2 to tell smm we are taking over? -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] USB problem with Haswell+LynxPointLP motherboards

this kind of thing is pretty common. Linux has intermittent problems working on machines built without a real(TM) bios. Few people test in unnatural(TM) coreboot environments so you see errors you might not expect. I've had this off and on since we started in 1999 On Mon, Oct 9, 2017 at 5:26

[coreboot] SMM save area in MSRs on newer intel CPUs

can someone point me at the documents that describe how this works? thanks ron -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] Ability to remotely debug the grub menu in case of boot failure

On Fri, Oct 6, 2017 at 6:54 AM Zoran Stojsavljevic < zoran.stojsavlje...@gmail.com> wrote: > > as always, your other other choice is to use linux in flash as a > bootstrap, and then have the full spectrum of x-over-network solutions that > you get from that. That's my new (old) approach nowadays.

Re: [coreboot] Ability to remotely debug the grub menu in case of boot failure

On Fri, Oct 6, 2017 at 3:22 AM Anshuman Aggarwal < anshuman.aggar...@gmail.com> wrote: > Ron, > Do you have any link to point me towards developing this solution. I > get at a high level what you are suggesting but would like to reuse > whatever work has already been done towards this. If the

Re: [coreboot] Ability to remotely debug the grub menu in case of boot failure

On Thu, Oct 5, 2017 at 2:55 AM Anshuman Aggarwal < anshuman.aggar...@gmail.com> wrote: > > > @ron, I assume you mean a livecd like alternative which I can connect > to and use to debug the issue? > no, I mean putting the kernel in firmware and using the network as the equivalent of a serial

Re: [coreboot] Ability to remotely debug the grub menu in case of boot failure

as always, your other other choice is to use linux in flash as a bootstrap, and then have the full spectrum of x-over-network solutions that you get from that. That's my new (old) approach nowadays. -- coreboot mailing list: coreboot@coreboot.org

Re: [coreboot] INT 13, real mode, block write commands and coreboot

On Thu, Sep 7, 2017 at 7:44 PM taii...@gmx.com wrote: > (side > question - how come so many laymen think it is an open source hardware?) > > marketing, I think. -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] [kernel-hardening] ME and PSP

On Thu, Sep 7, 2017 at 11:03 AM Timothy Pearson < tpear...@raptorengineering.com> wrote: > could anyone shed some light on these decision making > processes? An open ISA and core design does not guarantee open silicon, > and in fact one could argue that it will mean any performance >

Re: [coreboot] Moving the command line for Linux kernel payloads

It's a great idea. On Thu, Sep 7, 2017 at 6:29 AM Patrick Georgi via coreboot < coreboot@coreboot.org> wrote: > 2017-09-07 0:09 GMT+02:00 Trammell Hudson : > > Is there a current or historical reason for the ordering? > The reason for this order is that there had to be _some_

Re: [coreboot] [kernel-hardening] ME and PSP

On Thu, Sep 7, 2017 at 1:07 AM Shawn wrote: > > RISC-V doesn't have NDA issues like x86 which the firmware freedom > will get benefit of it. > Speaking as someone who has been working on and off with riscv for almost four years, and who has ported coreboot several times and

Re: [coreboot] About Paging, Realmode and what is going on

On Thu, Sep 7, 2017 at 1:43 AM Zoran Stojsavljevic < zoran.stojsavlje...@gmail.com> wrote: > > Please, could you try to do this with INTEL ATOM or CORE in this time for > this price? ;-) > > > This is a very interesting point about time to market, which is everything nowadays. I regret that ARM

Re: [coreboot] [kernel-hardening] ME and PSP

On Wed, Sep 6, 2017 at 8:07 PM Shawn wrote: > > IMOHO, RISC-V will be the long-term solution in the future;-) > > people need to stop saying that. It's not that simple. And, sadly, riscv may be baking in an SMM-like mode that you can't turn off. RISCV is neat but it's nowhere

Re: [coreboot] About Paging, Realmode and what is going on

The original statement about BIOS -- that it was a second OS from the first day on -- is not correct. I am pretty sure the term BIOS (Basic Input Output Subsystem) comes from the early days, from CP/M. That's when I started hearing it anyway. The BIOS was the bottom half of CP/M. It provided an

Re: [coreboot] About Paging, Realmode and what is going on

On Mon, Sep 4, 2017 at 3:41 PM Philipp Stanner wrote: > > Start the board, load the OS and go back into your flash until reboot. > Just checking, but have you looked at the code to see what "start the board" really means? Hint: on x86 it's essentially one billion instructions

[coreboot] was this a UEFI update maybe?

https://www.theguardian.com/technology/2017/aug/24/samsung-tv-buyers-furious-after-software-update-leaves-sets-unusable -- coreboot mailing list: coreboot@coreboot.org https://mail.coreboot.org/mailman/listinfo/coreboot

Re: [coreboot] How is depreciating 95% of coreboot boards worth it for such minor improvements?

On Wed, Aug 23, 2017 at 2:31 PM taii...@gmx.com wrote: > Ah I see thanks for explaining. > > I had read all the AGESA boards were going to be removed, besides the > asus D8/D16 those are the last and best owner controlled x86 boards. > Is there a current list of boards to be

Re: [coreboot] How is depreciating 95% of coreboot boards worth it for such minor improvements?

I am always sad to see boards go away, especially since it means that the amount of coreboot I still have code in is smaller by the month, but ... there's a real opportunity cost to keeping old boards in. We've had cases where a new, useful feature has to be implemented as a config variable since

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