I wrote a similar patch in the past but I didn't notice any improvements.
Though, as we already check state changes in some other places, I think
it's better to be consistent.
With the TODO comment removed, patch is:
Reviewed-by: Samuel Pitoiset
On 1/15/19 10:59 PM, Rhys Perry wrote:
DXVK
Ported from RadeonSI.
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_nir_to_llvm.c | 20 +++-
1 file changed, 15 insertions(+), 5 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 81a4149c321..bcec66fa107 100644
--- a/src
Fix crashes with
dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.*16
v2: - add INT16/UINT16 too
- update commit description
Signed-off-by: Samuel Pitoiset
Reviewed-by: Bas Nieuwenhuizen (v1)
---
src/amd/common/ac_nir_to_llvm.c | 5 +
1 file changed, 5 insertions(+)
diff
with Dota 2 but I've heard it's cpu-bound.
On Mon, 14 Jan 2019 at 16:05, Samuel Pitoiset wrote:
Did you benchmark?
On 1/14/19 5:01 PM, Rhys Perry wrote:
It's common in some applications to bind a new graphics pipeline without
ending up changing any context registers.
This has a pipline have two
Did you benchmark?
On 1/14/19 5:01 PM, Rhys Perry wrote:
It's common in some applications to bind a new graphics pipeline without
ending up changing any context registers.
This has a pipline have two command buffers: one for setting context
registers and one for everything else. The context
Fix a crash with
dEQP-VK.spirv_assembly.instruction.compute.workgroup_memory.float16
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_nir_to_llvm.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 5023b96f92d
I haven't played with merge requests yet, except for reviewing some
small RADV patches from Bas.
From my point of view, the main problem now is that we have to look
both at the mailing list and at the merge requests page and that's quite
annoying.
I don't think it's really a win to have two
struct ac_shader_abi {
* driver_location.
*/
LLVMValueRef *inputs;
newline
Also, missing Fixes tag?
Other than that, patch is:
Reviewed-by: Samuel Pitoiset
+ /* Varying -> attribute number mapping. Also NIR-only */
+ unsigned fs_input_attr_indices[
These functions return nothing.
v2: - do it for GetPhysicalDeviceQueueFamilyProperties too
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
heaps in the winsys
- improve budget/usage computations based on these counters
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 72 +++
src/amd/vulkan/radv_extensions.py | 1 +
src/amd/vulkan/radv_radeon_winsys.h | 4
Loosely based on RadeonSI.
v2: - do not check for indexed draws
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index d1b8b3dee6a
/usage computations based on these counters
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 72 +++
src/amd/vulkan/radv_extensions.py | 1 +
src/amd/vulkan/radv_radeon_winsys.h | 4 ++
src/amd/vulkan/winsys/amdgpu
hould turn on the
extension feature as well.
All dEQP-VK.spirv_assembly.instruction.compute.variable_pointers.*
pass with the khronos internal repo. Note that a bunch of them
fails with the public repo, but it's expected as they violate the
specification.
Signed-off-by: Samuel Pitoiset
---
src/
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_android.c| 18 +--
src/amd/vulkan/radv_cmd_buffer.c | 4 +-
src/amd/vulkan/radv_descriptor_set.c | 22 ++--
src/amd/vulkan/radv_device.c | 176 +--
src/amd/vulkan/radv_formats.c| 82
how we can be accurate for the
visible VRAM heap.
As said in the commit description, that implementation is really
inacurate. Though if you need something better I can improve.
Note that I agree with you about the spec.
Alex
On Mon, 7 Jan 2019 at 16:35, Samuel Pitoiset
mailto:samuel.pitoi
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 21 -
1 file changed, 16 insertions(+), 5 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 39bd47348a9..cef3a430555 100644
--- a/src/amd/vulkan/radv_device.c
+++ b
A simple Vulkan extension that allows apps to query size and
usage of all exposed memory heaps.
The different usage values are not really accurate because
they are per drm-fd, but they should be close enough.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 44
This function returns nothing.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 53aed1a15db..39bd47348a9 100644
--- a/src/amd/vulkan
On 1/7/19 2:53 PM, Bas Nieuwenhuizen wrote:
On Mon, Jan 7, 2019 at 2:45 PM Samuel Pitoiset
wrote:
Loosely based on RadeonSI.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/amd/vulkan
Acked-by: Samuel Pitoiset
On 1/7/19 4:39 PM, Jason Ekstrand wrote:
---
include/vulkan/vulkan.h | 2 +-
include/vulkan/vulkan_android.h | 2 +-
include/vulkan/vulkan_core.h| 155 +++-
include/vulkan/vulkan_fuchsia.h | 2 +-
include
Loosely based on RadeonSI.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 1966098e08c..8e3f1a7f5f0 100644
--- a/src/amd/vulkan
Reviewed-by: Samuel Pitoiset
On 12/24/18 3:43 PM, Bas Nieuwenhuizen wrote:
We started using it in the btoi paths for r32g32b32, and the LLVM IR
checker will complain about it because we end up with intrinsics with
the wrong type extension in the name.
Fixes: 593996bc02 ("radv: impl
Feel free to add my Rb if you want to push this now.
Reviewed-by: Samuel Pitoiset
On 12/20/18 4:12 PM, Alex Deucher wrote:
Signed-off-by: Alex Deucher
Cc: mesa-sta...@lists.freedesktop.org
---
include/pci_ids/radeonsi_pci_ids.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include
:23 PM Samuel Pitoiset
wrote:
This fixes GPU hangs on GFX9 with
dEQP-VK.memory.external_memory_host.bind_image_memory_and_render.with_zero_offset.*
Copied from RadeonSI.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 28 ++-
1 file changed
This fixes GPU hangs on GFX9 with
dEQP-VK.memory.external_memory_host.bind_image_memory_and_render.with_zero_offset.*
Copied from RadeonSI.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/winsys/amdgpu/radv_amdgpu_bo.c | 28 ++-
1 file changed, 27 insertions(+), 1 deletion
vk_format_get_blocksizebits(info->format) == 128 &&
+ vk_format_is_compressed(info->format) &&
+ (info->flags & VK_IMAGE_CREATE_BLOCK_TEXEL_VIEW_COMPATIBLE_BIT) &&
+ ((info->flags & VK_IMAGE_CREATE_EXTENDED_US
On 12/20/18 12:18 PM, Bas Nieuwenhuizen wrote:
Is not ideal but will have to do for now
Yes, this can be improved.
Reviewed-by: Bas Nieuwenhuizen
On Thu, Dec 20, 2018 at 12:01 PM Samuel Pitoiset
wrote:
The driver needs to decompress all image layers if a fast
depth/color clear has
The driver needs to decompress all image layers if a fast
depth/color clear has been performed.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan
This workaround has been introduced by 135e4d434f6 for fixing
DXVK GPU hangs with many games. It is no longer needed since
LLVM r345718.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_shader.c | 12 +---
1 file changed, 9 insertions(+), 3 deletions(-)
diff --git a/src/amd
This workaround has been introduced by 3d41757788a and it
is no longer needed since LLVM r346422.
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_nir_to_llvm.c | 24 +++-
1 file changed, 15 insertions(+), 9 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b
Original patch by Dave Airlie.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/Makefile.sources | 1 +
src/amd/vulkan/meson.build | 1 +
src/amd/vulkan/radv_cmd_buffer.c| 7 +
src/amd/vulkan/radv_meta.c | 8 +
src/amd/vulkan/radv_meta.h
Untested on older chips.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 4 ++--
src/amd/vulkan/radv_formats.c | 3 +--
src/amd/vulkan/radv_shader.c | 1 +
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan
The value depends on the number of samples.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 25 +
src/amd/vulkan/radv_meta.h | 2 ++
src/amd/vulkan/radv_meta_clear.c | 9 +
src/amd/vulkan/radv_private.h| 3 +++
4 files changed
We don't ever want to do the fmask lookup on a atomic or
store, the fmask should have been decompressed if the
surface has been moved to IMAGE_LAYOUT.
Original patch by Dave Airlie.
Signed-off-by: Samuel Pitoiset
---
src/amd/common/ac_nir_to_llvm.c | 2 +-
1 file changed, 1 insertion(+), 1
Signed-off-by: Samuel Pitoiset
---
src/compiler/shader_info.h| 1 +
src/compiler/spirv/spirv_to_nir.c | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index b21db3e60f0..05f37c8d197 100644
--- a/src/compiler
Hi,
This small series enables shaderStorageImageMultisample on GFX8+.
This series is originally based on Dave Airlie's work, but I made
some changes to make it work.
Please review,
Thanks!
Samuel Pitoiset (5):
spirv: add support for SpvCapabilityStorageImageMultisample
ac/nir: restrict
Reviewed-by: Samuel Pitoiset
On 12/14/18 7:32 PM, Rhys Perry wrote:
Fixes: f8d5b377c8b ('radv: set cb base tile swizzles for MRT speedups (v4)')
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108116
Signed-off-by: Rhys Perry
---
Unfortunately I was not able to test this patch
On 12/13/18 9:27 PM, Gert Wollny wrote:
IMHO allowing MRs is a good thing, so
Acked-by: Gert Wollny
Allowing MRs isn't a bad thing. The main problem IMHO is that now we
have to look at both emails and MRs, and I think we are probably going
to miss interesting/important changes.
I've
I thought the value was correctly propagated, but actually not.
Fixes: 2ac6d55f38c ("radv: bump reported version to 1.1.90")
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_extensions.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_ext
See my comment on the first patch. Anyways, series is:
Reviewed-by: Samuel Pitoiset
On 12/13/18 6:06 PM, Rhys Perry wrote:
Fixes: 7e7ee826982 ('ac: add support for 16bit buffer loads')
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108114
Signed-off-by: Rhys Perry
---
src/amd
On 12/13/18 6:06 PM, Rhys Perry wrote:
This is so that we can split different types of loads more easily.
Signed-off-by: Rhys Perry
---
src/amd/common/ac_llvm_build.c | 8 ++--
src/amd/common/ac_nir_to_llvm.c | 80 -
src/compiler/nir/nir.h | 2
ones) results in an assert.
Just tried to reproduce with a LLVM 8 debug build, I don't get an
assertion. Maybe I messed up my build too?
On Thu, 13 Dec 2018 at 08:38, Samuel Pitoiset wrote:
On 12/6/18 3:18 PM, Rhys Perry wrote:
./deqp-vk
--deqp-case=dEQP
This introduces crashes for
dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order_frag
dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order_geom
dEQP-VK.spirv_assembly.instruction.graphics.selection_block_order.out_of_order_tessc
uild? Can you figure out what change
introduces this crash?
On Thu, 6 Dec 2018 at 13:31, Samuel Pitoiset wrote:
On 12/6/18 2:15 PM, Rhys Perry wrote:
So that the signature is correct and consistent, the inputs to a export
intrinsic should always be 32-bit floats.
This and
This refactoring is really not easy to read as is. Can you please split
this in different parts? Maybe refactor first, then fix 16-bit ssbo loads?
If we want this to be backported, we will just need to squash the
different parts and send a separate patch to mesa-stable.
On 12/6/18 12:13 AM,
Reviewed-by: Samuel Pitoiset
On 12/13/18 4:32 AM, Dave Airlie wrote:
From: Dave Airlie
If we gave this function 0 counter buffers, we'd still try and
access pCounterBuffers[0] as this check was incorrect.
Fixes crash with ext_transform_feedback-pipeline-basic-primgen
on zink on radv.
Fixes
When hile_size is 0, we can't enable HTILE. This doesn't change
anything, except not calling radv_image_alloc_htile().
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_image.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd
This is always TRUE if htile_size is not 0.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_image.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index b1044639fdf..9b7564985a6 100644
--- a/src/amd/vulkan/radv_image.c
+++ b
What's the point of maintaining Travis? Shouldn't we just drop it in
favour of Gitlab CI? IIRC, Igalia worked on it.
On 12/12/18 8:45 AM, Rhys Kidd wrote:
Emil and Dylan,
I took a go at addressing the limited number of remaining meson-based
travis-ci errors. This series applies on top of the
Personally, I will continue to use the list, at least for a simplicity
point of view. I'm not sure if using a new tool will improve quality and
code review process.
Though, if the majority reports that is really nice to use, I will
probably change my mind. Not a strong reject.
On 12/6/18
On 12/11/18 7:18 PM, Eric Anholt wrote:
Emil Velikov writes:
On Mon, 10 Dec 2018 at 23:11, Dylan Baker wrote:
Meson 0.49.0 has been out for a couple of days now, and I'd like to make the
final call for autotools. My patch is so massive that it's a huge pain to send
to the list, the
by reporting VM faults. This is probably because the
hardware uses 32-bit instead of 16-bit. Anyways, decompressing
a surface when no Z planes are compressed is just dumb.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107563
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan
, Dec 11, 2018 at 10:08 AM Samuel Pitoiset
mailto:samuel.pitoi...@gmail.com>> wrote:
ping?
After looking into this again today, I can't find any better solutions.
We should probably push this patch because at least two games are
affected. My opinion is that correctness i
ping?
After looking into this again today, I can't find any better solutions.
We should probably push this patch because at least two games are
affected. My opinion is that correctness is more important than performance.
On 10/11/18 10:42 AM, Samuel Pitoiset wrote:
WD_SWITCH_ON_EOP seems
After going through the spec changelog, it looks like RADV
is up to date. Note that ANV also reports 1.1.90.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_extensions.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_extensions.py
b/src/amd
It's somehow similar to the FCE predicate.
v2: set the predicate to TRUE when drawing with DCC enabled
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 28 +++
src/amd/vulkan/radv_image.c | 3 ++-
src/amd/vulkan/radv_meta_clear.c
Acked-by: Samuel Pitoiset
On 12/10/18 6:04 PM, Jason Ekstrand wrote:
The Vulkan working group recently discovered that we made a mistake in
assuming that PCI domains are 16-bit even though they can potentially be
32-bit values. To fix this, the next spec update will chang the types
Acked-by: Samuel Pitoiset
On 12/10/18 6:21 AM, Rhys Kidd wrote:
Fixes: 3fbdcd942fe ("amd: remove support for LLVM 6.0")
Cc: Samuel Pitoiset
Cc: Marek Olšák
Cc: Emil Velikov
Cc: Jan Vesely
Cc: Andres Gomez
Cc: Dylan Baker
Signed-off-by: Rhys Kidd
---
.travi
, so you might already know
about some of these though (unless you were just talking about the
variableSampleLocations thing).
On Fri, 7 Dec 2018 at 16:19, Samuel Pitoiset wrote:
Basically, this extension allows applications to use custom
sample locations. This only implements the barely minimum
untested on older chips.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 177 +-
src/amd/vulkan/radv_device.c | 27 +
src/amd/vulkan/radv_extensions.py | 1 +
src/amd/vulkan/radv_pipeline.c| 30 +
src/amd/vulkan/radv_private.h
Fixes: 2710c40e3c8 ("gallium: Add new PIPE_CAP_SURFACE_SAMPLE_COUNT")
Signed-off-by: Samuel Pitoiset
---
src/gallium/auxiliary/util/u_screen.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/gallium/auxiliary/util/u_screen.c
b/src/gallium/auxiliary/util/u_screen.c
index 7
On 12/6/18 2:15 PM, Rhys Perry wrote:
So that the signature is correct and consistent, the inputs to a export
intrinsic should always be 32-bit floats.
This and the previous commit fixes a large amount crashes from
dEQP-VK.spirv_assembly.instruction.graphics.16bit_storage.input_output_int_*
On 12/5/18 7:24 PM, Juan A. Suarez Romero wrote:
On Wed, 2018-12-05 at 09:52 +, Alex Smith wrote:
As done for vkCmdBeginQuery() already. Prevents timestamps from being
overwritten by previous vkCmdResetQueryPool() calls if the shader path
was used to do the reset.
Bugzilla:
So my compiler doesn't want to show me warnings? That's something I
would need to fix up. Anyways,
Reviewed-by: Samuel Pitoiset
On 12/5/18 4:44 PM, Eric Engestrom wrote:
Added in 824cfc1ee5e0aba15b676 "radv: rework the TC-compat HTILE
hardware bug with COND_EXEC", but it is unuse
Hi Emil,
Yeah, that looks correct, Thanks!
On 12/5/18 4:22 PM, Emil Velikov wrote:
Hi guys
On Wed, 5 Dec 2018 at 10:49, Bas Nieuwenhuizen wrote:
Reviewed-by: Bas Nieuwenhuizen
On Wed, Dec 5, 2018 at 11:43 AM Samuel Pitoiset
wrote:
In case we are unlucky if the low part is 0x
Required for VK_KHR_shader_atomic_int64.
Signed-off-by: Samuel Pitoiset
---
src/compiler/shader_info.h| 1 +
src/compiler/spirv/spirv_to_nir.c | 5 -
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index
Nothing to do, the compiler already handles that.
All new dEQP.VK.ubo.* and dEQP.VK.ssbo.* pass, except some
16-bit tests that are quite related to fdo bug #108114.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_device.c | 6 ++
src/amd/vulkan/radv_extensions.py | 1 +
2 files
In case we are unlucky if the low part is 0x.
Fixes: 5d6a560a29 ("radv: do not use the availability bit for timestamp
queries")
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_query.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/
If the driver used a compute shader for resetting a query pool,
it should be completed when caches are flushed.
This might reduce the number of stalls if operations are done
between vkCmdResetQueryPool() and vkCmdBeginQuery()
(or vkCmdWriteTimestamp()).
Signed-off-by: Samuel Pitoiset
---
src
.
On Wed, 5 Dec 2018 at 10:04, Samuel Pitoiset <mailto:samuel.pitoi...@gmail.com>> wrote:
Yes, this is correct, indeed.
The issue wasn't present because we used EOP events before removing the
availability bit.
Btw, just noticed that we should reset pending_reset_query
DMA operations are currently always sync'ed,
while CP DMA copies are not. I plan to change this at some point.
Reviewed-by: Samuel Pitoiset
On 12/5/18 10:52 AM, Alex Smith wrote:
As done for vkCmdBeginQuery() already. Prevents timestamps from being
overwritten by previous vkCmdResetQueryPool
On 12/3/18 11:21 PM, Bas Nieuwenhuizen wrote:
On Mon, Dec 3, 2018 at 11:13 PM Samuel Pitoiset
wrote:
After investigating on this, it appears that COND_WRITE doesn't
work correctly in some situations. I don't know exactly why does
it fail to update DB_Z_INFO.ZRANGE_PRECISION, but as AMDVLK
is actually an availability bit. This
bit is allocated at creation time and always cleared before
emitting the EOP event.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108925
Fixes: 5d6a560a29 ("radv: do not use the availability bit for timestamp
queries")
Signed-off-by: Samuel Pitoiset
://bugs.freedesktop.org/show_bug.cgi?id=108914
Fixes: 68dead112e7 ("radv: update the ZRANGE_PRECISION value for the TC-compat
bug")
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 91 ++--
src/amd/vulkan/radv_image.c | 10 +++-
src/amd/vulkan/radv
Patches 1&2 are:
Acked-by: Samuel Pitoiset
Patch 3 is:
Reviewed-by: Samuel Pitoiset
On 11/26/18 4:26 PM, Bas Nieuwenhuizen wrote:
Fixes: b1444c9ccb0 "radv: Implement VK_ANDROID_native_buffer."
---
src/amd/vulkan/radv_android.c | 12 +++-
1 file changed, 11 in
Acked-by: Samuel Pitoiset
On 12/3/18 5:06 PM, Jason Ekstrand wrote:
---
include/vulkan/vulkan_core.h | 109 +++--
src/vulkan/registry/vk.xml | 130 +++
2 files changed, 204 insertions(+), 35 deletions(-)
diff --git a/include/vulkan
Reviewed-by: Samuel Pitoiset
On 12/3/18 5:38 AM, Dave Airlie wrote:
From: Dave Airlie
This fixes some crucible 3d miptree tests I've been working on
when executed using the compute shader path.
Fixes: d08f267814 (radv/gfx9: fix 3d image to image transfers on compute
queues.)
---
src/amd
On 12/1/18 3:36 PM, Connor Abbott wrote:
On Sat, Dec 1, 2018 at 3:22 PM Samuel Pitoiset
wrote:
I'm not saying this series is the right thing to do. It just fixes two
test failures in the vkd3d testsuite for RADV. I added a new compiler
option to not break anything and to only affects RADV
are already flagged
"inexact" (that's what the ~ means) so they won't apply to anything
that's "precise" or "invariant".
On Thu, Nov 29, 2018 at 9:18 AM Samuel Pitoiset
mailto:samuel.pitoi...@gmail.com>> wrote:
It's correct in GLSL because the behaviour
It's correct in GLSL because the behaviour is undefined in
presence of NaNs. But this seems incorrect in Vulkan.
Signed-off-by: Samuel Pitoiset
---
src/compiler/nir/nir.h| 6 ++
src/compiler/nir/nir_opt_algebraic.py | 8
2 files changed, 10 insertions(+), 4
ze: 44707992 -> 44635672 (-0.16 %) bytes
Max Waves: 219539 -> 219529 (-0.00 %)
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_shader.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index 456c462a230..
cc stable?
Reviewed-by: Samuel Pitoiset
On 11/24/18 11:31 PM, Bas Nieuwenhuizen wrote:
Mirrors AMDVLK. Looks like if we go over the alignment of height
we actually start to change the addressing. Seems like the extra
miplevels actually work with this.
Bugzilla: https://bugs.freedesktop.org
Apparently some games allocate depth buffers without rendering
to them, this will avoid wasting memory if that image usage
flag is not set.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_image.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan
Currently only true if RADV_PERFTEST=dccmsaa is set.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_clear.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 6c8ef4958f2..37b743e994a
The driver doesn't support DCC/CMASK for mipmapped textures.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_clear.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index f2f5cb32eb9..26bc5e75ef3 100644
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_clear.c | 78
1 file changed, 40 insertions(+), 38 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 37b743e994a..d4da614584b 100644
--- a/src/amd
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_clear.c | 68 ++--
1 file changed, 39 insertions(+), 29 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 26bc5e75ef3..d9acd194ce5 100644
--- a/src/amd
For further optimisations.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_clear.c | 133 +--
1 file changed, 89 insertions(+), 44 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 9c124c9b677
is obviously faster.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_clear.c | 90 ++--
1 file changed, 86 insertions(+), 4 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index d4da614584b..83d4b071d52 100644
--- a/src
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_clear.c | 47 ++--
1 file changed, 27 insertions(+), 20 deletions(-)
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index d9acd194ce5..9c124c9b677 100644
--- a/src/amd
We really need to refactor this...
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pass.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src/amd/vulkan/radv_pass.c b/src/amd/vulkan/radv_pass.c
index f8e5ea40954..b41ae89deec 100644
--- a/src/amd/vulkan/radv_pass.c
+++ b
We don't need to flush anything before these two commands as well.
This is because they have to be externally synchronized, so the
app should have called CmdPipelineBarrier() prior to that and the
driver should have flushed the caches.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan
Oops.
I was not planning to send this one. Please ignore.
On 11/22/18 7:10 PM, Samuel Pitoiset wrote:
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 23 +++
src/amd/vulkan/radv_device.c | 4 ++
src/amd/vulkan/radv_meta.c| 2 +
src
Viewport/scissor don't need to be updated for array textures.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_decompress.c | 47 +--
src/amd/vulkan/radv_meta_fast_clear.c | 55 +++
2 files changed, 41 insertions(+), 61 deletions(-)
diff
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 17 ++---
1 file changed, 6 insertions(+), 11 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 7367e24fd28..1e7954434fe 100644
--- a/src/amd/vulkan
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 23 +++
src/amd/vulkan/radv_device.c | 4 ++
src/amd/vulkan/radv_meta.c| 2 +
src/amd/vulkan/radv_meta_buffer.c | 6 ++
src/amd/vulkan/radv_meta_clear.c | 11
src/amd/vulkan
Feral games aren't affected because they don't decompress DCC.
F1 2018 has one DCC decompression per frame, but I don't see
any performance improvements. This new predicate will be
probably more useful for DCC/MSAA.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_meta_fast_clear.c | 19
It's somehow similar to the FCE predicate.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_cmd_buffer.c | 23 +++
src/amd/vulkan/radv_image.c | 3 ++-
src/amd/vulkan/radv_meta_clear.c | 3 +++
src/amd/vulkan/radv_meta_fast_clear.c | 7
Reviewed-by: Samuel Pitoiset
On 11/22/18 1:52 AM, Timothy Arceri wrote:
Being able to see improvements as well as regressions is useful
during the development of shader opts.
Ported from commit 8f0c7aca8683 in shader-db
---
radv-report.py | 30 ++
1 file changed
to set those flags internallY.
VK_PIPELINE_STAGE_TRANSFER_BIT will wait for compute to be idle,
while VK_ACCESS_TRANSFER_WRITE_BIT will invalidate both L1 vector
caches and L2. RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 will be superseded
by RADV_CMD_FLAG_INV_GLOBAL_L2.
Signed-off-by: Samuel Pitoiset
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