On Thu, Oct 11 2018 at 11:37 -0600, Sudeep Holla wrote:
On Thu, Oct 11, 2018 at 10:58:22AM -0600, Lina Iyer wrote:
On Thu, Oct 11 2018 at 10:19 -0600, Sudeep Holla wrote:
> On Thu, Oct 11, 2018 at 10:00:53AM -0600, Lina Iyer wrote:
> > Sudeep,
> >
> > The CPU PD does not
On Thu, Oct 11 2018 at 11:37 -0600, Sudeep Holla wrote:
On Thu, Oct 11, 2018 at 10:58:22AM -0600, Lina Iyer wrote:
On Thu, Oct 11 2018 at 10:19 -0600, Sudeep Holla wrote:
> On Thu, Oct 11, 2018 at 10:00:53AM -0600, Lina Iyer wrote:
> > Sudeep,
> >
> > The CPU PD does not
On Thu, Oct 11 2018 at 10:19 -0600, Sudeep Holla wrote:
On Thu, Oct 11, 2018 at 10:00:53AM -0600, Lina Iyer wrote:
Sudeep,
The CPU PD does not power off the domain from Linux. That is done from
PSCI firmware (ATF). These patches are doing the part that Linux has do,
when powering off the CPUs
On Thu, Oct 11 2018 at 10:19 -0600, Sudeep Holla wrote:
On Thu, Oct 11, 2018 at 10:00:53AM -0600, Lina Iyer wrote:
Sudeep,
The CPU PD does not power off the domain from Linux. That is done from
PSCI firmware (ATF). These patches are doing the part that Linux has do,
when powering off the CPUs
to power off the domain from the firmware. However, Linux has
responsibilities that it needs to complete before the power down can be
beneficial.
3. Is this a shortcut approached taken to bypass the CPU genpd attempts
from Lina/Ulf ?
This is an incorrect interpretation and an unwarranted
to power off the domain from the firmware. However, Linux has
responsibilities that it needs to complete before the power down can be
beneficial.
3. Is this a shortcut approached taken to bypass the CPU genpd attempts
from Lina/Ulf ?
This is an incorrect interpretation and an unwarranted
.
Request the corresponding PDC IRQ, when the GPIO is requested as an IRQ,
but keep it disabled. During suspend, we can enable the PDC IRQ instead
of the GPIO IRQ, which may or not be detected.
Signed-off-by: Lina Iyer
---
Changes in v4:
- Redesign to use PDC interrupts instead of TLMM
see any
issues that I may have missed.
Thanks,
Lina
[1]. https://lkml.org/lkml/2018/9/4/846
Lina Iyer (1):
drivers: pinctrl: qcom: add wakeup capability to GPIO
drivers/pinctrl/qcom/pinctrl-msm.c | 91 +-
1 file changed, 90 insertions(+), 1 deletion
see any
issues that I may have missed.
Thanks,
Lina
[1]. https://lkml.org/lkml/2018/9/4/846
Lina Iyer (1):
drivers: pinctrl: qcom: add wakeup capability to GPIO
drivers/pinctrl/qcom/pinctrl-msm.c | 91 +-
1 file changed, 90 insertions(+), 1 deletion
.
Request the corresponding PDC IRQ, when the GPIO is requested as an IRQ,
but keep it disabled. During suspend, we can enable the PDC IRQ instead
of the GPIO IRQ, which may or not be detected.
Signed-off-by: Lina Iyer
---
Changes in v4:
- Redesign to use PDC interrupts instead of TLMM
On Tue, Oct 02 2018 at 11:06 -0600, Lina Iyer wrote:
Marc,
I am exploring an option where we don't do this enable/disable every
suspend/resume and in that process, I was able to just use the PDC
interrupt instead of the TLMM for triggering the GPIO. The PDC interrupt
(which takes over
On Tue, Oct 02 2018 at 11:06 -0600, Lina Iyer wrote:
Marc,
I am exploring an option where we don't do this enable/disable every
suspend/resume and in that process, I was able to just use the PDC
interrupt instead of the TLMM for triggering the GPIO. The PDC interrupt
(which takes over
at 15:18 -0600, Lina Iyer wrote:
QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on
domain can wakeup the SoC, when interrupts and GPIOs are routed to its
interrupt controller. Only select GPIOs that are deemed wakeup capable
are routed to specific PDC pins. During low power
at 15:18 -0600, Lina Iyer wrote:
QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on
domain can wakeup the SoC, when interrupts and GPIOs are routed to its
interrupt controller. Only select GPIOs that are deemed wakeup capable
are routed to specific PDC pins. During low power
Hi guys,
i would like to figure out how much time is left in one phase which started. So i wrote following code for this part:
traci.start(sumoCmd)
while i==0:
k+=1
traci.simulationStep()
if traci.trafficlight.getPhase("B") == 2:
timeleft =
On Fri, Sep 28 2018 at 04:40 -0600, Marc Zyngier wrote:
On 27/09/18 18:18, Lina Iyer wrote:
The PDC irqchp can convert a falling edge or level low interrupt to a
rising edge or level high interrupt at the GIC. We just need to setup
the GIC correctly. Set up the interrupt type
On Fri, Sep 28 2018 at 04:40 -0600, Marc Zyngier wrote:
On 27/09/18 18:18, Lina Iyer wrote:
The PDC irqchp can convert a falling edge or level low interrupt to a
rising edge or level high interrupt at the GIC. We just need to setup
the GIC correctly. Set up the interrupt type
The PDC irqchp can convert a falling edge or level low interrupt to a
rising edge or level high interrupt at the GIC. We just need to setup
the GIC correctly. Set up the interrupt type for the IRQ_TYPE_EDGE_BOTH
as IRQ_TYPE_EDGE_RISING at the GIC.
Reported-by: Evan Green
Signed-off-by: Lina Iyer
The PDC irqchp can convert a falling edge or level low interrupt to a
rising edge or level high interrupt at the GIC. We just need to setup
the GIC correctly. Set up the interrupt type for the IRQ_TYPE_EDGE_BOTH
as IRQ_TYPE_EDGE_RISING at the GIC.
Reported-by: Evan Green
Signed-off-by: Lina Iyer
Hi guys,
i would like to run my simulation but unfortuantely i get the error : Error: tcpip::Storage::readIsSafe: want to read 8 bytes from Storage, but only 4 remaining. Would you know the problem? Thanks a lot
___
sumo-user mailing list
approaches
toward wakeups in the kernel, so I included Lina, Marc and Ulf
to see if we can get some common understanding.
On Fri, Sep 21, 2018 at 12:25 PM Thierry Reding
wrote:
> The following is a set of patches that allow certain interrupts to be
> used as wakeup sources on Tegra186 and
approaches
toward wakeups in the kernel, so I included Lina, Marc and Ulf
to see if we can get some common understanding.
On Fri, Sep 21, 2018 at 12:25 PM Thierry Reding
wrote:
> The following is a set of patches that allow certain interrupts to be
> used as wakeup sources on Tegra186 and
On Sun, Sep 23 2018 at 03:48 -0600, Marc Zyngier wrote:
On Sat, 22 Sep 2018 18:09:09 +0100,
Lina Iyer wrote:
On Sat, Sep 22 2018 at 10:29 -0600, Marc Zyngier wrote:
> Hi Lina,
>
> On Tue, 04 Sep 2018 22:18:08 +0100,
> Lina Iyer wrote:
Also, I am exploring an option that w
On Sun, Sep 23 2018 at 03:48 -0600, Marc Zyngier wrote:
On Sat, 22 Sep 2018 18:09:09 +0100,
Lina Iyer wrote:
On Sat, Sep 22 2018 at 10:29 -0600, Marc Zyngier wrote:
> Hi Lina,
>
> On Tue, 04 Sep 2018 22:18:08 +0100,
> Lina Iyer wrote:
Also, I am exploring an option that w
On Sat, Sep 22 2018 at 10:29 -0600, Marc Zyngier wrote:
Hi Lina,
On Tue, 04 Sep 2018 22:18:08 +0100,
Lina Iyer wrote:
During suspend the system may power down some of the system rails. As a
result, the TLMM hw block may not be operational anymore and wakeup
capable GPIOs will not be detected
On Sat, Sep 22 2018 at 10:29 -0600, Marc Zyngier wrote:
Hi Lina,
On Tue, 04 Sep 2018 22:18:08 +0100,
Lina Iyer wrote:
During suspend the system may power down some of the system rails. As a
result, the TLMM hw block may not be operational anymore and wakeup
capable GPIOs will not be detected
On Fri, Sep 21 2018 at 17:11 -0600, Marc Zyngier wrote:
Hi Lina,
On Tue, 04 Sep 2018 22:18:06 +0100,
Lina Iyer wrote:
[...]
+static irqreturn_t wake_irq_gpio_handler(int irq, void *data)
+{
+ struct irq_data *irqd = data;
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd
On Fri, Sep 21 2018 at 17:11 -0600, Marc Zyngier wrote:
Hi Lina,
On Tue, 04 Sep 2018 22:18:06 +0100,
Lina Iyer wrote:
[...]
+static irqreturn_t wake_irq_gpio_handler(int irq, void *data)
+{
+ struct irq_data *irqd = data;
+ struct gpio_chip *gc = irq_data_get_irq_chip_data(irqd
On Wed, Sep 12 2018 at 16:28 -0600, Matthias Kaehlcke wrote:
On Fri, Jul 27, 2018 at 03:34:48PM +0530, Raju P L S S S N wrote:
From: Lina Iyer
The Power Domain Controller can be programmed to wakeup the RSC and
setup the resources back in the active state, before the processor is
woken up
On Wed, Sep 12 2018 at 16:28 -0600, Matthias Kaehlcke wrote:
On Fri, Jul 27, 2018 at 03:34:48PM +0530, Raju P L S S S N wrote:
From: Lina Iyer
The Power Domain Controller can be programmed to wakeup the RSC and
setup the resources back in the active state, before the processor is
woken up
On Tue, Sep 11 2018 at 17:02 -0600, Matthias Kaehlcke wrote:
Hi Raju/Lina,
On Fri, Jul 27, 2018 at 03:34:46PM +0530, Raju P L S S S N wrote:
From: Lina Iyer
Controllers may be in 'solver' state, where they could be in autonomous
mode executing low power modes for their hardware
On Tue, Sep 11 2018 at 17:02 -0600, Matthias Kaehlcke wrote:
Hi Raju/Lina,
On Fri, Jul 27, 2018 at 03:34:46PM +0530, Raju P L S S S N wrote:
From: Lina Iyer
Controllers may be in 'solver' state, where they could be in autonomous
mode executing low power modes for their hardware
On Tue, Sep 11 2018 at 16:39 -0600, Matthias Kaehlcke wrote:
Hi Raju/Lina,
On Fri, Jul 27, 2018 at 03:34:44PM +0530, Raju P L S S S N wrote:
From: Lina Iyer
Allow the controller status be queried. The controller is busy if it is
actively processing request.
Signed-off-by: Lina Iyer
Signed
On Tue, Sep 11 2018 at 16:39 -0600, Matthias Kaehlcke wrote:
Hi Raju/Lina,
On Fri, Jul 27, 2018 at 03:34:44PM +0530, Raju P L S S S N wrote:
From: Lina Iyer
Allow the controller status be queried. The controller is busy if it is
actively processing request.
Signed-off-by: Lina Iyer
Signed
On Mon, Sep 10 2018 at 10:28 -0600, Rob Herring wrote:
On Tue, Sep 04, 2018 at 03:18:07PM -0600, Lina Iyer wrote:
Update the documentation to use interrupts-extended format for
specifying the TLMM summary IRQ line that is requested from GIC and the
PDC interrupts corresponding to the wakeup
On Mon, Sep 10 2018 at 10:28 -0600, Rob Herring wrote:
On Tue, Sep 04, 2018 at 03:18:07PM -0600, Lina Iyer wrote:
Update the documentation to use interrupts-extended format for
specifying the TLMM summary IRQ line that is requested from GIC and the
PDC interrupts corresponding to the wakeup
On Tue, Sep 04 2018 at 16:00 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-09-04 14:09:34)
On Mon, Aug 27 2018 at 14:01 -0600, Stephen Boyd wrote:
>
>Can't we just configure a different chained IRQ handler with
>irq_set_chained_handler_and_data() for each of the GPIO IRQs that are
On Tue, Sep 04 2018 at 16:00 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-09-04 14:09:34)
On Mon, Aug 27 2018 at 14:01 -0600, Stephen Boyd wrote:
>
>Can't we just configure a different chained IRQ handler with
>irq_set_chained_handler_and_data() for each of the GPIO IRQs that are
The wait_for_compl register ensures the request sequence is maintained
when sending requests from the TCS. Clear the register after sending
active request and during invalidate of the sleep and wake TCS.
Reported-by: Raju P.L.S.S.S.N
Signed-off-by: Lina Iyer
---
This is based on https
The wait_for_compl register ensures the request sequence is maintained
when sending requests from the TCS. Clear the register after sending
active request and during invalidate of the sleep and wake TCS.
Reported-by: Raju P.L.S.S.S.N
Signed-off-by: Lina Iyer
---
This is based on https
Stephen, Doug,
Would you have some time to take a look at this series?
Thanks,
Lina
On Fri, Jul 27 2018 at 04:04 -0600, Raju P L S S S N wrote:
From: "Raju P.L.S.S.S.N"
Changes in v1:
- Remove unnecessary EXPORT_SYMBOL in rpmh-rsc
This set of patches add additional functionali
Stephen, Doug,
Would you have some time to take a look at this series?
Thanks,
Lina
On Fri, Jul 27 2018 at 04:04 -0600, Raju P L S S S N wrote:
From: "Raju P.L.S.S.S.N"
Changes in v1:
- Remove unnecessary EXPORT_SYMBOL in rpmh-rsc
This set of patches add additional functionali
On Tue, Sep 04 2018 at 15:18 -0600, Lina Iyer wrote:
QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on
domain can wakeup the SoC, when interrupts and GPIOs are routed to its
interrupt controller. Only select GPIOs that are deemed wakeup capable
are routed to specific PDC
On Tue, Sep 04 2018 at 15:18 -0600, Lina Iyer wrote:
QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on
domain can wakeup the SoC, when interrupts and GPIOs are routed to its
interrupt controller. Only select GPIOs that are deemed wakeup capable
are routed to specific PDC
being interrupted twice (for TLMM and once for PDC IRQ) when a
GPIO trips, use TLMM for active and switch to PDC for suspend. When
entering suspend, disable the TLMM wakeup interrupt and instead enable
the PDC IRQ and revert upon resume.
Signed-off-by: Lina Iyer
---
Changes in v3:
- Enable
.
Request the corresponding PDC IRQ, when the GPIO is requested as an IRQ,
but keep it disabled. During suspend, we can enable the PDC IRQ instead
of the GPIO IRQ, which may or not be detected.
Signed-off-by: Lina Iyer
---
Changes in v3:
- free action->name
Changes in v2:
- Rem
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
Reviewed-by: Rob Herring
---
Changes in v2
y helpful.
Thanks,
Lina
[1]. drivers/irqchip/qcom-pdc.c
[2]. Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
[3]. drivers/pinctrl/qcom/pinctrl-msm.c
[4]. https://lore.kernel.org/patchwork/patch/977589/
[5]. https://lore.kernel.org/patchwork/patch/975425/
Lina Iyer (5):
driv
being interrupted twice (for TLMM and once for PDC IRQ) when a
GPIO trips, use TLMM for active and switch to PDC for suspend. When
entering suspend, disable the TLMM wakeup interrupt and instead enable
the PDC IRQ and revert upon resume.
Signed-off-by: Lina Iyer
---
Changes in v3:
- Enable
.
Request the corresponding PDC IRQ, when the GPIO is requested as an IRQ,
but keep it disabled. During suspend, we can enable the PDC IRQ instead
of the GPIO IRQ, which may or not be detected.
Signed-off-by: Lina Iyer
---
Changes in v3:
- free action->name
Changes in v2:
- Rem
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
Reviewed-by: Rob Herring
---
Changes in v2
y helpful.
Thanks,
Lina
[1]. drivers/irqchip/qcom-pdc.c
[2]. Documentation/devicetree/bindings/interrupt-controller/qcom,pdc.txt
[3]. drivers/pinctrl/qcom/pinctrl-msm.c
[4]. https://lore.kernel.org/patchwork/patch/977589/
[5]. https://lore.kernel.org/patchwork/patch/975425/
Lina Iyer (5):
driv
...@vger.kernel.org
Signed-off-by: Lina Iyer
---
Changes in v2:
- Fix PDC IRQ number in example
- Describe IRQ trigger type in example
---
.../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 104 +-
1 file changed, 101 insertions(+), 3 deletions(-)
diff --git a/Documentation
.
Signed-off-by: Lina Iyer
---
Changes in v3:
- Move the common suspend ops definition to pinctrl-msm.c
---
drivers/pinctrl/qcom/pinctrl-msm.c| 5 +
drivers/pinctrl/qcom/pinctrl-msm.h| 2 ++
drivers/pinctrl/qcom/pinctrl-sdm845.c | 1 +
3 files changed, 8 insertions(+)
diff --git
...@vger.kernel.org
Signed-off-by: Lina Iyer
---
Changes in v2:
- Fix PDC IRQ number in example
- Describe IRQ trigger type in example
---
.../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 104 +-
1 file changed, 101 insertions(+), 3 deletions(-)
diff --git a/Documentation
.
Signed-off-by: Lina Iyer
---
Changes in v3:
- Move the common suspend ops definition to pinctrl-msm.c
---
drivers/pinctrl/qcom/pinctrl-msm.c| 5 +
drivers/pinctrl/qcom/pinctrl-msm.h| 2 ++
drivers/pinctrl/qcom/pinctrl-sdm845.c | 1 +
3 files changed, 8 insertions(+)
diff --git
On Mon, Aug 27 2018 at 14:01 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-08-24 10:14:32)
On Fri, Aug 24 2018 at 02:22 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2018-08-17 12:10:23)
>> During suspend the system may power down some of the system rails. As a
>> resu
On Mon, Aug 27 2018 at 14:01 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-08-24 10:14:32)
On Fri, Aug 24 2018 at 02:22 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2018-08-17 12:10:23)
>> During suspend the system may power down some of the system rails. As a
>> resu
On Mon, Aug 27 2018 at 16:35 -0600, Matthias Kaehlcke wrote:
Hi Lina,
On Fri, Aug 24, 2018 at 02:01:53PM -0600, Lina Iyer wrote:
QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on
domain can wakeup the SoC, when interrupts and GPIOs are routed to the
its interrupt
On Mon, Aug 27 2018 at 16:35 -0600, Matthias Kaehlcke wrote:
Hi Lina,
On Fri, Aug 24, 2018 at 02:01:53PM -0600, Lina Iyer wrote:
QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on
domain can wakeup the SoC, when interrupts and GPIOs are routed to the
its interrupt
On Mon, Aug 27 2018 at 16:57 -0600, Matthias Kaehlcke wrote:
Hi Lina,
On Fri, Aug 24, 2018 at 02:01:55PM -0600, Lina Iyer wrote:
During suspend the system may power down some of the system rails. As a
result, the TLMM hw block may not be operational anymore and wakeup
capable GPIOs
On Mon, Aug 27 2018 at 16:57 -0600, Matthias Kaehlcke wrote:
Hi Lina,
On Fri, Aug 24, 2018 at 02:01:55PM -0600, Lina Iyer wrote:
During suspend the system may power down some of the system rails. As a
result, the TLMM hw block may not be operational anymore and wakeup
capable GPIOs
On Mon, Aug 27 2018 at 18:26 -0600, Bjorn Andersson wrote:
On Mon 27 Aug 09:56 PDT 2018, Lina Iyer wrote:
On Sun, Aug 26 2018 at 08:33 -0600, Linus Walleij wrote:
> On Fri, Aug 17, 2018 at 6:39 PM Lina Iyer wrote:
>
> > QCOM SoC's that have Power Domain Controller (PDC) chip i
On Mon, Aug 27 2018 at 18:26 -0600, Bjorn Andersson wrote:
On Mon 27 Aug 09:56 PDT 2018, Lina Iyer wrote:
On Sun, Aug 26 2018 at 08:33 -0600, Linus Walleij wrote:
> On Fri, Aug 17, 2018 at 6:39 PM Lina Iyer wrote:
>
> > QCOM SoC's that have Power Domain Controller (PDC) chip i
On Mon, Aug 27 2018 at 18:31 -0600, Bjorn Andersson wrote:
On Fri 24 Aug 13:01 PDT 2018, Lina Iyer wrote:
Enable TLMM IRQs to be sensed by PDC when we enter suspend. It is
possible that the TLMM may be powered off and not detect GPIOs that are
configured as wake up interrupts. By hooking
On Mon, Aug 27 2018 at 18:31 -0600, Bjorn Andersson wrote:
On Fri 24 Aug 13:01 PDT 2018, Lina Iyer wrote:
Enable TLMM IRQs to be sensed by PDC when we enter suspend. It is
possible that the TLMM may be powered off and not detect GPIOs that are
configured as wake up interrupts. By hooking
On Sun, Aug 26 2018 at 08:33 -0600, Linus Walleij wrote:
On Fri, Aug 17, 2018 at 6:39 PM Lina Iyer wrote:
QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on
domain can wakeup the SoC, when interrupts and GPIOs are routed to the
its interrupt controller. Only select GPIOs
On Sun, Aug 26 2018 at 08:33 -0600, Linus Walleij wrote:
On Fri, Aug 17, 2018 at 6:39 PM Lina Iyer wrote:
QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on
domain can wakeup the SoC, when interrupts and GPIOs are routed to the
its interrupt controller. Only select GPIOs
On Mon, Aug 20 2018 at 00:05 -0600, Bjorn Andersson wrote:
On Fri 17 Aug 09:38 PDT 2018, Lina Iyer wrote:
Thanks Lina, I think this looks like a very reasonable approach!
QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on
domain can wakeup the SoC, when interrupts
On Mon, Aug 20 2018 at 00:05 -0600, Bjorn Andersson wrote:
On Fri 17 Aug 09:38 PDT 2018, Lina Iyer wrote:
Thanks Lina, I think this looks like a very reasonable approach!
QCOM SoC's that have Power Domain Controller (PDC) chip in the always-on
domain can wakeup the SoC, when interrupts
to be sent
only during entry of deeper system low power modes or suspend.
[1]https://patchwork.kernel.org/patch/10477533/
Signed-off-by: Raju P.L.S.S.S.N
Reviewed-by: Lina Iyer
---
drivers/soc/qcom/rpmh.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/soc/qcom
to be sent
only during entry of deeper system low power modes or suspend.
[1]https://patchwork.kernel.org/patch/10477533/
Signed-off-by: Raju P.L.S.S.S.N
Reviewed-by: Lina Iyer
---
drivers/soc/qcom/rpmh.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/drivers/soc/qcom
again.
Request the corresponding PDC IRQ, when the GPIO is requested as an IRQ,
but keep it disabled. During suspend, we can enable the PDC IRQ instead
of the GPIO IRQ, which may or not be detected.
Signed-off-by: Lina Iyer
---
Changes in v2:
- Remove IRQF_NO_SUSPEND and IRQF_ONE_SHOT from
again.
Request the corresponding PDC IRQ, when the GPIO is requested as an IRQ,
but keep it disabled. During suspend, we can enable the PDC IRQ instead
of the GPIO IRQ, which may or not be detected.
Signed-off-by: Lina Iyer
---
Changes in v2:
- Remove IRQF_NO_SUSPEND and IRQF_ONE_SHOT from
being interrupted twice (for TLMM and once for PDC IRQ) when a
GPIO trips, use TLMM for active and switch to PDC for suspend. When
entering suspend, disable the TLMM wakeup interrupt and instead enable
the PDC IRQ and revert upon resume.
Signed-off-by: Lina Iyer
---
Changes in v2:
- Fix PDC
being interrupted twice (for TLMM and once for PDC IRQ) when a
GPIO trips, use TLMM for active and switch to PDC for suspend. When
entering suspend, disable the TLMM wakeup interrupt and instead enable
the PDC IRQ and revert upon resume.
Signed-off-by: Lina Iyer
---
Changes in v2:
- Fix PDC
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
---
Changes in v2:
- Define IRQ trigger type in DT
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
---
Changes in v2:
- Define IRQ trigger type in DT
.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2ab7a8885757..cc333b8afb99 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b
...@vger.kernel.org
Signed-off-by: Lina Iyer
---
Changes in v2:
- Fix PDC IRQ number in example
- Describe IRQ trigger type in example
---
.../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 104 +-
1 file changed, 101 insertions(+), 3 deletions(-)
diff --git a/Documentation
I am unsure of how to set the
polarity of the PDC pin without locking, since we are not in hierarchy with the
PDC interrupt controller. Again, your inputs on these would be greatly helpful.
Thanks,
Lina
[1]. drivers/irqchip/qcom-pdc.c
[2]. Documentation/devicetree/bindings/interrupt-controll
.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2ab7a8885757..cc333b8afb99 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++ b
...@vger.kernel.org
Signed-off-by: Lina Iyer
---
Changes in v2:
- Fix PDC IRQ number in example
- Describe IRQ trigger type in example
---
.../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 104 +-
1 file changed, 101 insertions(+), 3 deletions(-)
diff --git a/Documentation
I am unsure of how to set the
polarity of the PDC pin without locking, since we are not in hierarchy with the
PDC interrupt controller. Again, your inputs on these would be greatly helpful.
Thanks,
Lina
[1]. drivers/irqchip/qcom-pdc.c
[2]. Documentation/devicetree/bindings/interrupt-controll
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
Changes in v3:
- Fix PDC map, use GIC SPI port number for hwirq
Changes in v2:
- Order by address
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
Changes in v3:
- Fix PDC map, use GIC SPI port number for hwirq
Changes in v2:
- Order by address
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff
The PDC map should use the GIC SPI port and not the vector. GIC
internally adds 32 to SPI hwirq numbers.
Fixes: 1ae8862e27e ("dt-bindings/interrupt-controller: pdc: Describe PDC device
binding")
Signed-off-by: Lina Iyer
---
.../devicetree/bindings/interrupt-controller/qcom,pdc.t
The PDC map should use the GIC SPI port and not the vector. GIC
internally adds 32 to SPI hwirq numbers.
Fixes: 1ae8862e27e ("dt-bindings/interrupt-controller: pdc: Describe PDC device
binding")
Signed-off-by: Lina Iyer
---
.../devicetree/bindings/interrupt-controller/qcom,pdc.t
On Fri, Aug 24 2018 at 02:22 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-08-17 12:10:23)
During suspend the system may power down some of the system rails. As a
result, the TLMM hw block may not be operational anymore and wakeup
capable GPIOs will not be detected. The PDC however
On Fri, Aug 24 2018 at 02:22 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-08-17 12:10:23)
During suspend the system may power down some of the system rails. As a
result, the TLMM hw block may not be operational anymore and wakeup
capable GPIOs will not be detected. The PDC however
ev)
+{
+ struct icc_provider *provider = platform_get_drvdata(pdev);
+ struct icc_node *n;
+
+ list_for_each_entry(n, >nodes, node_list) {
+ icc_node_del(n);
+ icc_node_destroy(n->id);
+ }
+
+ return icc_provider_del(provider);
+}
+
+s
ev)
+{
+ struct icc_provider *provider = platform_get_drvdata(pdev);
+ struct icc_node *n;
+
+ list_for_each_entry(n, >nodes, node_list) {
+ icc_node_del(n);
+ icc_node_destroy(n->id);
+ }
+
+ return icc_provider_del(provider);
+}
+
+s
On Thu, Aug 23 2018 at 19:57 -0600, David Dai wrote:
Add RSC(Resource State Coordinator) provider
dictating network-on-chip interconnect bus performance
found on SDM845-based platforms.
Change-Id: I58f0bfc3ed484d7b45064dceb94dcfda507e9333
Remove this pls.
-- Lina
Signed-off-by: David Dai
On Thu, Aug 23 2018 at 19:57 -0600, David Dai wrote:
Add RSC(Resource State Coordinator) provider
dictating network-on-chip interconnect bus performance
found on SDM845-based platforms.
Change-Id: I58f0bfc3ed484d7b45064dceb94dcfda507e9333
Remove this pls.
-- Lina
Signed-off-by: David Dai
On Mon, Aug 20 2018 at 09:34 -0600, Marc Zyngier wrote:
On 20/08/18 16:26, Lina Iyer wrote:
On Sat, Aug 18 2018 at 07:13 -0600, Marc Zyngier wrote:
Hi Lina,
On Fri, 17 Aug 2018 20:10:23 +0100,
Lina Iyer wrote:
[...]
@@ -920,6 +928,8 @@ static int msm_gpio_pdc_pin_request(struct irq_data
On Mon, Aug 20 2018 at 09:34 -0600, Marc Zyngier wrote:
On 20/08/18 16:26, Lina Iyer wrote:
On Sat, Aug 18 2018 at 07:13 -0600, Marc Zyngier wrote:
Hi Lina,
On Fri, 17 Aug 2018 20:10:23 +0100,
Lina Iyer wrote:
[...]
@@ -920,6 +928,8 @@ static int msm_gpio_pdc_pin_request(struct irq_data
On Sat, Aug 18 2018 at 07:13 -0600, Marc Zyngier wrote:
Hi Lina,
On Fri, 17 Aug 2018 20:10:23 +0100,
Lina Iyer wrote:
During suspend the system may power down some of the system rails. As a
result, the TLMM hw block may not be operational anymore and wakeup
capable GPIOs will not be detected
On Sat, Aug 18 2018 at 07:13 -0600, Marc Zyngier wrote:
Hi Lina,
On Fri, 17 Aug 2018 20:10:23 +0100,
Lina Iyer wrote:
During suspend the system may power down some of the system rails. As a
result, the TLMM hw block may not be operational anymore and wakeup
capable GPIOs will not be detected
Please ignore this series. The series is incorrectly marked as v2. I am
resending it as v1.
On Fri, Aug 17 2018 at 10:39 -0600, Lina Iyer wrote:
Hi,
Changes in v1:
- Avoid GPIO-PDC map in .c file
- Trigger GPIO by writing to the hardware
- Hooked up to suspend/resume
Please ignore this series. The series is incorrectly marked as v2. I am
resending it as v1.
On Fri, Aug 17 2018 at 10:39 -0600, Lina Iyer wrote:
Hi,
Changes in v1:
- Avoid GPIO-PDC map in .c file
- Trigger GPIO by writing to the hardware
- Hooked up to suspend/resume
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