...@vger.kernel.org
Signed-off-by: Lina Iyer
---
.../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 58 ++-
1 file changed, 55 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845
...@vger.kernel.org
Signed-off-by: Lina Iyer
---
.../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 58 ++-
1 file changed, 55 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845
or with interrupt names. Also, I am still sorting out some issues
with the IRQ handling part of these patches. And I am unsure of how to set the
polarity of the PDC pin without locking, since we are not in hierarchy with the
PDC interrupt controller. Again, your inputs on these would be greatly help
or with interrupt names. Also, I am still sorting out some issues
with the IRQ handling part of these patches. And I am unsure of how to set the
polarity of the PDC pin without locking, since we are not in hierarchy with the
PDC interrupt controller. Again, your inputs on these would be greatly help
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
---
Changes in v1:
- Use interrupt-extended for all
From: Marc Zyngier
Although GICv3 doesn't directly offers support for wake-up interrupts
and relies on external HW for this, it shouldn't prevent the driver
for such HW from doing it work.
Let's set the required flags on the irq_chip structures.
Reported-by: Lina Iyer
Signed-off-by: Marc
being interrupted twice (for TLMM and once for PDC IRQ) when a
GPIO trips, use TLMM for active and switch to PDC for suspend. When
entering suspend, disable the TLMM wakeup interrupt and instead enable
the PDC IRQ and revert upon resume.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl
From: Marc Zyngier
Although GICv3 doesn't directly offers support for wake-up interrupts
and relies on external HW for this, it shouldn't prevent the driver
for such HW from doing it work.
Let's set the required flags on the irq_chip structures.
Reported-by: Lina Iyer
Signed-off-by: Marc
being interrupted twice (for TLMM and once for PDC IRQ) when a
GPIO trips, use TLMM for active and switch to PDC for suspend. When
entering suspend, disable the TLMM wakeup interrupt and instead enable
the PDC IRQ and revert upon resume.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
---
Changes in v1:
- Use interrupt-extended for all
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2ab7a8885757..cc333b8afb99 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2ab7a8885757..cc333b8afb99 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++
being interrupted twice (for TLMM and once for PDC IRQ) when a
GPIO trips, use TLMM for active and switch to PDC for suspend. When
entering suspend, disable the TLMM wakeup interrupt and instead enable
the PDC IRQ and revert upon resume.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl
being interrupted twice (for TLMM and once for PDC IRQ) when a
GPIO trips, use TLMM for active and switch to PDC for suspend. When
entering suspend, disable the TLMM wakeup interrupt and instead enable
the PDC IRQ and revert upon resume.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl
again.
Request the corresponding PDC IRQ, when the GPIO is requested as an IRQ,
but keep it disabled. During suspend, we can enable the PDC IRQ instead
of the GPIO IRQ, which may or not be detected.
Signed-off-by: Lina Iyer
---
Changes in v1:
- Trigger GPIO in h/w from PDC IRQ handler
again.
Request the corresponding PDC IRQ, when the GPIO is requested as an IRQ,
but keep it disabled. During suspend, we can enable the PDC IRQ instead
of the GPIO IRQ, which may or not be detected.
Signed-off-by: Lina Iyer
---
Changes in v1:
- Trigger GPIO in h/w from PDC IRQ handler
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
---
Changes in v1:
- Use interrupt-extended for all
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
---
Changes in v1:
- Use interrupt-extended for all
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2ab7a8885757..cc333b8afb99 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++
ssues
with the IRQ handling part of these patches. And I am unsure of how to set the
polarity of the PDC pin without locking, since we are not in hierarchy with the
PDC interrupt controller. Again, your inputs on these would be greatly helpful.
Thanks,
Lina
[1]. drivers/irqchip/qcom-pdc.c
...@vger.kernel.org
Signed-off-by: Lina Iyer
---
.../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 58 ++-
1 file changed, 55 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2ab7a8885757..cc333b8afb99 100644
--- a/drivers/pinctrl/qcom/pinctrl-sdm845.c
+++
ssues
with the IRQ handling part of these patches. And I am unsure of how to set the
polarity of the PDC pin without locking, since we are not in hierarchy with the
PDC interrupt controller. Again, your inputs on these would be greatly helpful.
Thanks,
Lina
[1]. drivers/irqchip/qcom-pdc.c
...@vger.kernel.org
Signed-off-by: Lina Iyer
---
.../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 58 ++-
1 file changed, 55 insertions(+), 3 deletions(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
b/Documentation/devicetree/bindings/pinctrl/qcom,sdm845
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
Changes in v2:
- Order by address
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
Changes in v2:
- Order by address
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom
-by: Lina Iyer
Signed-off-by: Marc Zyngier
---
Lina, please let me know how this goes. If that fixes your issues,
I'll queue it as a fix for the current cycle.
Thanks for the quick turn around, Marc.
Tested-by: Lina Iyer
drivers/irqchip/irq-gic-v3.c | 8 ++--
1 file changed, 6 insertions
-by: Lina Iyer
Signed-off-by: Marc Zyngier
---
Lina, please let me know how this goes. If that fixes your issues,
I'll queue it as a fix for the current cycle.
Thanks for the quick turn around, Marc.
Tested-by: Lina Iyer
drivers/irqchip/irq-gic-v3.c | 8 ++--
1 file changed, 6 insertions
On Wed, Aug 15 2018 at 09:28 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-08-14 10:30:58)
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64
On Wed, Aug 15 2018 at 09:28 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2018-08-14 10:30:58)
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64
Adding Ram, so he can respond.
-- Lina
On Thu, Jul 26 2018 at 02:55 -0600, Zhang Rui wrote:
On 一, 2018-05-07 at 11:55 -0600, Lina Iyer wrote:
From: Ram Chandrasekar
Let userspace be another voter for cooling device state instead of
the
overriding authority. It is possible that the thermal
Adding Ram, so he can respond.
-- Lina
On Thu, Jul 26 2018 at 02:55 -0600, Zhang Rui wrote:
On 一, 2018-05-07 at 11:55 -0600, Lina Iyer wrote:
From: Ram Chandrasekar
Let userspace be another voter for cooling device state instead of
the
overriding authority. It is possible that the thermal
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 24e254efb9d1..399bfbd52c5b
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 24e254efb9d1..399bfbd52c5b
On Wed, Aug 01 2018 at 14:04 -0600, Lina Iyer wrote:
On Wed, Aug 01 2018 at 02:42 -0600, Marc Zyngier wrote:
On Wed, 01 Aug 2018 03:00:19 +0100,
Lina Iyer wrote:
Add GPIO to PDC pin map for the SDM845 SoC.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 76
On Wed, Aug 01 2018 at 14:04 -0600, Lina Iyer wrote:
On Wed, Aug 01 2018 at 02:42 -0600, Marc Zyngier wrote:
On Wed, 01 Aug 2018 03:00:19 +0100,
Lina Iyer wrote:
Add GPIO to PDC pin map for the SDM845 SoC.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 76
On Thu, Aug 09 2018 at 02:16 -0600, Rafael J. Wysocki wrote:
On Wed, Aug 8, 2018 at 8:02 PM, Lina Iyer wrote:
On Wed, Aug 08 2018 at 04:56 -0600, Lorenzo Pieralisi wrote:
On Mon, Aug 06, 2018 at 11:37:55AM +0200, Rafael J. Wysocki wrote:
On Fri, Aug 3, 2018 at 1:42 PM, Ulf Hansson
wrote
On Thu, Aug 09 2018 at 02:16 -0600, Rafael J. Wysocki wrote:
On Wed, Aug 8, 2018 at 8:02 PM, Lina Iyer wrote:
On Wed, Aug 08 2018 at 04:56 -0600, Lorenzo Pieralisi wrote:
On Mon, Aug 06, 2018 at 11:37:55AM +0200, Rafael J. Wysocki wrote:
On Fri, Aug 3, 2018 at 1:42 PM, Ulf Hansson
wrote
On Thu, Aug 09 2018 at 04:25 -0600, Lorenzo Pieralisi wrote:
On Wed, Aug 08, 2018 at 12:02:48PM -0600, Lina Iyer wrote:
On Wed, Aug 08 2018 at 04:56 -0600, Lorenzo Pieralisi wrote:
>On Mon, Aug 06, 2018 at 11:37:55AM +0200, Rafael J. Wysocki wrote:
>>On Fri, Aug 3, 2018 at 1:42 PM, Ul
On Thu, Aug 09 2018 at 04:25 -0600, Lorenzo Pieralisi wrote:
On Wed, Aug 08, 2018 at 12:02:48PM -0600, Lina Iyer wrote:
On Wed, Aug 08 2018 at 04:56 -0600, Lorenzo Pieralisi wrote:
>On Mon, Aug 06, 2018 at 11:37:55AM +0200, Rafael J. Wysocki wrote:
>>On Fri, Aug 3, 2018 at 1:42 PM, Ul
g
the interrupts that are configured as a wake-up source (although it
needs to track an interrupt that is logically connected to the TLMM,
which sucks).
The PDC also needs to be configured for wakeups from deep CPU idle
states where the GIC and TLMM are powered down. Lina, can you confirm
this?
Yes
g
the interrupts that are configured as a wake-up source (although it
needs to track an interrupt that is logically connected to the TLMM,
which sucks).
The PDC also needs to be configured for wakeups from deep CPU idle
states where the GIC and TLMM are powered down. Lina, can you confirm
this?
Yes
On Tue, Aug 07 2018 at 13:57 -0600, Evan Green wrote:
On Tue, Jul 31, 2018 at 3:44 PM Lina Iyer wrote:
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines
On Tue, Aug 07 2018 at 13:57 -0600, Evan Green wrote:
On Tue, Jul 31, 2018 at 3:44 PM Lina Iyer wrote:
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines
f benchmarks between OSI and PC.
AFAIK, there are no platforms supporting both.
But, the OSI feature is critical for QCOM mobile platforms. The
last man activities during cpuidle save quite a lot of power. Powering
off the clocks, busses, regulators and even the oscillator is very
important to have a r
f benchmarks between OSI and PC.
AFAIK, there are no platforms supporting both.
But, the OSI feature is critical for QCOM mobile platforms. The
last man activities during cpuidle save quite a lot of power. Powering
off the clocks, busses, regulators and even the oscillator is very
important to have a r
On Thu, Aug 02 2018 at 01:27 -0600, Marc Zyngier wrote:
On Thu, 02 Aug 2018 07:51:04 +0100,
Lina Iyer wrote:
On Thu, Aug 02 2018 at 00:08 -0600, Marc Zyngier wrote:
> Hi Lina,
>
> On Wed, 01 Aug 2018 20:45:38 +0100,
> Lina Iyer wrote:
>>
>> Thanks for the feedback, Ma
On Thu, Aug 02 2018 at 01:27 -0600, Marc Zyngier wrote:
On Thu, 02 Aug 2018 07:51:04 +0100,
Lina Iyer wrote:
On Thu, Aug 02 2018 at 00:08 -0600, Marc Zyngier wrote:
> Hi Lina,
>
> On Wed, 01 Aug 2018 20:45:38 +0100,
> Lina Iyer wrote:
>>
>> Thanks for the feedback, Ma
On Thu, Aug 02 2018 at 00:08 -0600, Marc Zyngier wrote:
Hi Lina,
On Wed, 01 Aug 2018 20:45:38 +0100,
Lina Iyer wrote:
Thanks for the feedback, Marc.
On Wed, Aug 01 2018 at 00:31 -0600, Marc Zyngier wrote:
> On Wed, 01 Aug 2018 03:00:18 +0100,
> Lina Iyer wrote:
>>
>> +
On Thu, Aug 02 2018 at 00:08 -0600, Marc Zyngier wrote:
Hi Lina,
On Wed, 01 Aug 2018 20:45:38 +0100,
Lina Iyer wrote:
Thanks for the feedback, Marc.
On Wed, Aug 01 2018 at 00:31 -0600, Marc Zyngier wrote:
> On Wed, 01 Aug 2018 03:00:18 +0100,
> Lina Iyer wrote:
>>
>> +
On Wed, Aug 01 2018 at 16:38 -0600, Bjorn Andersson wrote:
On Wed 01 Aug 12:45 PDT 2018, Lina Iyer wrote:
Thanks for the feedback, Marc.
On Wed, Aug 01 2018 at 00:31 -0600, Marc Zyngier wrote:
> On Wed, 01 Aug 2018 03:00:18 +0100,
> Lina Iyer wrote:
[..]
> Why isn't that
On Wed, Aug 01 2018 at 16:38 -0600, Bjorn Andersson wrote:
On Wed 01 Aug 12:45 PDT 2018, Lina Iyer wrote:
Thanks for the feedback, Marc.
On Wed, Aug 01 2018 at 00:31 -0600, Marc Zyngier wrote:
> On Wed, 01 Aug 2018 03:00:18 +0100,
> Lina Iyer wrote:
[..]
> Why isn't that
On Wed, Aug 01 2018 at 02:42 -0600, Marc Zyngier wrote:
On Wed, 01 Aug 2018 03:00:19 +0100,
Lina Iyer wrote:
Add GPIO to PDC pin map for the SDM845 SoC.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 76 +++
1 file changed, 76 insertions
On Wed, Aug 01 2018 at 02:42 -0600, Marc Zyngier wrote:
On Wed, 01 Aug 2018 03:00:19 +0100,
Lina Iyer wrote:
Add GPIO to PDC pin map for the SDM845 SoC.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 76 +++
1 file changed, 76 insertions
Thanks for the feedback, Marc.
On Wed, Aug 01 2018 at 00:31 -0600, Marc Zyngier wrote:
On Wed, 01 Aug 2018 03:00:18 +0100,
Lina Iyer wrote:
+static irqreturn_t wake_irq_gpio_handler(int irq, void *data)
+{
+ struct irq_data *irqd = data;
+ struct irq_desc *desc = irq_data_to_desc
Thanks for the feedback, Marc.
On Wed, Aug 01 2018 at 00:31 -0600, Marc Zyngier wrote:
On Wed, 01 Aug 2018 03:00:18 +0100,
Lina Iyer wrote:
+static irqreturn_t wake_irq_gpio_handler(int irq, void *data)
+{
+ struct irq_data *irqd = data;
+ struct irq_desc *desc = irq_data_to_desc
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 69
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 69
h the IRQ handling part of these patches. And I am unsure of how to set the
polarity of the PDC pin without locking, since we are not in hierarchy with the
PDC interrupt controller. Again, your inputs on these would be greatly helpful.
Thanks,
Lina
[1]. drivers/irqchip/qcom-pdc.c
[2]. Docume
h the IRQ handling part of these patches. And I am unsure of how to set the
polarity of the PDC pin without locking, since we are not in hierarchy with the
PDC interrupt controller. Again, your inputs on these would be greatly helpful.
Thanks,
Lina
[1]. drivers/irqchip/qcom-pdc.c
[2]. Docume
Add GPIO to PDC pin map for the SDM845 SoC.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 76 +++
1 file changed, 76 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2ab7a8885757
at the GIC and the interrupt handler for the GPIO is invoked.
Setup the PDC IRQ when the GPIO's IRQ is requested and enable the PDC
IRQ when the GPIO's IRQ is enabled.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-msm.c | 163 +
drivers/pinctrl/qcom
Add GPIO to PDC pin map for the SDM845 SoC.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 76 +++
1 file changed, 76 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2ab7a8885757
at the GIC and the interrupt handler for the GPIO is invoked.
Setup the PDC IRQ when the GPIO's IRQ is requested and enable the PDC
IRQ when the GPIO's IRQ is enabled.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-msm.c | 163 +
drivers/pinctrl/qcom
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 2acc17ce1a9c..8ccce42885c1
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 2acc17ce1a9c..8ccce42885c1
Add GPIO to PDC pin map for the SDM845 SoC.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 76 +++
1 file changed, 76 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2ab7a8885757
at the GIC and the interrupt handler for the GPIO is invoked.
Setup the PDC IRQ when the GPIO's IRQ is requested and enable the PDC
IRQ when the GPIO's IRQ is enabled.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-msm.c | 163 +
drivers/pinctrl/qcom
Add GPIO to PDC pin map for the SDM845 SoC.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 76 +++
1 file changed, 76 insertions(+)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl/qcom/pinctrl-sdm845.c
index 2ab7a8885757
at the GIC and the interrupt handler for the GPIO is invoked.
Setup the PDC IRQ when the GPIO's IRQ is requested and enable the PDC
IRQ when the GPIO's IRQ is enabled.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-msm.c | 163 +
drivers/pinctrl/qcom
h the IRQ handling part of these patches. And I am unsure of how to set the
polarity of the PDC pin without locking, since we are not in hierarchy with the
PDC interrupt controller. Again, your inputs on these would be greatly helpful.
Thanks,
Lina
[1]. drivers/irqchip/qcom-pdc.c
[2]. Docume
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 2acc17ce1a9c..8ccce42885c1
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 69
h the IRQ handling part of these patches. And I am unsure of how to set the
polarity of the PDC pin without locking, since we are not in hierarchy with the
PDC interrupt controller. Again, your inputs on these would be greatly helpful.
Thanks,
Lina
[1]. drivers/irqchip/qcom-pdc.c
[2]. Docume
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index 2acc17ce1a9c..8ccce42885c1
GPIOs that are wakeup capable have interrupt lines that are routed to
the always-on interrupt controller (PDC) in parallel to the pinctrl. The
interrupts listed here are the wake up lines corresponding to GPIOs.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 69
ow invalidation
of sleep/wake TCS")
Reported-by: Dan Carpenter
Signed-off-by: Raju P.L.S.S.S.N
Reviewed-by: Lina Iyer
---
drivers/soc/qcom/rpmh-rsc.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c
index 098
ow invalidation
of sleep/wake TCS")
Reported-by: Dan Carpenter
Signed-off-by: Raju P.L.S.S.S.N
Reviewed-by: Lina Iyer
---
drivers/soc/qcom/rpmh-rsc.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c
index 098
+ Dan
On Fri, Jul 13 2018 at 07:46 -0600, Raju P L S S S N wrote:
From: "Raju P.L.S.S.S.N"
The patch fixes the bug reported by Dan Carpenter.
It removes the unnecessary err check for ‘tcs’ reported by
static checker warning:
drivers/soc/qcom/rpmh-rsc.c:111 tcs_invalidate()
warn: 'tcs' isn't
+ Dan
On Fri, Jul 13 2018 at 07:46 -0600, Raju P L S S S N wrote:
From: "Raju P.L.S.S.S.N"
The patch fixes the bug reported by Dan Carpenter.
It removes the unnecessary err check for ‘tcs’ reported by
static checker warning:
drivers/soc/qcom/rpmh-rsc.c:111 tcs_invalidate()
warn: 'tcs' isn't
On Thu, Jul 12 2018 at 10:31 -0600, Evan Green wrote:
On Tue, Jul 10, 2018 at 1:38 PM Lina Iyer wrote:
On Tue, Jul 10 2018 at 12:53 -0600, Evan Green wrote:
>On Mon, Jul 9, 2018 at 10:27 AM Bjorn Andersson
> wrote:
>Our understanding is the downstream kernel had an interrupt hierarch
On Thu, Jul 12 2018 at 10:31 -0600, Evan Green wrote:
On Tue, Jul 10, 2018 at 1:38 PM Lina Iyer wrote:
On Tue, Jul 10 2018 at 12:53 -0600, Evan Green wrote:
>On Mon, Jul 9, 2018 at 10:27 AM Bjorn Andersson
> wrote:
>Our understanding is the downstream kernel had an interrupt hierarch
y a RFC patch in a week or two.
-- Lina
So anyway, with regard to this patch, I'm happy to create a second
spin that simply removes this function, but for me at least it brought
up some larger questions we've been wrestling with.
-Evan
--
To unsubscribe from this list: send the line "unsubsc
y a RFC patch in a week or two.
-- Lina
So anyway, with regard to this patch, I'm happy to create a second
spin that simply removes this function, but for me at least it brought
up some larger questions we've been wrestling with.
-Evan
--
To unsubscribe from this list: send the line "unsubsc
Thanks for the quick spin Doug.
On Mon, Jun 18 2018 at 15:51 -0600, Douglas Anderson wrote:
This adds the rpmh-rsc node to sdm845 based on the examples in the
bindings.
Signed-off-by: Douglas Anderson
Reviewed-by: Lina Iyer
---
Changes in v2:
- Fixed ordering of tcs-config as per Lina
Thanks for the quick spin Doug.
On Mon, Jun 18 2018 at 15:51 -0600, Douglas Anderson wrote:
This adds the rpmh-rsc node to sdm845 based on the examples in the
bindings.
Signed-off-by: Douglas Anderson
Reviewed-by: Lina Iyer
---
Changes in v2:
- Fixed ordering of tcs-config as per Lina
,
;
While the above configuration would work for now, it would fail, when we
enable system low power modes, which would use TCSes 2-7 for sleep and
wake set transitions from the firmware.
Thanks,
Lina
+ };
+
,
;
While the above configuration would work for now, it would fail, when we
enable system low power modes, which would use TCSes 2-7 for sleep and
wake set transitions from the firmware.
Thanks,
Lina
+ };
+
On Mon, Jun 18 2018 at 13:54 -0600, Doug Anderson wrote:
Hi,
On Mon, Jun 18, 2018 at 12:06 PM, Lina Iyer wrote:
On Mon, Jun 18 2018 at 12:33 -0600, Doug Anderson wrote:
Lina,
On Mon, Jun 18, 2018 at 9:39 AM, Lina Iyer wrote:
+/**
* struct rsc_drv: the Direct Resource Voter (DRV
On Mon, Jun 18 2018 at 13:54 -0600, Doug Anderson wrote:
Hi,
On Mon, Jun 18, 2018 at 12:06 PM, Lina Iyer wrote:
On Mon, Jun 18 2018 at 12:33 -0600, Doug Anderson wrote:
Lina,
On Mon, Jun 18, 2018 at 9:39 AM, Lina Iyer wrote:
+/**
* struct rsc_drv: the Direct Resource Voter (DRV
On Mon, Jun 18 2018 at 12:33 -0600, Doug Anderson wrote:
Lina,
On Mon, Jun 18, 2018 at 9:39 AM, Lina Iyer wrote:
+/**
* struct rsc_drv: the Direct Resource Voter (DRV) of the
* Resource State Coordinator controller (RSC)
*
@@ -52,6 +78,7 @@ struct tcs_group {
* @tcs:TCS groups
On Mon, Jun 18 2018 at 12:33 -0600, Doug Anderson wrote:
Lina,
On Mon, Jun 18, 2018 at 9:39 AM, Lina Iyer wrote:
+/**
* struct rsc_drv: the Direct Resource Voter (DRV) of the
* Resource State Coordinator controller (RSC)
*
@@ -52,6 +78,7 @@ struct tcs_group {
* @tcs:TCS groups
On Mon, Jun 18 2018 at 11:23 -0600, Douglas Anderson wrote:
Children of RPMh will need access to cmd_db. Rather than having each
child have code to check if cmd_db is ready let's add the check to
RPMh.
Suggested-by: Stephen Boyd
Signed-off-by: Douglas Anderson
Acked-by: Lina Iyer
On Mon, Jun 18 2018 at 11:23 -0600, Douglas Anderson wrote:
Children of RPMh will need access to cmd_db. Rather than having each
child have code to check if cmd_db is ready let's add the check to
RPMh.
Suggested-by: Stephen Boyd
Signed-off-by: Douglas Anderson
Acked-by: Lina Iyer
On Mon, Jun 18 2018 at 07:37 -0600, Raju P L S S S N wrote:
From: Lina Iyer
Sending RPMH requests and waiting for response from the controller
through a callback is common functionality across all platform drivers.
To simplify drivers, add a library functions to create RPMH client and
send
On Mon, Jun 18 2018 at 07:37 -0600, Raju P L S S S N wrote:
From: Lina Iyer
Sending RPMH requests and waiting for response from the controller
through a callback is common functionality across all platform drivers.
To simplify drivers, add a library functions to create RPMH client and
send
lidate fails, its mostly because, the TCS is busy or in use by an
external entity. Only the caller would be able to resolve the condition
and take corrective action.
-- Lina
lidate fails, its mostly because, the TCS is busy or in use by an
external entity. Only the caller would be able to resolve the condition
and take corrective action.
-- Lina
() function in [4]. However, could you please confirm
with Lina that this usage will continue to work in the future? I'm not
sure what guarantees are made at the rpmh API level.
We expect to cache all active values into wake if there was a sleep
value already defined. Expect to continue this behav
() function in [4]. However, could you please confirm
with Lina that this usage will continue to work in the future? I'm not
sure what guarantees are made at the rpmh API level.
We expect to cache all active values into wake if there was a sleep
value already defined. Expect to continue this behav
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