+ linaro-toolchain@lists.linaro.org
Could someone help with this information in Maxim's absence ?
Thanks,
Lina
On Tue, Oct 10 2023 at 10:07 -0600, Lina Iyer wrote:
Hi Maxim,
Do you have a list of machines and who provided us with those machines
that we use for WoA projects? I see the list
to `cmd_db_read_addr'
Fixes: 778279f4f5e4 ("soc: qcom: cmd-db: allow loading as a module")
Reported-by: kernel test robot
Signed-off-by: Randy Dunlap
Cc: Lina Iyer
Cc: Liam Girdwood
Cc: Mark Brown
Reviewed-by: Lina Iyer
---
drivers/regulator/Kconfig |1 +
1 file changed, 1
On Wed, Oct 28 2020 at 03:43 -0600, Anders Roxell wrote:
On Tue, 27 Oct 2020 at 22:15, Lina Iyer wrote:
Hi Anders,
On Tue, Oct 27 2020 at 05:14 -0600, Anders Roxell wrote:
>When building allmodconfig leading to the following link error with
>CONFIG_QCOM_RPMH=y and CONFIG_QCOM_COMMAN
Hi Anders,
On Tue, Oct 27 2020 at 05:14 -0600, Anders Roxell wrote:
When building allmodconfig leading to the following link error with
CONFIG_QCOM_RPMH=y and CONFIG_QCOM_COMMAND_DB=m:
aarch64-linux-gnu-ld: drivers/clk/qcom/clk-rpmh.o: in function `clk_rpmh_probe':
On Tue, Oct 13 2020 at 06:23 -0600, Ulf Hansson wrote:
A device may have specific HW constraints that must be obeyed to, before
its corresponding PM domain (genpd) can be powered off - and vice verse at
power on. These constraints can't be managed through the regular runtime PM
based deployment
GENPD_NOTIFY_PRE_OFF, NULL, -1,
+ _calls);
+ ret = notifier_to_errno(ret);
+ if (ret)
+ goto busy;
Nit: You could enclose this in a function call to keep these functions
clean.
Otherwise,
Tested-by: Lin
-Original Message-
Date: Wed, 19 Aug 2020 12:40:57 +0200
From: Ulf Hansson
To: "Rafael J . Wysocki" , Kevin Hilman
, linux...@vger.kernel.org
Cc: Sudeep Holla , Lorenzo Pieralisi
, Daniel Lezcano ,
Lina Iyer , Lukasz Luba , Vincent
Guittot , Stephen Boyd , Bjorn
Andersson
Hi Ulf,
On Tue, Sep 01 2020 at 06:41 -0600, Ulf Hansson wrote:
On Tue, 1 Sep 2020 at 14:35, Ulf Hansson wrote:
On Tue, 1 Sep 2020 at 12:42, wrote:
>
> On Tue, Sep 01, 2020 at 08:50:57AM +0200, Ulf Hansson wrote:
> > On Tue, 1 Sep 2020 at 08:46, Ulf Hansson wrote:
> > > On Mon, 31 Aug 2020
On Wed, Aug 19 2020 at 04:41 -0600, Ulf Hansson wrote:
A device may have specific HW constraints that must be obeyed to, before
its corresponding PM domain (genpd) can be powered off - and vice verse at
power on. These constraints can't be managed through the regular runtime PM
based deployment
On Tue, Jul 28 2020 at 13:51 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2020-07-28 09:52:12)
On Mon, Jul 27 2020 at 18:45 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2020-07-24 09:28:25)
>> On Fri, Jul 24 2020 at 03:03 -0600, Rajendra Nayak wrote:
>> >Hi Maulik/Lina,
>
On Mon, Jul 27 2020 at 18:45 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2020-07-24 09:28:25)
On Fri, Jul 24 2020 at 03:03 -0600, Rajendra Nayak wrote:
>Hi Maulik/Lina,
>
>On 7/23/2020 11:36 PM, Stanimir Varbanov wrote:
>>Hi Rajendra,
>>
>>After applying 2,
On Fri, Jul 24 2020 at 14:11 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2020-07-24 13:08:41)
On Fri, Jul 24 2020 at 14:01 -0600, Stephen Boyd wrote:
>Quoting Doug Anderson (2020-07-24 12:49:56)
>> Hi,
>>
>> On Fri, Jul 24, 2020 at 12:44 PM Stephen Boyd wrote:
>I
On Fri, Jul 24 2020 at 14:01 -0600, Stephen Boyd wrote:
Quoting Doug Anderson (2020-07-24 12:49:56)
Hi,
On Fri, Jul 24, 2020 at 12:44 PM Stephen Boyd wrote:
I think Lina was alluding to this earlier in this
thread.
I was thinking more of threaded irq handler than a kthread to post the
On Fri, Jul 24 2020 at 03:03 -0600, Rajendra Nayak wrote:
Hi Maulik/Lina,
On 7/23/2020 11:36 PM, Stanimir Varbanov wrote:
Hi Rajendra,
After applying 2,3 and 4/5 patches on linaro-integration v5.8-rc2 I see
below messages on db845:
qcom-venus aa0.video-codec: dev_pm_opp_set_rate: failed
loop we
currently have today.
Cc: Douglas Anderson
Cc: Maulik Shah
Cc: Lina Iyer
Signed-off-by: Stephen Boyd
---
drivers/soc/qcom/rpmh-internal.h | 2 +
drivers/soc/qcom/rpmh-rsc.c | 101 ---
2 files changed, 41 insertions(+), 62 deletions(-)
diff --git a/drivers
On Thu, Jun 18 2020 at 07:06 -0600, Maulik Shah wrote:
Currently rpmh_invalidate() always returns success. Update its
return type to void.
Suggested-by: Stephen Boyd
Signed-off-by: Maulik Shah
Reviewed-by: Lina Iyer
---
drivers/interconnect/qcom/bcm-voter.c | 6 +-
drivers/soc/qcom
driver hooks
explicitly.
Thanks to Saravana for his help on pointing out the
IRQCHIP_DECLARE issue and guidance on a solution.
Cc: Andy Gross
Cc: Bjorn Andersson
Cc: Joerg Roedel
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: Linus Walleij
Cc: Lina Iyer
Cc: Saravana Kannan
Cc
driver hooks
explicitly.
Thanks to Saravana for his help on pointing out the
IRQCHIP_DECLARE issue and guidance on a solution.
Cc: Andy Gross
Cc: Bjorn Andersson
Cc: Joerg Roedel
Cc: Thomas Gleixner
Cc: Jason Cooper
Cc: Marc Zyngier
Cc: Linus Walleij
Cc: Lina Iyer
Cc: Saravana Kannan
Cc
On Fri, Sep 20 2019 at 16:22 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-09-11 09:15:57)
On Thu, Sep 05 2019 at 18:39 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2019-08-29 11:11:51)
>> When an interrupt is to be serviced, the convention is to mask the
>> interr
Adding Sibi
On Fri, Sep 13 2019 at 13:53 -0600, Lina Iyer wrote:
Sorry, I couldn't get to this earlier.
On Thu, Sep 05 2019 at 18:03 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-09-03 10:07:22)
On Mon, Sep 02 2019 at 07:58 -0600, Marc Zyngier wrote:
On 02/09/2019 14:38, Rob Herring
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index be0022e..41455b8 100644
Some interrupt controllers in a SoC, are always powered on and have a
select interrupts routed to them, so that they can wakeup the SoC from
suspend. Add wakeup-parent DT property to refer to these interrupt
controllers.
Cc: devicet...@vger.kernel.org
Signed-off-by: Lina Iyer
Reviewed-by: Rob
parent.
Co-developed-by: Stephen Boyd
Signed-off-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
Changes in RFC v2:
- Move irq_domain_qcom_handle_wakeup to the patch where it is
used
- Replace #define definitons
- Add Signed-off-by and other minor changes
was
used as a GPIO.
Signed-off-by: Maulik Shah
[updated commit text]
Signed-off-by: Lina Iyer
---
drivers/irqchip/qcom-pdc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index affb0bfa..2b49e70 100644
Enable PDC interrupt controller for SDM845 devices. The interrupt
controller can detect wakeup capable interrupts when the SoC is in a low
power state.
Signed-off-by: Lina Iyer
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b
PDC always-on interrupt controller can detect certain GPIOs even when
the TLMM interrupt controller is powered off. Link the PDC as TLMM's
wakeup parent.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts
with the wakeup interrupt controller
and ensure the wakeup GPIOs are handled correctly.
Signed-off-by: Maulik Shah
Signed-off-by: Lina Iyer
Changes in RFC v2:
- Define irq_domain_qcom_handle_wakeup()
- Rebase on top of GPIO hierarchy support in linux-next
- Set
the interrupt before enabling the
interrupt.
Signed-off-by: Maulik Shah
[updated commit text and minor code fixes]
Signed-off-by: Lina Iyer
---
Changes in RFC v2 -
- Rephrase commit text
- Address code review comments
---
include/linux/irq.h | 6 ++
kernel/irq/chip.c | 44
Add interrupt parents for wakeup capable GPIOs for Qualcomm SDM845 SoC.
Signed-off-by: Lina Iyer
---
Changes in RFC v2:
- Rearranged GPIO wakeup parent map
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 23 ++-
1 file changed, 22 insertions(+), 1 deletion(-)
diff --git
differently. So, in
addition to configuring the PDC, configure the interface registers as
well.
Signed-off-by: Lina Iyer
---
drivers/irqchip/qcom-pdc.c | 93 ++
1 file changed, 93 insertions(+)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom
Newer SoCs have increased the number of interrupts routed to the PDC
interrupt controller. Update the definition of max PDC interrupts.
Signed-off-by: Lina Iyer
---
drivers/irqchip/qcom-pdc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/irqchip/qcom-pdc.c b
://lore.kernel.org/linux-gpio/20190808123242.5359-1-linus.wall...@linaro.org/
[2]. https://lkml.org/lkml/2019/5/7/1173
[3]. https://lore.kernel.org/r/20190819084904.30027-1-linus.wall...@linaro.org
[4]. https://lore.kernel.org/r/20190724083828.7496-1-linus.wall...@linaro.org
Lina Iyer (12):
irqdomain: add
token"
that indicates the wake-up domain. This slightly abuses the notion of
bus, but also radically simplifies the design of such a driver. Between
two evils, we choose the least damaging.
Suggested-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
include/linux/irqdomain.h | 1 +
1 file changed, 1 insertio
the PDC when the IRQ is masked and unmasked, instead
use the irq_enable/irq_disable callbacks to toggle the IRQ_ENABLE
register at the PDC. The PDC's IRQ_ENABLE register is only used during
the monitoring mode when the system is asleep and is not needed for
active mode detection.
Signed-off-by: Lina Iyer
the firmware using the SCM interface. Add a flag to indicate if the
register is to be written using SCM interface.
Cc: devicet...@vger.kernel.org
Signed-off-by: Lina Iyer
---
.../devicetree/bindings/interrupt-controller/qcom,pdc.txt | 13 -
1 file changed, 12 insertions(+), 1 deletion
Sorry, I couldn't get to this earlier.
On Thu, Sep 05 2019 at 18:03 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-09-03 10:07:22)
On Mon, Sep 02 2019 at 07:58 -0600, Marc Zyngier wrote:
>On 02/09/2019 14:38, Rob Herring wrote:
>> On Thu, Aug 29, 2019 at 12:11:54PM -0600, Lina I
On Wed, Sep 11 2019 at 04:19 -0600, Linus Walleij wrote:
On Thu, Aug 29, 2019 at 7:35 PM Lina Iyer wrote:
Replace gpiochip_irqchip_add() and gpiochip_set_chained_irqchip() calls
by populating the gpio_irq_chip data structures instead.
Signed-off-by: Lina Iyer
This is mostly fixed upstream
On Thu, Sep 05 2019 at 18:39 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-08-29 11:11:51)
When an interrupt is to be serviced, the convention is to mask the
interrupt at the chip and unmask after servicing the interrupt. Enabling
and disabling the interrupt at the PDC irqchip causes
On Wed, Sep 11 2019 at 04:05 -0600, Linus Walleij wrote:
On Thu, Aug 29, 2019 at 8:47 PM Lina Iyer wrote:
+- qcom,scm-spi-cfg:
+ Usage: optional
+ Value type:
+ Definition: Specifies if the SPI configuration registers have to be
+ written from the firmware
On Mon, Sep 02 2019 at 07:58 -0600, Marc Zyngier wrote:
On 02/09/2019 14:38, Rob Herring wrote:
On Thu, Aug 29, 2019 at 12:11:54PM -0600, Lina Iyer wrote:
In addition to configuring the PDC, additional registers that interface
the GIC have to be configured to match the GPIO type. The registers
On Fri, Aug 30 2019 at 08:50 -0600, Marc Zyngier wrote:
[Please use my kernel.org address in the future. The days of this
arm.com address are numbered...]
Sure, will update and repost.
On 29/08/2019 19:11, Lina Iyer wrote:
Introduce a new domain for wakeup capable GPIOs. The domain can
token"
that indicates the wake-up domain. This slightly abuses the notion of
bus, but also radically simplifies the design of such a driver. Between
two evils, we choose the least damaging.
Suggested-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
include/linux/irqdomain.h | 1 +
1 file changed, 1 insertio
the firmware using the SCM interface. Add a flag to indicate if the
register is to be written using SCM interface.
Cc: devicet...@vger.kernel.org
Signed-off-by: Lina Iyer
---
.../bindings/interrupt-controller/qcom,pdc.txt | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff
with the wakeup interrupt controller
and ensure the wakeup GPIOs are handled correctly.
Signed-off-by: Maulik Shah
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-msm.c | 114 +
drivers/pinctrl/qcom/pinctrl-msm.h | 16
2 files changed, 130 insertions
differently. So, in
addition to configuring the PDC, configure the interface registers as
well.
Signed-off-by: Lina Iyer
---
drivers/irqchip/qcom-pdc.c | 93 ++
1 file changed, 93 insertions(+)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
index
is enabled
as an interrupt.
Please consider reviewing these patches.
Thanks,
Lina
Lina Iyer (12):
irqdomain: add bus token DOMAIN_BUS_WAKEUP
drivers: irqchip: pdc: Do not toggle IRQ_ENABLE during mask/unmask
drivers: irqchip: add PDC irqdomain for wakeup capable GPIOs
of: irq: document
PDC always-on interrupt controller can detect certain GPIOs even when
the TLMM interrupt controller is powered off. Link the PDC as TLMM's
wakeup parent.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts
Some interrupt controllers in a SoC, are always powered on and have a
select interrupts routed to them, so that they can wakeup the SoC from
suspend. Add wakeup-parent DT property to refer to these interrupt
controllers.
Cc: devicet...@vger.kernel.org
Signed-off-by: Lina Iyer
---
.../bindings
From: Maulik Shah
Add irqchip calls to set/get interrupt status from the parent interrupt
controller.
Signed-off-by: Maulik Shah
---
drivers/irqchip/qcom-pdc.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/drivers/irqchip/qcom-pdc.c b/drivers/irqchip/qcom-pdc.c
From: Maulik Shah
On certain QTI chipsets some GPIOs are direct-connect interrupts
to the GIC.
Even when GPIOs are not used for interrupt generation and interrupt
line is disabled, it does not prevent interrupt to get pending at
GIC_ISPEND. When drivers call enable_irq unwanted interrupt
Replace gpiochip_irqchip_add() and gpiochip_set_chained_irqchip() calls
by populating the gpio_irq_chip data structures instead.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-msm.c | 28 +---
1 file changed, 13 insertions(+), 15 deletions(-)
diff --git
Enable PDC interrupt controller for SDM845 devices. The interrupt
controller can detect wakeup capable interrupts when the SoC is in a low
power state.
Signed-off-by: Lina Iyer
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b
parent.
Co-developed-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
drivers/irqchip/qcom-pdc.c | 104 ---
include/linux/soc/qcom/irq.h | 34
2 files changed, 129 insertions(+), 9 deletions(-)
create mode 100644 include/linux/soc/qcom/irq.h
diff
Add interrupt parents for wakeup capable GPIOs for Qualcomm SDM845 SoC.
Signed-off-by: Lina Iyer
---
drivers/pinctrl/qcom/pinctrl-sdm845.c | 83 ++-
1 file changed, 82 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/qcom/pinctrl-sdm845.c
b/drivers/pinctrl
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi
b/arch/arm64/boot/dts/qcom/sdm845.dtsi
index be0022e09465
the PDC when the IRQ is masked and unmasked, instead
use the irq_enable/irq_disable callbacks to toggle the IRQ_ENABLE
register at the PDC. The PDC's IRQ_ENABLE register is only used during
the monitoring mode when the system is asleep and is not needed for
active mode detection.
Signed-off-by: Lina Iyer
On Mon, Jul 29 2019 at 14:56 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-07-29 12:01:39)
On Thu, Jul 25 2019 at 09:44 -0600, Doug Anderson wrote:
>On Thu, Jul 25, 2019 at 8:18 AM Lina Iyer wrote:
>>
>> On Wed, Jul 24 2019 at 17:28 -0600, Doug Anderson wrote:
>> >
On Thu, Jul 25 2019 at 09:44 -0600, Doug Anderson wrote:
Hi,
On Thu, Jul 25, 2019 at 8:18 AM Lina Iyer wrote:
On Wed, Jul 24 2019 at 17:28 -0600, Doug Anderson wrote:
>Hi,
>
>On Wed, Jul 24, 2019 at 1:36 PM Lina Iyer wrote:
>>
>> On Wed, Jul 24 2019 at 13:38 -060
On Wed, Jul 24 2019 at 17:28 -0600, Doug Anderson wrote:
Hi,
On Wed, Jul 24, 2019 at 1:36 PM Lina Iyer wrote:
On Wed, Jul 24 2019 at 13:38 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2019-07-24 07:52:51)
>> On Tue, Jul 23 2019 at 14:11 -0600, Stephen Boyd wrote:
>> >
On Wed, Jul 24 2019 at 13:38 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-07-24 07:52:51)
On Tue, Jul 23 2019 at 14:11 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2019-07-22 14:53:38)
>> Avoid locking in the interrupt context to improve latency. Since we
>> don't lock i
On Wed, Jul 24 2019 at 12:32 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-07-24 07:54:52)
On Tue, Jul 23 2019 at 14:19 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2019-07-23 12:21:59)
>> On Tue, Jul 23 2019 at 12:22 -0600, Stephen Boyd wrote:
>> >Can you keep irq sa
On Tue, Jul 23 2019 at 14:19 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-07-23 12:21:59)
On Tue, Jul 23 2019 at 12:22 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2019-07-22 14:53:37)
>> From: "Raju P.L.S.S.S.N"
>>
>> The tcs->lock was introduced to
On Tue, Jul 23 2019 at 14:11 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-07-22 14:53:38)
Avoid locking in the interrupt context to improve latency. Since we
don't lock in the interrupt context, it is possible that we now could
race with the DRV_CONTROL register that writes the enable
On Tue, Jul 23 2019 at 12:22 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-07-22 14:53:37)
From: "Raju P.L.S.S.S.N"
The tcs->lock was introduced to serialize access with in TCS group. But,
drv->lock is still needed to synchronize core aspects of the
communication. This pu
.N
Signed-off-by: Lina Iyer
---
drivers/soc/qcom/rpmh-internal.h | 4 ++--
drivers/soc/qcom/rpmh-rsc.c | 2 +-
drivers/soc/qcom/rpmh.c | 21 -
3 files changed, 11 insertions(+), 16 deletions(-)
diff --git a/drivers/soc/qcom/rpmh-internal.h b/drivers/soc
ides the all necessary
synchronization. So remove locking around TCS group and simply use the
drv->lock instead.
Signed-off-by: Raju P.L.S.S.S.N
[ilina: split patch into multiple files, update commit text]
Signed-off-by: Lina Iyer
---
Changes in v2:
- Split the patches into multiple
Since drv->tcs_in_use is updated when the DRV_STATUS is updated, we
could simply use the former to determine if the TCS is idle or not.
Therefore, remove redundant TCS register read.
Signed-off-by: Lina Iyer
---
drivers/soc/qcom/rpmh-rsc.c | 3 +--
1 file changed, 1 insertion(+), 2 deleti
.
Signed-off-by: Lina Iyer
---
drivers/soc/qcom/rpmh-rsc.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc/qcom/rpmh-rsc.c
index 5ede8d6de3ad..694ba881624e 100644
--- a/drivers/soc/qcom/rpmh-rsc.c
+++ b/drivers/soc/qcom/rpmh-rsc.c
On Mon, Jul 22 2019 at 12:18 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-07-22 09:20:03)
On Fri, Jul 19 2019 at 12:20 -0600, Stephen Boyd wrote:
>Quoting Lina Iyer (2019-07-01 08:29:06)
>> From: "Raju P.L.S.S.S.N"
>>
>> tcs->lock was introduced to
On Fri, Jul 19 2019 at 12:20 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-07-01 08:29:06)
From: "Raju P.L.S.S.S.N"
tcs->lock was introduced to serialize access with in TCS group. But
even without tcs->lock, drv->lock is serving the same purpose. So
use a single
On Fri, Jul 19 2019 at 12:22 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-07-01 08:29:07)
When triggering a TCS to send its contents, reading back the trigger
value may return an incorrect value. That is because, writing the
trigger may raise an interrupt which could be handled
explicitly switch to Platform Coordinated mode during boot.
> >
> > Finally, the actual initialization of the PM domain data structures, is
> > done via calling the new shared function, psci_dt_init_pm_domains().
> > However, this is implemented by subsequent changes.
> >
On Thu, Jul 18 2019 at 10:55 -0600, Ulf Hansson wrote:
On Thu, 18 Jul 2019 at 15:31, Lorenzo Pieralisi
wrote:
On Thu, Jul 18, 2019 at 12:35:07PM +0200, Ulf Hansson wrote:
> On Tue, 16 Jul 2019 at 17:53, Lorenzo Pieralisi
> wrote:
> >
> > On Mon, May 13, 2019 at 09:22:56PM +0200, Ulf Hansson
On Tue, Jul 16 2019 at 08:47 -0600, Sudeep Holla wrote:
On Mon, May 13, 2019 at 09:22:59PM +0200, Ulf Hansson wrote:
From: Lina Iyer
In the hierarchical layout, we are creating power domains around each CPU
and describes the idle states for them inside the power domain provider
node. Note
Switching Andy's email address.
On Mon, Jul 01 2019 at 09:32 -0600, Lina Iyer wrote:
When triggering a TCS to send its contents, reading back the trigger
value may return an incorrect value. That is because, writing the
trigger may raise an interrupt which could be handled immediately
Switching Andy's email address.
On Mon, Jul 01 2019 at 09:32 -0600, Lina Iyer wrote:
From: "Raju P.L.S.S.S.N"
tcs->lock was introduced to serialize access with in TCS group. But
even without tcs->lock, drv->lock is serving the same purpose. So
use a single drv->lock
ear_bit() is
atomic.
- Remove redundant read of TCS registers.
- Use spin_lock instead of _irq variants as the locks are not held
in interrupt context.
Fixes: 658628 ("drivers: qcom: rpmh-rsc: add RPMH controller for QCOM
SoCs")
Signed-off-by: Raju P.L.S.S.S.N
Signed-off-by: Lina
spinning waiting for the value we wrote.
Fixes: 658628 ("drivers: qcom: rpmh-rsc: add RPMH controller for QCOM
SoCs")
Signed-off-by: Lina Iyer
---
drivers/soc/qcom/rpmh-rsc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/qcom/rpmh-rsc.c b/drivers/soc
Setup PDC wakeup parent for TLMM for SDM845 SoC.
Signed-off-by: Lina Iyer
---
Changes in v3:
- Provide irqdomain-map for GPIOs that map to PDC
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 79
1 file changed, 79 insertions(+)
diff --git a/arch/arm64/boot/dts
fwspec.
The solution to this problem is still at large and I would like to
solicit feedback on this.
Appreciate your time.
Thanks,
Lina
[1]. https://patchwork.kernel.org/cover/10851807/
Lina Iyer (9):
gpio: allow gpio_to_irq to use OF variants for gpiochips
irqdomain: add bus token DOMAIN_BUS_
Enable PDC interrupt controller for SDM845 devices. The interrupt
controller can detect wakeup capable interrupts when the SoC is in a low
power state.
Signed-off-by: Lina Iyer
---
arch/arm64/configs/defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/configs/defconfig b
interrupt map.
Cc: devicet...@vger.kernel.org
Signed-off-by: Lina Iyer
---
.../bindings/pinctrl/qcom,sdm845-pinctrl.txt | 79 ++-
1 file changed, 78 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/pinctrl/qcom,sdm845-pinctrl.txt
b/Documentation/devicetree
needs to exist to associate the same interrupt line on multiple
interrupt controllers. Providing this map in every driver is cumbersome.
Let's add this in the device tree and document the properties to map the
interrupt specifiers
Cc: devicet...@vger.kernel.org
Signed-off-by: Lina Iyer
-by: Lina Iyer
---
drivers/gpio/gpiolib.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/gpio/gpiolib.c b/drivers/gpio/gpiolib.c
index 4a9a6d4afe6e..77317435e2b2 100644
--- a/drivers/gpio/gpiolib.c
+++ b/drivers/gpio/gpiolib.c
@@ -1825,6 +1825,19 @@ EXPORT_SYMBOL_GPL
token"
that indicates the wake-up domain. This slightly abuses the notion of
bus, but also radically simplifies the design of such a driver. Between
two evils, we choose the least damaging.
Suggested-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
Changes in v4:
- Update commit text
---
inc
parent.
Co-developed-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
Changes in v5:
- Define invalid wakeup interrupt
Changes in v4:
- Remove vestigial changes from v2
Changes in v3:
- Remove PDC GPIO map data (moved to DT)
- hwirq passed in .alloc() is a PDC pin now
Add PDC interrupt controller device bindings for SDM845.
Signed-off-by: Lina Iyer
---
Changes in v1:
- Use updated address specification in reg
- Rename to pdc_intc
- Sort per address in DT
---
arch/arm64/boot/dts/qcom/sdm845.dtsi | 9 +
1 file changed, 9
as the
TLMM and therefore the GPIOs need to be masked at TLMM to avoid
duplicate interrupts. To enable both these configurations to exist,
allow the parent irqchip to dictate the TLMM irqchip's behavior when
masking/unmasking the interrupt.
Co-developed-by: Stephen Boyd
Signed-off-by: Lina Iyer
be a
parent to other interrupt controllers and program additional registers
when an IRQ has its wake capability enabled or disabled.
Signed-off-by: Thierry Reding
Signed-off-by: Lina Iyer
---
drivers/gpio/gpiolib.c | 15 +++
include/linux/gpio/driver.h | 6 ++
2 files
t specifier from the map to irq_fwspec per the mask in
irqdomain-map-pass-thru property for the matched interrupt.
Signed-off-by: Stephen Boyd
Signed-off-by: Lina Iyer
---
Changes in v5:
- Fix returning 0 when no match is found
Changes in v4:
- Fix commit text spelling and v
On Wed, Apr 17 2019 at 07:59 -0600, Linus Walleij wrote:
On Thu, Mar 21, 2019 at 10:54 PM Stephen Boyd wrote:
Quoting Marc Zyngier (2019-03-16 04:39:48)> > On Fri, 15 Mar 2019 09:28:31 -0700
> Stephen Boyd wrote:
>
> > Quoting Lina Iyer (2019-03-13 14:18:41)
> > > @
On Fri, Mar 15 2019 at 10:28 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-03-13 14:18:41)
---
Changes in v4:
- Remove irq_set_wake() on summary IRQ interrupt
Changes in v3:
- Use of_irq_domain_map() and pass PDC pin to parent irqdomain
Changes in v2:
- Call parent
On Thu, Mar 21 2019 at 15:54 -0600, Stephen Boyd wrote:
Quoting Marc Zyngier (2019-03-16 04:39:48)
On Fri, 15 Mar 2019 09:28:31 -0700
Stephen Boyd wrote:
> Quoting Lina Iyer (2019-03-13 14:18:41)
> > @@ -994,6 +1092,22 @@ static int msm_gpio_init(struct msm_pinctrl *pctrl)
> >
On Tue, Apr 16 2019 at 10:54 -0600, Stephen Boyd wrote:
Quoting Lina Iyer (2019-04-04 08:58:38)
On Mon, Mar 18 2019 at 11:54 -0600, Marc Zyngier wrote:
>On Wed, 13 Mar 2019 15:18:37 -0600
>Lina Iyer wrote:
>
>Please do Cc Rob when posting DT related patches.
>
>> Some
On Mon, Apr 15 2019 at 06:42 -0600, Marc Zyngier wrote:
On 04/04/2019 16:58, Lina Iyer wrote:
On Mon, Mar 18 2019 at 11:54 -0600, Marc Zyngier wrote:
On Wed, 13 Mar 2019 15:18:37 -0600
Lina Iyer wrote:
Please do Cc Rob when posting DT related patches.
Some interrupt controllers in a SoC
On Mon, Apr 15 2019 at 06:43 -0600, Marc Zyngier wrote:
On 13/03/2019 21:18, Lina Iyer wrote:
Hi all,
This series adds support for wakeup capable GPIOs. It is based on Thierry's
hiearchical GPIO domains. This approach is based on Stephen's idea [1]. The SoC
that is used for this development
On Mon, Mar 18 2019 at 11:54 -0600, Marc Zyngier wrote:
On Wed, 13 Mar 2019 15:18:37 -0600
Lina Iyer wrote:
Please do Cc Rob when posting DT related patches.
Some interrupt controllers in a SoC, are always powered on and have a
select interrupts routed to them, so that they can wakeup
I observed an issue with return value being set to 0, when a match is
not found in the irqdomain-map.
On Wed, Mar 13 2019 at 15:20 -0600, Lina Iyer wrote:
From: Stephen Boyd
Sometimes interrupts are routed from an interrupt controller to another
in no specific order. Having
Thanks for the review Rob.
On Fri, Mar 15 2019 at 17:37 -0600, Rob Herring wrote:
On Wed, Mar 13, 2019 at 03:18:40PM -0600, Lina Iyer wrote:
SDM845 SoC has an always-on interrupt controller (PDC) with select GPIO
routed to the PDC as interrupts that can be used to wake the system up
from deep
be a
parent to other interrupt controllers and program additional registers
when an IRQ has its wake capability enabled or disabled.
Signed-off-by: Thierry Reding
Signed-off-by: Lina Iyer
---
drivers/gpio/gpiolib.c | 15 +++
include/linux/gpio/driver.h | 6 ++
2 files
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