I'd rather get the raw book in whatever format it is. Of course, this might
lead to people making their own changes. Which might be what IBM is wanting to
avoid. The documentation equivalent of OCO.
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151
I despise InfoCenter. Try here:
http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/Shelves for BookManager +
PDF. I use either
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151 Boulevard 26 * N. Richland Hills * TX 76010
(817) 255-3225 phone *
2012 15:38:32 -0600 McKown, John
john.mck...@healthmarkets.com wrote:
:OK, since I have you here anyway. What about a real weirdie? An
instruction which says whether or not to execute the next instruction,
based on the condition code? That would enable every instruction to be
a conditional
It's the holiday season. So be nice.
There currently exist 2 execute variants. The old base+displacement and the new
relative. Now that we have 64 bit registers, why not have an RR instruction
where the first register the modifying value but the second register contains
the actual instruction
.
You mean like LOAD ON CONDITION and STORE ON CONDITION?
They were added in the 9th edition of the POPS.
Robert Ngan
CSC Financial Services Group
From: McKown, John john.mck...@healthmarkets.com
To: ASSEMBLER-LIST@listserv.uga.edu
Date: 2012/11/26 15:39
Subject:Stupid
I likely want something that is really impossible. I would like to write a
macro which does not specify any parameters, but can dynamically detect them in
the macro itself. For positional parameters, this could likely be easy via
SYSLIST. Something like:
MACRO
LBL MYMAC
LBL EQU *
LCLA I
Ah. I can see how that would be easy to do (0011 == 11 decimal == b'1011'). I
guess the byte after the HALFWORD just happened to contain x'00'.
It's always Friday somewhere.
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151 Boulevard 26 * N. Richland
I may be the lone voice of dissent on this. I really don't like magic values
and rarely like literals. In the case given
IC R0,=AL1(1,0,2,3,4,0)(R7)
In my weirdness, I might code this like:
IC R0,UNDERSTANDABLE_NAME(R7)
Where UNDERSTANDABLE_NAME would be a SETC or GLBC symbol set at
I know where our love of putting sequence numbers in columns 73-80 comes
from. But the only thing that I know of that continues to really use them is
IEBUPDTE. So I'm wondering if it is really worth the bother to have them
anymore. Now, most here would likely say what bother? ISPF makes it
What! You don't have an IBM 088 collator handy? How do you do daily processing?
grin/
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151 Boulevard 26 * N. Richland Hills * TX 76010
(817) 255-3225 phone *
john.mck...@healthmarkets.com *
So, in summary, use them or not as the individual or company dictates. I don't
really lose any capability by keeping my source as I do, without sequence
numbers.
Thanks to all. It was interesting to read that some still do have a use for
these.
--
John McKown
Systems Engineer IV
IT
It is curious to me that curiosity is spelled without the u. That's why I
consistently misspell it. Cursed be Webster grin/.
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151 Boulevard 26 * N. Richland Hills * TX 76010
(817) 255-3225 phone *
Yes, and also must update the BASETAB and BASETAB2 tables appropriately.
Alternately, you could extend to base 62 by using lower case letters as well.
I.e. 0-9A-Za-z . But most people don't seem to like to distinguish between
upper and lower case. Especially old tyme mainframers.
--
John
Neat! I hope they back port it to z/OS 1.12 (which I am stuck at). Much nicer
that having multiple VCONs, then doing a series of LTs to see which was
resolved and use the one first which did.
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151 Boulevard
That's what it looks like to me. Instead of something like:
WXTRN PGM1
WXTRN PGM2
WXTRN PGM3
...
LHI R1,=A((VCON3-VCON1)/4)
LA R14,VCON1
FINDVCON DS 0H
LT R15,0(,R14)
JNZ GOTVCON
LA R14,4(,R14)
JCT R1,FINDVCON
J NO_VCON
GOTVCON DS 0H
CALL (15),...
...
VCON1 DC
In your scenario, where the non-TS code uses a pointer some time later, then
it can suffer a problem because the TS code is not interrupted (because it is
run after the non-TS code fetches the pointer), nor is the non-TS code
interrupted (because it isn't TS code). To be absolutely safe, the
http://www.anandtech.com/show/6290/making-sense-of-intel-haswell-transactional-synchronization-extensions
quote from second page
The new Transactional Synchronization eXtensions (TSX) extend the x86 ISA with
two new interfaces: HLE and RTM.
Restricted Transactional Memory (RTM) uses Xbegin and
Cole
At 9/18/2012 02:57 PM, McKown, John wrote:
Thanks, that makes a lot of sense. It is for updating Read Mostly
Memory. Since the death of PLMs, I really don't know much about
internals any more. I now tend to be a strict GUPI type of
programmer. Do you happen to know of a z/OS data
I must have total misunderstood TS state. I was under the impression that the
TS would abort if *any* code read or updated any storage updated by the TS
code. TS state should abort if any interrupt occurs while in TS state, even an
I/O or External (e.g. timer) interrupt.
This means that the
Ben's objection, if a scanner is not in the TS state, then (as
Ben points out) he can quite easily be delayed. This is why my prior
understanding was incorrect. And this is why both scanners and
updaters all need to be in the TS state.
Dave
At 9/19/2012 08:52 AM, McKown, John wrote:
I must
Insurance Company of TennesseeSM and The
MEGA Life and Health Insurance Company.SM
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-
l...@listserv.uga.edu] On Behalf Of McKown, John
Sent: Wednesday, September 19, 2012 9:12 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
@LISTSERV.UGA.EDU
Subject: Re: The Transaction state (correction)
On Wed, 19 Sep 2012 09:11:40 -0500, McKown, John wrote:
I don't see how Routine B can free block X. Routine B
cannot do a FREEMAIN or a STORAGE RELEASE as these
invoke Restricted instructions (SVC or PC).
No, but it can unlink
: Tuesday, September 18, 2012 12:12 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Model 2827 New Instructions
On 5 September 2012 11:52, McKown, John john.mck...@healthmarkets.com
wrote:
The link worked for me, but only after I logged into IBMLink. The
data pasted is basically all
Damn, it's 100 years until that Share presentation? Or, by chance, did you mean
2013? GRIN
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151 Boulevard 26 * N. Richland Hills * TX 76010
(817) 255-3225 phone *
john.mck...@healthmarkets.com *
Mainframe Assembler List [mailto:ASSEMBLER-
l...@listserv.uga.edu] On Behalf Of Mike Shaw
Sent: Tuesday, September 18, 2012 12:39 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Model 2827 New Instructions
On Tue, Sep 18, 2012 at 1:23 PM, McKown, John
john.mck...@healthmarkets.com
wrote
I just read up on the Transaction Execution. I now need two things: 1. Aspirin;
2. a nap. I get the general concept, but the restrictions are immense. I guess
it is good for a *very* short routine which does not update very much storage.
The conditions under which it can abort are a multitude.
Fox Hollow RoadVOICE:540-456-8536
Afton, VA 22920FAX: 540-456-6658
At 9/18/2012 02:20 PM, McKown, John wrote:
I just read up on the Transaction Execution. I now need two things:
1. Aspirin; 2. a nap. I get the general concept, but the
restrictions are immense. I guess
The link worked for me, but only after I logged into IBMLink. The data pasted
is basically all that is on the page. It does not appear that the newest PoPS
is available yet. I can normally find it on ResourceLink when I click on the
Library for the specific processor.
--
John McKown
Systems
First, the ATTACHing task can just do a DETACH of the child task. However, this
likely will cause an abend of the child with a S33E abend, which shows up on
the SYSLOG. I've never done a STIMERM so I cannot really comment on the rest of
your question. When I do this sort of thing, I have always
, 2012 6:35 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: which instructions should I use?
On 28 August 2012 11:24, McKown, John john.mck...@healthmarkets.com
wrote:
Yes, but I cannot simply relate the such and such facility to an
actual processor. Except by looking at the documentation
Value to be tested is in a register, not storage. On the newer machines, the
TMLL instruction can do this. But I run on a z9BC.
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151 Boulevard 26 * N. Richland Hills * TX 76010
(817) 255-3225 phone *
That is a RISC-like approach. I have read a bit on the ARM architecture and was
impressed by it. It does have a condition code register. And most of the
instructions have a mask which makes their execution conditional on the CC
register, like a branch is conditional on the CC.
--
John McKown
: Re: which instructions should I use?
TMLL was included with the first set of Relative and Immediate
instructions
way back on the 9672-G2. If you are willing to use AHI and BRC, then
there
is not reason not to use TMLL.
On Tue, 28 Aug 2012 07:27:59 -0500, McKown, John wrote:
Value
Yes, but I cannot simply relate the such and such facility to an actual
processor. Except by looking at the documentation for the processor. I would
like the reverse mapping. I.e. look for such and such facility and get a list
of current processors which support it. I am not aware of such a
Insurance Company.SM
-Original Message-
From: IBM Mainframe Assembler List [mailto:ASSEMBLER-
l...@listserv.uga.edu] On Behalf Of Robin Vowels
Sent: Tuesday, August 28, 2012 10:21 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: which instructions should I use?
From: McKown, John
*-4 EQU *
Oh, I love it! My immediate thought, as intended I'm sure, was that *-4 is
not a valid symbol and would cause an assembler error. Then the backbrain
slapped the forebrain saying * in position means it's a comment, you idiot!
--
John McKown
Systems Engineer IV
IT
Administrative
What is your RMODE? If you look at your last ECB pointer, you have
DC X'80'
DC AL3(ECB$REFRESH)
This means that ECB$REFRESH *must* be in RMODE(24) storage. Try replacing those
two statements with:
DC A(ECB$REFRESH+X'8000')
--
John McKown
Systems Engineer IV
IT
Administrative
I agree. Of course, you still need base+displacement in two cases that I can
think of: (1) desire for an index register; and (2) to access dynamic storage
(STORAGE OBTAIN or LOADed module).
As an example of (1), I quite often do:
CALL PROGRAM,(PARM1,PARM2),VL
CHI
That using z/OS on Hercules is not PC (Politically Correct).
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151 Boulevard 26 * N. Richland Hills * TX 76010
(817) 255-3225 phone *
john.mck...@healthmarkets.com * www.HealthMarkets.com
Confidentiality
Thanks for the technique. I'm not sure that I like the NILL instruction at this
point. It could change an invalid (as in not planned for) RC into a valid
RC. Looks like maybe I could use TMLL to just test. (TMLL R15,X'000C')
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
that something akin to the
MACHINE option should be available as a system variable, say
SYSM_MACHINE, that could be interrogated within a macro to produce
different code for different target machines.
--jg
On 8/27/12, McKown, John john.mck...@healthmarkets.com wrote:
Destroys the contents of R15
Mainframe Assembler List [mailto:ASSEMBLER-
l...@listserv.uga.edu] On Behalf Of Binyamin Dissen
Sent: Monday, August 27, 2012 3:01 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: which instructions should I use?
On Mon, 27 Aug 2012 14:13:12 -0500 McKown, John
john.mck
Most of the time, people will do something like:
UNPK C_RC(L'C_RC+1),RC(L'RC)
TR C_RC,TOHEX-C'0'
...
TOHEX DC C'0123456789ABCDEF'
C_RC DS CL8
C_RC_1 DS C NEEDED FOR PADDING
RCDS F
RC_1 DS C NEEDED FOR PADDING
The above UNPK instruction places an F nybble in front of every
You don't have the proper setup at the start of your CICS code. You can't use
standard OS linkage setup.
You have:
SETOPTI CSECT
STM R14,R12,12(R13)* SAVE CALLER'S REGS
USING SETOPTI,R12 * R12 IS BASE
STR13,SAVEAREA+4
LA
Insurance Company of TennesseeSM and The
MEGA Life and Health Insurance Company.SM
-Original Message-
From: IBM Mainframe Assembler List
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of McKown, John
Sent: Friday, July 27, 2012 9:47 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject
-Original Message-
From: IBM Mainframe Assembler List
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Paul Gilmartin
Sent: Thursday, July 12, 2012 10:59 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Subject: AW: ** ASMA030E Invalid literal usage -
=CL8'MARTINWH'
snip
-Original Message-
From: IBM Mainframe Assembler List
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of John Gilmore
Sent: Monday, July 02, 2012 9:37 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Detecting RMODE at assembly time
Paul Gilmartin wrote
begin extract
I agree, using 64-bit common storage would likely be a good idea. Or maybe
not, since it is what __I__ would do. grin
http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/IEA2A570/4.7.4
Also, IIRC, some code will create a COMMON dataspace and assign ownership to
*MASTER*.
--
John McKown
I echo your comments. Well done, Mr. Ehrman and associates. Good on ya, mate!
(in deference to the people in Perth)
I just wish that z/OS UNIX had been around back then and strategic. The only
thing missing, IMO, is native support of z/OS UNIX files. I.e. being able
to COPY
OK, I can live with jumpify. I would just like something that is generally
acceptable to the community. Only minus is that it doesn't say anything about
the use of Relative and Immediate instructions. Of which I am also a big fan.
--
John McKown
Systems Engineer IV
IT
Administrative Services
as a nonce word, in, say, EJ's title.
It is nevertheless barbarous English and should not be adopted for
routine use.
JRI?
--jg
On 6/19/12, McKown, John john.mck...@healthmarkets.com wrote:
OK, I can live with jumpify. I would just like something that is
generally acceptable to the community
I'm not entirely sure exactly what you want. But one thing that I do is use the
Assembler parm MACHINE(architecture) to indicate my highest level instruction
set. E.g. I use //ASM EXEC PGM=ASMA90,PARM='MACHINE(ZSERIES-3)' to cause an
assembler error if I were to use EXRL other instruction which
-Original Message-
From: IBM Mainframe Assembler List
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of John Ehrman
Sent: Tuesday, June 19, 2012 11:55 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Base registers
... I prefer using Branch Relative, Relative (such as LARL
To: IBM Mainframe Assembler List
Cc: McKown, John
Subject: Re: Checking for more restrictive
TYPECHECK(REGISTER) at assemble time
LLH comes in at MACHINE(ZS-3), so the macro substitutes for
LLH if assembled
with MACHINE(ZS-2) and earlier. (O' is a nice addition.)
I'm using a combination of LH
-Original Message-
From: IBM Mainframe Assembler List
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Rob van der Heij
Sent: Monday, June 18, 2012 6:23 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Base registers
On Mon, Jun 18, 2012 at 10:36 AM, Thomas Berg
-Original Message-
From: IBM Mainframe Assembler List
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Frank Swarbrick
Sent: Wednesday, June 13, 2012 6:29 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: DS 0H
I though of doing that very thing. Do you find it
.
Frank
From: McKown, John john.mck...@healthmarkets.com
To: 'Frank Swarbrick' frank.swarbr...@yahoo.com;
ASSEMBLER-LIST@LISTSERV.UGA.EDU ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Thursday, June 14, 2012 6:00 AM
Subject: RE: DS 0H
-Original Message
to my eye.
Frank
From: McKown, John john.mck...@healthmarkets.com
To: 'Frank Swarbrick' frank.swarbr...@yahoo.com;
ASSEMBLER-LIST@LISTSERV.UGA.EDU
ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Thursday, June 14, 2012 6:00 AM
Subject: RE: DS 0H
-Original Message-
From: IBM Mainframe Assembler List
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Tom Marchant
Sent: Wednesday, June 13, 2012 7:54 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: CEETERM and register 15
next
I really wish people wouldn't call it
] On Behalf Of Edward Jaffe
Sent: Tuesday, June 12, 2012 5:23 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: DS 0H
On 6/5/2012 4:51 AM, McKown, John wrote:
My rule for most instructions is place any required label on a
separate DS 0H as the preceding statement.
I use DC 0H rather than
If I want structured assembler, I'll use Metal C. Or would if I had a license.
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151 Boulevard 26 * N. Richland Hills * TX 76010
(817) 255-3225 phone *
john.mck...@healthmarkets.com * www.HealthMarkets.com
The reason for the L in CEETERM is because you can do CEETERM
RC=VARNAME,MODIFIER=MODNAME where VARNAME and MODNAME are fullword areas.
In general, in z/OS, you should __never__ use R0 (impossible actually), R1,
R14, or R15 for a CSECT/RSECT base register. Many (most) IBM macros use these
probably get away (for now) with leaving it using R15, since
those fields will be based on R13.
I will try this out. Thanks for your help
Frank
From: McKown, John john.mck...@healthmarkets.com
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Sent: Tuesday, June
If it fails, you get an ABEND. Period. You either get the storage you requested
or it ABENDs.
The only overflow that I am aware of is of SQA into CSA. And, IIRC, even if
that happens, the subpool number is still the one for SQA (and ESQA similarly).
--
John McKown
Systems Engineer IV
IT
-Original Message-
From: IBM Mainframe Assembler List
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Kirk Wolf
Sent: Thursday, June 07, 2012 10:03 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Java mainframe emulator?
snip
Another cool project would be to build a
GETMAIN RU is Register Unconditional which means that if it fails, it should
get an ABEND of some sort. Also, I don't see where the ALLOWUSERKEY(CSA) is
relevant because the doc says that the default key is 0 if the KEY= operand is
not specified.
Watch for wrap!
I simply don't know. The only difference I see in the book between 229 and 230
is that 229 is fetch protected and 230 is not.
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151 Boulevard 26 * N. Richland Hills * TX 76010
(817) 255-3225 phone *
Would a different method satisfy you? Perhaps: http://z390.org/
It is a Java environment which includes an HLASM compatible assembler, a COBOL
compiler, and the ability to run the programs inside an MVS-like emulator. It
currently runs on Windows and Linux.
--
John McKown
Systems Engineer IV
IT
-Original Message-
From: IBM Mainframe Assembler List
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of glen
herrmannsfeldt
Sent: Monday, June 04, 2012 4:24 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: DS 0H
snip
Oh, yes, in the general case I agree. It just seemed unneeded
-Original Message-
From: IBM Mainframe Assembler List
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of John Ehrman
Sent: Monday, June 04, 2012 4:31 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Opinions? Syntax enhancement to numeric literals.
John McKown suggested:
It
] On Behalf Of McKown, John
Sent: Tuesday, June 05, 2012 7:08 AM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Base registers
-Original Message-
From: IBM Mainframe Assembler List
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Robert
A. Rosenberg
Sent: Monday, June 04
Ah! I have never use the RELATED= and so I didn't think of that reason. In that
case, I (still being weird) would consider that label to not be one for use in
a branch, but more as documentation. So I'd still have the branch label in a
preceding DS 0H statement.
--
John McKown
Systems Engineer
I does. We still use it. If we didn't, the programmers and Production Control
would likely kill us. But they are more interested in the step return codes
than the other data.
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151 Boulevard 26 * N. Richland
Another weird thought from me. In order to more easily convert to baseless
coding, IBM created the IEABRCX instruction to convert all the
base+displacement branch instructions to the corresponding relative
instruction. As best as I can tell, the majority of the IBM macros still use
the short
Damn, you had to include the word good. If you want some baseless code which
is LE enabled and is designed to run as a z/OS UNIX command, you can download
my UNIX alpha code from the CBT. It is FILE864 at
http://www.cbttape.org/updates.htm
I also attached a non-LE baseless HLASM program source
I think it may have been an parody of a joke:
Question: How much money is enough?
Answer: Just a little bit more.
In assembler, it is how many bytes do you need to be resolvable to a valid
offset? just a few more.
It's why I (as a customer only), love doing baseless programming. I separate
the
No such thing as a negative displacement. A displacement is more like an
unsigned immediate operand. From 0..4095 (0x000 to 0xFFF for a 12 bit
displacement) or 0..1048575 (0x0 to 0xF for a 20 bit long displacement).
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
(a division of Mazda Computer Corporation)
Tel: (905) 470-7113, Fax: (905) 470-6507
On 2012-06-04 15:20, McKown, John wrote:
No such thing as a negative displacement. A displacement is
more like an unsigned immediate operand. From 0..4095 (0x000
to 0xFFF for a 12 bit displacement) or 0..1048575
snip
But, why the DS 0H instead of putting the label on the LM?
-- glen
I do the same thing for labels to code. Why? Hum, I guess from reading the
HASP code long ago. Also, it makes it easier to insert a new instruction at
that logical point in the program without remembering to remove the
I don't see where this is possible in HLASM. But some languages all a _
character in numeric literals, and simply ignoring it. Often used in decimal
literals to separate thousands, and in binary literals to separate into nybbles
(4 bits). It is much easier to recognize 16_777_216 than 16777216.
Have you considered the LMD service routines in ISPF? Of course, this means
running your program under the TSO TMP. But it is possible even in batch.
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151 Boulevard 26 * N. Richland Hills * TX 76010
(817)
You are probably thinking of this:
quote
The execution of the instruction is interruptible. When an interruption occurs,
other than one that follows termination, the lengths in general registers R1 +
1 and R2 + 1 are decremented by the number of bytes moved, and the addresses in
general
: IBM Mainframe Assembler List
[mailto:ASSEMBLER-LIST@LISTSERV.UGA.EDU] On Behalf Of Mike Shaw
Sent: Tuesday, May 22, 2012 3:57 PM
To: ASSEMBLER-LIST@LISTSERV.UGA.EDU
Subject: Re: Messages - Was MVC with 2nd operand length
On Tue, May 22, 2012 at 2:29 PM, McKown, John
john.mck
I don't really know if this is the place to start a discussion on some things
that I, personally, might like to see in HLASM. HLASM is very good. And, until
I started doing some z/OS UNIX programming using z/OS UNIX files, I didn't have
any problems with it. Now that I'm doing wacky things such
From:
http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/ASMI1020/PREFACE.7
quote
Your feedback is important to us in helping us to provide accurate,
high-quality information. If you have comments about this document or any other
High Level Assembler documentation, contact us in one of
I've tried finding about this using the -08 version of the Principles of
Operation. I got a few hits, but nothing which described what it actually
__does__. I can guess from the phrase, but I'd like something documented.
John McKown
Systems Engineer IV
IT
Administrative Services Group
I was writing on my tablet at home when I posted that. The strangeness is
that although it looks like a GLBA, and the value is incremented if used by a
nested macro, the value within a given invocation of a macro is unchanging,
unless specifically set by code in the macro.
--
John McKown
for variable
It doesn't look like a global.
On Mon, 16 Apr 2012 07:17:46 -0500 McKown, John
john.mck...@healthmarkets.com wrote:
:I was writing on my tablet at home when I posted that. The
strangeness is that although it looks like a GLBA, and the
value is incremented if used by a nested macro
I am fairly sure IBM won't do this. But I could use an enhancement to the CALL
macro. I use the following in a lot of my code, to see if I'm in a UNIX
environment.
_L OPSYN L
...
LAR1,CALLX
LOPSYN LRL
CALL CEE3INF,(SYS,ENV,MEMBER,GPID,FC),VL,MF=(E,(1))
L
Thanks! I'm just getting to the point of using the SYSSTATE macro in my code.
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151 Boulevard 26 * N. Richland Hills * TX 76010
(817) 255-3225 phone *
john.mck...@healthmarkets.com *
I had forgotten about using (15) instead of the actual name. I also wanted to
avoid the LRL because it doesn't work pre-z10 (I think LRL came in on the z10).
But using the SYSSTATE ARCHLVL=2 works great. I'm now upgrading all my source
to include this. And, since I'm keeping my source in UNIX
This was due to my looking at the expansion of the CALL macro after using
SYSSTATE ARCHLVL=2. The part of the expansion I was looking at was:
BRAS 15,*+8
DC V(epname)
L 15,0(15,0)
And I immediately wondered by it was L 15,0(15,0) instead of how I am used to
it: L 15,0(,15). Then it hit me.
of the corresponding AR register ?
On 4/10/2012 11:31 AM, McKown, John wrote:
But that made me wonder why the z/Architecture does not
specify that the contents of the AR register associated with
the link register in any of the branch and link type
instructions: BALR, BASR, BRAS, BRASL, and BASSM
Nope. I'm not much into COBOL. I guess the current version is quite a bit
better than the stuff I learned long ago. But I still shudder when I look at
the assembler emitted. And I haven't found any compile parameters to improve
it. A few years ago, we had the C compiler. I was fairly well
Not the same at all on z/OS UNIX.
--
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151 Boulevard 26 * N. Richland Hills * TX 76010
(817) 255-3225 phone *
john.mck...@healthmarkets.com * www.HealthMarkets.com
Confidentiality Notice: This e-mail message may
I will say his heart was in the right place. We won't discuss the position of
his head. grin (Just kidding, Bob).
John McKown
Systems Engineer IV
IT
Administrative Services Group
HealthMarkets(r)
9151 Boulevard 26 * N. Richland Hills * TX 76010
(817) 255-3225 phone *
Young as possible is nothing really new. I remember the jokes when I was just
out of college, MVS was recently announced. It was joked that companies were
looking for 20 year olds with an MBA and 15 years of MVS internals experience
for entry level positions. As always, management wants the
Most strange. Try this:
MODCB ACB=acb,DDNAME=(*,0(R3))
The macro is using I don't know what it's called, as documented here:
http://publibz.boulder.ibm.com/cgi-bin/bookmgr_OS390/BOOKS/DGT2D570/1.2.1
quote
An expression of the form (*,scon), where scon is an expression valid for an
S-type
Hello from a member of the CABAL. I can think of one possibility of a use for a
Data Space instead of using above the line storage. As a type of protection.
With a program in AMODE(64), an errant pointer __might__ corrupt something. As
in, you mean to update one area above the line, but
OK, I'm considering donating some code to the CBTtape so that others can use
it, if they want. The code, such as it is, is all for UNIX commands.
I use FLOWASM because it makes it easier for me to use vi to edit HLASM code if
I don't need to conform to the normal HLASM syntax requirements.
I
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