- config-pin [pin] [state] will mux the pins to the PWM Subsystems
- Modifying am33xx.dtsi under the dtb-rebuilder project such that:
epwmss0, epwmss1, and epwmss2 status = okay, and their children, ehrpwm0,
ehrpwm1, and erhpwm2 status = okay, will enable the system clocks for
Hi all,
Am new to beaglebone black and also to linux. I am using a 3.8.13-bone71
kernel which I update it using /opt/scripts/tools/./update_kernel.sh .
Is it the latest release? If not how can I update it to the latest release?
Am using debian.
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Hi BB team,
I have a project that requires two screens, 1 LCD touch display and 1 LCD
HMDI display (front and back respectively), I'm interested in duplicating
screens and/or different screens functionalities.
Is it possible to use the BB-xM for this project? If yes, I would
Hello,
I'm trying to enable SPI0 on the BBB, i have an LCD7 cape and pin 85
which is P9_21 was in conflict with it so i changed the dts file in the
kernel build folder and i rebuilt the kernel :
i modified capemgr in the /etc/defaults folder to boot the system with the
pins activated but i
Hi BB team,
I have a project that requires two screens, 1 LCD touch display and 1 LCD
HMDI display (front and back screens respectively), both 7, I'm
interested in duplicating and/or different screens functionalities.
Is it possible to use the BB-xM for this project? If yes, I would
Hello, I acutally do not know a answere to your question, but I would like
to know how you got QNX running on the BBB. I followed the instructions in
the documentation and copied the MLO, uboot and bin file on a empty sd card
with fat32 but the board is not booting. Which instructions did you
On Thu, Apr 16, 2015 at 4:48 AM, krishnan...@gmail.com wrote:
Hi all,
Am new to beaglebone black and also to linux. I am using a 3.8.13-bone71
kernel which I update it using /opt/scripts/tools/./update_kernel.sh .
Is it the latest release? If not how can I update it to the latest release?
I can't get it to work either. If you get any movement on this issue, I'd
like to know.
On Wednesday, November 26, 2014 at 8:02:25 AM UTC-5, AdamMagaluk wrote:
Has anyone been able to get internet sharing working with the Beaglebone
Black with the latest OS X from Apple?
In my testing
I suspect that your LCD design is interfering with the boot pins that are
co-located with the LCD pins which is changing the boot order.
I suggest that you read the System Reference Manual for more information.
Gerald
On Thu, Apr 16, 2015 at 11:49 AM, lix...@gmail.com wrote:
Hello, Everyone.
Hello, Everyone.
I am in the very early stages of interfacing the BBB with a new 4.3 TFT
LCD, not a cape. It has a 16-bit data bus setup for 6800 style interface
with the onboard controller (SSD1963). This winds up requiring 22 GPIO
pins. I have been an engineer in the LCD industry for 6
It will be tough. Both screes must have same resolution and timing. There
is only one LCD interface. May be tough to do with an HDMI display and an
LCD display.
Gerald
On Thu, Apr 16, 2015 at 10:16 AM, fdo.preci...@gmail.com wrote:
Hi BB team,
I have a project that requires two screens,
Hi, what is the current status on OpenGL on the BBB? Is there a driver now
that works with the current kernel used in the BBB? Instructions somewhere?
Thanks!
On Wednesday, October 30, 2013 at 3:59:21 AM UTC-5, Alexander Rössler wrote:
Hi guys,
TI finally responded to my request. Still cant
On 17/04/15 11:51, liyaoshi wrote:
Hello all
Do you know , how to enable L2 cache in Beagle-x15 board ?
Screw enabling L2 cache, how to get hold of a Beagle-x15 board? ;)
P.
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So i downloaded the newest image put it on an SD card and it works great.
now i set up a static ip address in /etc/network/interfaces
# This file describes the network interfaces available on your system
# and how to activate them. For more information, see interfaces(5).
# The loopback network
Hello all
Do you know , how to enable L2 cache in Beagle-x15 board ?
Searching from google , and linux kernel source .
I dont find any function about the scu config for enable in kernel .
For Cortex-A9 , there will be almost PL310 cache controler , but on Cortex
A15 ,intergrated SCU replace
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