RE: [casper] state of the art single bit correlators

Yes, thank you, Dan, I realise much more than just the right number of I/O pins, Cheers, Neil From: casper@lists.berkeley.edu On Behalf Of Dan Werthimer Sent: 14 November 2023 22:01 To: casper@lists.berkeley.edu Subject: Re: [casper] state of the art single bit correlators hi neil,

Re: [casper] state of the art single bit correlators

hi neil, thanks for this research on FPGA LVDS pair resources. as you know, just because an FPGA has 1152 pairs at 1.4 Gb/sec, doesn't mean you can input and correlate1152 antennas at 700 MHz bandwidth (real sampling), or 576 antennas at 1.4 GHz bandwidth (complex sampling), as the FPGA fabric

RE: [casper] state of the art single bit correlators

Hi Dan, Quite right! Xilinx(AMD) do the VIRTEXTM-7 XC7V2000T with a maximum of 576 differential I/O pairs, the XC7VX1140T with a maximum of 528 Differential I/O pairs, and the VIRTEXTM ULTRASCALE XCVU440 with a maximum of 648 differential HP I/O pairs. Altera (Intel) do the Stratix 10

Re: [casper] Help with setting up RFSoC

Hey Mitch. Thank you for the reply. The Python version that my system is returning is 3.7.13. Should I rather use Python 3.8? I have noticed that matlab2021a does not support python3.9. Thank you - Heystek Grobler 0832721009

Re: [casper] Help with setting up RFSoC

Hi Haystek, This most likely is a python version conflict. When you activate your Python environment, what is the version of Python that `python -V` returns? For me, my casper dev env returns Python 3.8.2. The second tutorial incorporates the RFDC yellow block. When the back end tool