Re: [casper] pfb_coeff_gen_calc shifted sinc arguments

Hi Nathan This bug (if we are talking about the same one) was fixed in a commit 2 years ago but has not made it into the main repo yet. It was pointed out to me by Jack Hickish. For more info see https://github.com/ska-sa/mlib_devel/commit/702d962842b53f76ec661b27b1156679ccb71929 The fixed

Re: [casper] Anyone have an asynchronous VACC?

Hey Morag SARAO has one (used in MeerKAT X-engines) that might be useful. Cheers Andrew On Tue, 20 Jun 2023, 14:37 Morag Brown, wrote: > Hey all,As the subject says. We might need an async vacc for a project, so > checking if anyone here already has one working with the toolflow in the >

Re: [casper] Installing the toolchain (segfault!)

inx licenses. Regards Andrew On Sun, Feb 19, 2023 at 12:38 PM Andrew Martens wrote: > Hi Kaj > > There is a (possibly not bleeding edge) version of the tools for use > online via the Pacific Research Platform. There is a Slack channel where > you can get more information at > >

Re: [casper] Installing the toolchain (segfault!)

/enQtNDgxOTU1ODc0MjY0Ni03NDllNjI5OWUwOWU0MzFjMTQ3MTJjNGRjYWZjY2ZmMDYwMmY4OWQwN2IzOWEyZWEzNzk4ZTkyODFjZjFhNTJi I will see if I can figure out a good way of sharing the virtual machine I have in the next few days as there are a couple of people who've shown interest. Regards Andrew On Sun, 19 Feb 2023, 12:11 Kaj Wiik, wrote: > Hi Andrew, > > On 17/02/2023 21:08, Andre

Re: [casper] Installing the toolchain

For those interested - I have a virtual machine with the latest (MATLAB 2021a) tools where I have solved a lot of these issues. One just needs to add licenses for MATLAB and Xilinx. VirtualBox, and it's big (>100GB). Hit me up with a shared folder if you'd like to give it a spin. I would also

Re: [casper] fft_biplex_real_2x Block

Hi Wang It may be that the version of the toolflow used to create that model, is not the same as what is on your machine. You may want to drag a new block in from your library, and then set the parameters to the same as the block in the model. There is also a script that will update the blocks

Re: [casper] fft_biplex_real_2x Block

Hi Wang It looks like there is something going wrong during the creation of the internal logic in the FFT. Could you give us the following information 1. Which git repo and branch of mlib_devel are you using? 2. What parameters did you change on the FFT? 3. What are the first error messages you

Re: [casper] ROACH2 to implement F-engine

Hi Wang Some would say that it might be easier to buy a newer hardware platform, as this would be supported by the latest tools, software versions etc. You should maybe try build something simple on the ROACH2 I assume you have, and decide for yourself. You should check out which versions of

Re: [casper] Help with packing data

a similar kind of block? Or > should I rethink the sine wave that I generated that makes use of 602 000 > 000 data points? > > Thanks for the help! > > Heystek > > On 26 Nov 2021, at 15:46, Andrew Martens wrote: > > Hi Heystek > > Simulink has a maximum BRAM size of

Re: [casper] Help with packing data

Hi Heystek Simulink has a maximum BRAM size of 64k (16 bits address size). A 32 bit address size would equate to 4G addresses, which is far larger than the amount of BRAM available in the FPGA. Regards Andrew On Fri, Nov 26, 2021 at 3:40 PM Heystek Grobler wrote: > Hey everyone. > > I have

Re: [casper] Tips to speed up simulation

Hi Sebastian To add to what Dave has suggested. As you mention, significant time is taken to do the 'Update' before the actual simulation is run. To prevent having to do this every time a simulation runs, keep the design open rather than closing and re-opening. Parameter changes often do not

Re: [casper] Help with timing constraint

t; > > On Wed, Aug 26, 2020 at 10:59 AM Andrew Martens wrote: > >> Hi Heystek >> >> Output reports and their location change over versions, between ISE and >> Vivado etc. I think the output reports for ISE are located in the >> 'implementation' folder. I think

Re: [casper] Help with timing constraint

Hi Heystek Output reports and their location change over versions, between ISE and Vivado etc. I think the output reports for ISE are located in the 'implementation' folder. I think the timing related ones have 'timing' in the name... A quick Google search of the error will help. Note that there

Re: [casper] A bug in the Xilinx FFT frame sync

Thanks for the heads up, that could cause a lot of confusion. You could try the CASPER FFT, at least you can fix any bugs without having to update your Xilinx install :) We have, over the years, come across a few similar bugs. The most painful was a compiler bug which generated incorrect logic

Re: [casper] Compiling design

Hi Heystek I notice that you are using Xilinx Output Gateways leading to scopes, I would guess that there are Input Gateway/s as well. These will be linked to physical pins, or software interfaces, on the FPGA when compiled. If you want to access inputs linked to FPGA pins or software interfaces,

Re: [casper] Use of xBlock for block scripting

To add to what Dave has said. I found that having no control over the relative size and placement of the blocks when using xBlocks made it hard to see what was happening, making the design write-only and hard to debug. Generating scipts can be tedious though. The mdl2m.m script in the

Re: [casper] FIR and decimating CIC filter

Hi I implemented a similar library of vector processing primitives (the Bus subsection in the library) a few years ago when we upgraded the PFB. Unfortunately, Simulink has upper limits on the width of buses, and drawing area. We have not been able to implement large-number-of-tap pfb_firs

Re: [casper] Data-Width Conversion in FIFO

r inputs. > > Indrajit Barve > indra...@iiap.res.in > 080-22541492 > On Apr 25 2019, at 6:12 pm, Andrew Martens wrote: > > Hi Indrajit > > This should do something like what you want to do I think. > > Cheers > Andrew > > > On Thu, Apr 25, 2019 at 6:53 AM Indraji

Re: [casper] Data-Width Conversion in FIFO

Alas, there seems to be no such System Generator FIFO block with different input output widths. The FIFO block I provide has been used for a few years now in our beamformers, but assumes a careful user. On Fri, Apr 26, 2019 at 8:15 PM David MacMahon wrote: > I thought that system generator

Re: [casper] Data-Width Conversion in FIFO

Hi Indrajit This should do something like what you want to do I think. Cheers Andrew On Thu, Apr 25, 2019 at 6:53 AM Indrajit Barve wrote: > Hello all, > > I would like to implement a FIFO with input port data type depth and > width of 2048 X 32 and output port data type 1024 X 64.

Re: [casper] Snapshot block and trigger

Hi Franco The snapshot block has internal registers for arming, triggering etc. The trig line from the external register is not doing anything in your example code above because you are manually triggering when calling the snapshot_get function. If you are interested, look inside the snapshot

Re: [casper] ROACH2 4-element correlator compilation error

Hi Bela Please open you design in Matlab/Simulink and then Press 'Ctrl-D' (hold the Ctrl key down and hit the D key at the same time). This will do an 'Update' on your design and will give more useful error messages. Regards Andrew On Thu, Jan 18, 2018 at 7:28 AM, Bela Dixit

Re: [casper] Berkeley CASPER group

Hey Jack This next year is supposed to be a ramp down for us as we get MeerKAT finished and online. I am keen to look for new interesting tasks to get involved in. In particular, I am interested in -- Designing test benches / verification frameworks for libraries I have the beginnings of a

[casper] Re: FFT Nyquist Freq

Hey Jonathon I am copying my reply to the list to expose my own potential ignorance. The CASPER FFT implements a DFT where each resultant bin is the same as mixing with a complex exponential and then low pass filtering the result (as per the DFT definition). The complex exponentials have

Re: [casper] Minimum Clock Frequency (ROACH2)

Hey Franco Many of the CASPER blocks were updated a while ago so that you can use them asynchronously i.e data does not need to be fed to the blocks on every clock cycle. You can then run your FPGA at a higher clock rate than the input data rate. Regards Andrew On Tue, Apr 4, 2017 at 4:22 AM,

Re: [casper] Issue with snapshot block

Hey Michael I am not sure that I understand your use case correctly. It seems that you want to generate snap shots of the spectrum being generated? The way we generally use the circular capture snapshot mode is to start capturing data, and then to trigger a stop signal on some event. The

Re: [casper] Weird FFT Output

Hi Amit We have also identified a bug in the pfb_fir_generic block and are working on debugging it. Will let you know when we have a solution. Sorry for the inconvenience. Regards Andrew On Thu, Jan 21, 2016 at 11:18 AM, Amit Bansod wrote: > Hi Jack, > > I finally

Re: [casper] casper Digest, Vol 98, Issue 13

.@lists.berkeley.edu >> >> When replying, please edit your Subject line so it is more specific >> than "Re: Contents of casper digest..." >> >> >> Today's Topics: >> >>1. Re: Weird FFT Output (Amit Bansod) >>2. Re: Weird FFT

Re: [casper] fft_biplex_real_2x

Hi Rolando You may want to look at the Xilinx FFT for your use case. The CASPER FFT is optimised so that minimal resources are used when processing high bandwidths (either many inputs, or inputs captured at high sample rates). In this case you may find that the Xilinx FFT actually uses fewer

Re: [casper] On FFTs

Hi Mugundhan I am including the CASPER list in my reply as there are others who may be able to give advice. Most of our blocks are targeted at high bandwidth applications where the sampling rate is high and the data must be parallelised to allow it to be processed. The closest thing we have to a

Re: [casper] casper Digest, Vol 95, Issue 2- ROACH2 FFT

t; > ---------- > *From:* Madden, Timothy J. > *Sent:* Wednesday, December 09, 2015 8:02 AM > *To:* Andrew Martens > *Cc:* casper@lists.berkeley.edu > *Subject:* RE: [casper] casper Digest, Vol 95, Issue 2- ROACH2 FFT > > Thanks for the response Andrew... >

Re: [casper] casper Digest, Vol 95, Issue 3: FFT problems

casper-ow...@lists.berkeley.edu > > When replying, please edit your Subject line so it is more specific than > "Re: Contents of casper digest..." > > > Today's Topics: > >1. Re: FFT problems (Andrew Martens) > > >

Re: [casper] About Shared BRAM

Hi Aniket I am sending a copy of this reply to the CASPER mailing list as others may be able to help or benefit from the help. Firstly, if you have not already done so, I would recommend doing the CASPER tutorials available at (https://github.com/casper-astro/tutorials_devel). In particular,

Re: [casper] New CASPER toolflow features for planAhead

Hi Dave, All These (useful) changes have been pushed to the repo at ska-sa as well. Regards Andrew On Fri, Apr 24, 2015 at 12:26 AM, David MacMahon dav...@astro.berkeley.edu wrote: I pushed a few changes to the casper-astro mlib_devel repository to make life easier when working with Pblocks

Re: [casper] Roach2 QDR

I played around with ROACH2 QDR calibration a few months ago and the following must be noted; The physical trace length between FPGA and QDR SRAM is a fixed length. This fixed length equates to a different number of clock cycles, depending on clock speed. The interfacing firmware assumes a fixed

Re: [casper] about complex FFT core problem

Hi Wang This error occurs when you have a data bus and are trying to use part of it that does not exist. This means that a Slice block is expecting a wider data bus than your design is giving it. For the FFT it may be that the shift input does not have the correct width, or possibly your data

Re: [casper] Green blocks with Enables

Hey John The pfb_fir_generic and fft family are asynchronous capable in recent casper library versions. There is a mask option and an en input and dvalid output ports are added. One thing to watch out for is that the sync must occur on the last valid cycle of an input data window. Let me know

Re: [casper] about error report of tut3

Hi The FFT blocks in the library are empty but can still be used. Put one in a design and change the number of channels from 0 to the number you want for your design. They are stored empty in the library to make sure that there are no 'old' blocks stored in the library. Regards Andrew On

Re: [casper] fft_biplex_real_2X block

Hi Rolando Now, I need to understand the equalizer block. After the FFT the size of each data sample has grown. Many astronomical signals have a frequency spectrum that is related to white noise. This means that each frequency channel sample is about the same size. So we don't need lots of

Re: [casper] Snap Block Assertion Error

revision of the ska-sa github repository I'm using. - git log -1 commit 2d523da21e87393f8d025e570a97e3b42af9358a Merge: b89854a a0f051b Author: Andrew Martens and...@ska.ac.za mailto:and...@ska.ac.za Date: Fri Jan 24 18:29:56 2014 +0200 Merge branch 'master

Re: [casper] How do you cause the one_GbE to send a packet on a ROACH-2

Hi Joe, all I ran into some issues on a roach 1 where the 10 gbe buffer would fill up and overflow before i had run tap_start (if I recall correctly). In that case, no data would ever be transmitted, and I had to add a software register to the overflow port to see this was the case. Executing

Re: [casper] Finally Compiled Correlator!!! //QUADC+IBOB

Hi Rolando Congratulations How I can confirm that the correlator function properly? A good way to test a correlator is to do the following; 1. Get a wideband noise source and add a low pass filter so that the signal will fit into the bandwidth of your system. 2. Split this signal and feed

Re: [casper] Correlator IBOB // Rolando Paz

Hi Rolando I am sending my reply to the mailing list as my reply is not very useful and someone else may know more than me, especially as I have not looked at iBOB related models in a long time. When performing a simulation, no errors, but when checking the command line I found this error

Re: [casper] Large (N 13) biplex FFT does not compile / blackbox

Hi Danny I think I have managed to fix this bu would appreciate confirmation. It seems that large distributed RAM buffers can cause exceptions under certain conditions. In this case the lookup buffers in the reorder blocks in the unscrambler block, if implemented in distributed RAM and

Re: [casper] Large (N 13) biplex FFT does not compile / blackbox

Hi Danny Did a test compile and also got an exception. Think I have found a possible cause. Will let you know when a fix is implemented. Cheers Andrew On 29/01/2014 13:16, Price, Daniel wrote: Hi all I am trying to black-box a 2^13 fft_biplex, but it is failing with a non-specific error

Re: [casper] Invalid simulink object name error

- This makes me believe that the reorder_init.m script has an issue. Should I clone an earlier git revision before the recent changes to the reorder block? Thanks, On Mon, Jan 20, 2014 at 12:20 AM, Andrew Martens and...@ska.ac.za mailto:and...@ska.ac.za wrote: Hi Richard Which

Re: [casper] how long can filter banks be?

Hi Gerry Dan's idea of ganging together filter banks works well provided you can make do with an FFT for the second filter bank i.e you don't need any of the benefits of a PFB. We currently are working on a design that includes 2 2^16 filter banks (10 bits ADC input data, 8 tap PFB FIR, 18

Re: [casper] how long can filter banks be?

channels. Regards Andrew Thanks Andrew. I suppose you suggest 2^16 useable channels from a 2^17 FFT b/c of aliasing? Yes, we must give it a try to really know. Gerry On 1/20/2014 9:55 PM, Andrew Martens wrote: Hi Gerry Dan's idea of ganging together filter banks works well provided you can make

Re: [casper] Invalid simulink object name error

Hi Danny I have setup a fresh install of Xilinx 14.6, Matlab r2012b on ubuntu 12.04, ska-sa library, and am getting errors when generating blocks. For example: --Error in 'untitled/pfb_fir_generic': Initialization commands cannot be evaluated. --Invalid Simulink object name:

Re: [casper] Invalid simulink object name error

Hi Richard Which casper repo are you using? There have been some recent changes to the reorder block in the ska-sa repo, which require swapping out all reorder blocks in your design for new ones (or swapping the block containing them of course). Cheers Andrew I just found this same

Re: [casper] Hi // IBOB spectrometer- 2048 channels

Hi Rolando The error you got means that the place and route program used to convert your design into logic in the FPGA has not been able to design things so that your design will operate at the clock rate you wanted. This often happens as the design gets larger and logic resources become

Re: [casper] Fwd: Problems with Speed Optimization toolflow

Hi Andres Another way to save logic is to hard-code the shifting schedule for the FFT. (Go to the Implementation tab and choose 'Hardcode shift schedule). This removes quite a lot of logic. You must then decide what shift schedule to use to prevent overflows, starting with a '1' for every fft

Re: [casper] Problems with Speed Optimization toolflow

Hi Andres It is unclear to me what your goals are. Could you give a basic description of your design (sampling rate, number of channels, target board (ROACH or ROACH2) etc) and what speed you are targeting? Someone out there has probably built something close to what you are trying to do and

Re: [casper] Problems with Speed Optimization toolflow

Hi again It is unclear to me what your goals are. Could you give a basic description of your design (sampling rate, number of channels, target board (ROACH or ROACH2) etc) and what speed you are targeting? Someone out there has probably built something close to what you are trying to do

Re: [casper] Simulink Input output problem.

Hi Nishanth Hi All, I have a basic doubt after I installed simulink and Xilinx according to the Casper website I find that In the casper DSP blocks has NO INPUTS and OUTPUTS connected to it (green blocks- the downconverters mixers) .The blocks in yellow are all fine and has inputs and

Re: [casper] ROACH2 XAUI

Hi Jack Do you need 10Ge links or XAUI? The 10Ge yellow blocks work fine on ROACH2. One of the outstanding yellow blocks for ROACH2 is the XAUI block. The 10Ge yellow blocks use a quad core XAUI core underneath which takes care of bonding the individual streams together so it will not quite

Re: [casper] ROACH2 XAUI

Hi jack My mistake. You should be able to use the quad core XAUI core underneath the existing 10Ge block. Cheers Hi Jack Do you need 10Ge links or XAUI? The 10Ge yellow blocks work fine on ROACH2. One of the outstanding yellow blocks for ROACH2 is the XAUI block. The 10Ge yellow blocks

Re: [casper] ROACH 2 clocking questions

Hi Joe 2) Can multiple clock rates be set/used in the ROACH2 board? For example, can we use the ADC clock for ADC captures and a (much) faster clock for the data processing portion of the algorithm? Multiple clock rates do normally run on a ROACH/ROACH2, but only in yellow blocks. As an

Re: [casper] ROACH2 clock and ADC16x250-8 question

Hi Joe When you try with adc0_clk at 150MHz does LED 7 light up? This LED should be independent of the clock source. If it is not lit it indicates that the FPGA may not have been configured or has not come up properly. You may want to try writing to and then reading from the register

Re: [casper] DRAM write speed

Hi Alex You should be able to do this with the existing snapshot block. Make sure that the 'DRAM clock rate parameter' is higher than the FPGA clock rate. In your case a DRAM clock rate of 250 should be more than sufficient I think. We have used a snapshot block pretty much as you describe

Re: [casper] Matlab components for toolflow

that does what you need. Thanks, Dave On Sep 25, 2013, at 7:36 AM, Andrew Martens wrote: Hi Thanks Andrew! Would you know approximately how much time it would take for you to look into this? Meanwhile, would you know the latest commit that does not use fi, and hence, does not need Floating

Re: [casper] Matlab components for toolflow

development team over the weekend, but we are stuck right now due to this issue. If you do manage to find a work-around and can provide a block update, please let us know. Many Thanks, Dale On Thu, Sep 26, 2013 at 5:43 AM, Andrew Martens and...@ska.ac.za mailto:and...@ska.ac.za wrote: Hi Dave

Re: [casper] Matlab components for toolflow

. Regards Andrew Thanks, Nimish On Wed, Sep 25, 2013 at 1:24 AM, David MacMahon dav...@astro.berkeley.edu mailto:dav...@astro.berkeley.edu wrote: Thanks, Andrew! Dave On Sep 24, 2013, at 10:13 PM, Andrew Martens wrote: Hi I do use the fi constructor to generate

Re: [casper] Matlab components for toolflow

) will probably need a Fixed Point Toolbox license. I suspect it wouldn't be too difficult to rewrite these files in a way that maintain the functionality, but avoids the fi (and any related) call(s). It looks like Andrew Martens introduced at least some of the fi dependencies, so maybe he would be willing

Re: [casper] Subject related to: Report of experience with KatADC

Hi https://github.com/casper-astro/mlib_devel contains the official stable CASPER libraries. There are other repos that contain more bleeding-edge versions of the libraries but I would advise using the standard libraries if possible. Regards Andrew Hello, It is my understanding that the

Re: [casper] Trouble with Casper DSP sincos block

other designs e.g the tutorials? Is the compile problem specific to the sincos block? Regards Andrew On 09/19/2013 11:41 AM, Paul Marganian wrote: Thanks Andrew, I'll look into those other blocks. The problem happens at compile time. Paul On 09/19/2013 09:45 AM, Andrew Martens wrote: Hi Paul

Re: [casper] questions on DRAM

Hi Tim I have a ROACH board and am using a design I got from another ROACH person. The design uses a lookup table stored in a dram. The software interface is used to load the dram with the data. later, the dram is read out to stream data to MKID DAC board. Questions: I have my FPGA running at

Re: [casper] Question on fft_wideband_real

Hi Tim I think the number of simultaneous streams refers to how many signals you want to process in parallel in the FFT. I think it makes multiple parallel FFTs that share twiddle factors. I could have maybe used 'simultaneous polarisations' to be more astronomy specific. Also, the way the

Re: [casper] Problem setting parameters in fft blocks using mlib_devel

Hi Tim Was the following issue (see below) ever solved? I have exactly the same problem with latest libraries at https://github.com/ska-sa Matlab R2012b System Generator is 14.2.4415 Linux- Redhat See below from Ken Treptow from Fermilab: Tim Madden I get the following simulink error if I

Re: [casper] Fwd: error in the slice

Hi Katty Hi All, I tested the scalability in the number of channels of existing digital spectrometers but when the size of pfb and FFT are 2 ^15 pntos and the other blocks as acc-cntrl and vacc. I have any error: In the console of matlab: Error using gen_xps_files (line 196) The

Re: [casper] Resources not decreases significant

Hi Katty Hi all, When the number of parallel spectrometers increases when one decreases the number of channels, but surprisingly, this increase is not very significant, why resources not decreases significant from 32 to 2048 channels and where do the resources, FFt, PFB? and like to know

Re: [casper] strange problem in the FFT

Hi Dave Thanks for sending your test model. Since it was saved using a newer Simulink version, I had to simulate it using a newer toolflow version. Sorry about that. Doing so did indeed show the FFT problem you described. I then re-simulated my test model in the newer Simulink version

Re: [casper] Idea for speeding up CASPER build times

Hi Ryan So I just finished a ROACH2 build, and everything from copy base package through bitgen took almost 2 hours. It looks like this is because I have 48 shared memories, plus about another 20 snapshots. The tools seem to be synthesizing each of these separately. I would expect

Re: [casper] strange problem in the FFT

Hi Dave The only way that the script could generate logic that would result in correct data would be correct if; 1. The Relational block could get a latency of 1 when no latency was specified i.e default operation has latency of 1 in that toolflow version. You're right! That's exactly the

Re: [casper] Error in Shared BRAM yellow block

Hi Rurik I tried the recent changes to Shared BRAM on ska-sa but I ran into an error during Update Diagram in munge_init.m resulting from commit 2c13dab where it's trying to index div_size which is just a integer. Thanks for the fix :) I attach a patch which fixes this issue; however I'm

Re: [casper] Error in Shared BRAM yellow block

Hey Jason When I try to set the Data Binary Point parameter in the Shared BRAM block I get the error: Illegal parametrization: Binary point Binary point must be less than or equal to the number of bits, X. X appears to be the index of the Data Width rather than the actual value selected by

Re: [casper] strange problem in the FFT

)) on the output. It is easy to see channel swapping as the output function is nice and smooth. We're using the casper library: [ptcs@ptcs /export/home/ptcs/scratch/guppi2/libraries/mlib_devel]$ git log -1 commit 6050c725f770f0bdb776fae107dc4fe26f7fce51 Merge: f50084e 0c15bf7 Author: Andrew Martens

Re: [casper] number of coefficients needed in PFB and FFT

Hi All I have just completed a rather large overhaul of the CASPER FFT family. Rigorous testing has yet to be performed but it works at the moment and has been pushed to the ska-sa repo on github for early adopters/testers. The main aim (and reason this email continues this thread) was to

Re: [casper] number of coefficients needed in PFB and FFT

Hi Dave Do you have any utilization comparisons of old vs new? Not yet, I hope to do a basic one soon though. Savings will depend on use case. Also, you can optimise for resources in a few ways (DSPs vs BRAMs when using fft_direct, logic vs BRAMS in the biplex stages and in reset point

Re: [casper] Address Space Overlap

Hi Ioana, all It turns out I was trying to use more BRAM's than we had payed for (well, my design was nice and simple, except I had put two huge snaps. Once I decreased the size of one, no problem) I didn't expect the error message to take this form though I'm not sure that these

Re: [casper] Fwd:connecting with .py this is register cnt_rst not found

Hi Katty This is running my designs: *first this is for modeinterleave * root@roach:/boffiles# ./s1_2013_May_02_1157.bof [1] 519 root@roach:/boffiles# ps PID TTY TIME CMD 506 ttyS000:00:00 login 507 ttyS000:00:00 bash 519 ttyS000:00:00 s1_2013_May_02_ 520 ttyS0

Re: [casper] Simulation of tutorial3

Hi Ross Solved - too much gain in the quant causing all the problems seen - Need to work out why it had the effect it did but reducing it produces a perfect spectrum. We did see this when preparing for the last workshop. Tutorial 3 is set up for a wideband noise input where the input power is

Re: [casper] Problems with shared_memory blocks on ROACH2?

Hi Ryan Hey all, just an update on this: First, I reverted to an old copy of the libraries -- it didn't work, but had a different problem. It looks like after you have more than a certain number of yellow blocks in use, the tools start using the opb2opb_lite pcore, which can be had from the

Re: [casper] Latency in PFB and FFT

Hi Ross The guys at Berkeley and Ryan would probably have more detailed advice (especially regarding hand-placement) but the following are some general guidelines if trying to optimise timing from within System Generator; 1. Adding latency to an operation in System Generator results in the

Re: [casper] bug in shared bram block?

Hi John Hi all. When trying to use the shared bram block in a recent (march 15ish) version of the casper xps blockset from mlib_devel, we have a problem. The munge_io block inside the yellow block doesn't work. It has a bad parameter list. It ends up with a box in the corner signifying

Re: [casper] Changing Clock Source on MSSGE ROACH Block

Hi Tim Are you using one of the CASPER DAC yellow blocks? You are also using dac1_clk and not dac0_clk - are you using 2 DAC boards? Henno To expand on what Henno has said, if you specify that you will be using a clock source besides those derived from the onboard oscillator (sys_clk,

Re: [casper] Error reading registers with ROACH2

Hi Jason I'm having a hard time updating the .mdl file for tutorial1 after I tried to update to the newest CASPER tools. By 'CASPER tools' are you referring to recent git commits of the Simulink libraries from the ska-sa repo? If so, I know what your problem below is... All the links to

Re: [casper] Disable KATADC 20dB Amplifier

Hi Nimish Andrew, Your response makes it very clear. Perhaps, the description enable gain block in the mask could be changed to something else more intuitive in the future versions. The name makes sense if you trace that parameter from the base verilog but is probably not intuitive for a

Re: [casper] Virtex 6 BRAM timing

Hi Dave It would be good to add an optional Latency parameter to the Shared BRAM block and allow the user to select 1 (current value that does not use the BRAMs optional output register) or 2 (new value that does use the BRAM's optional output register). I think this would help ROACH2

Re: casper-scm Recent mlib_devel pushes to casper-astro

Hi Dave, all The flurry of updates were a mistake (hence the undo). In preparing for the workshop I started seeing what updating casper-astro to ska-sa would look like and did a bunch of cherry-pick commits on my local repo. After the workshop I did a push. Realising that I had broken support for

Re: [casper] Matlab 2012b

Hi Katty See this page for more information https://casper.berkeley.edu/wiki/MSSGE_Toolflow_Setup Cheers Andrew On Sat, 2013-02-02 at 10:33 -0300, katherine viviana cortes urbina wrote: Dear Casperites I decided change to Matlab 2012b but I need to know what products basics need Matlab

Re: [casper] Can't update link of adc083000x2

Hi If we could figure-out a clean way of scripting mask generation, then we could regenerate the entire library on-the-fly, which'd go a long way towards compatibility across versions. This is possible. It requires that the block itself be generated, as well as the mask using scripts. The

Re: [casper] number of coefficients needed in PFB and FFT

Hey I haven't seen the Goertzel algorithm before, but it looks like a great idea for this: we might be able to produce a coefficient DDS in just two DSPs! The Goertzel algorithm predates the FFT even and is used to calculate sparse FFTs. It basically just calculates each bin individually.

Re: [casper] number of coefficients needed in PFB and FFT

Hi Dan we used to use CORDIC for generating coefficients. not sure how cordic comares to goertzel. there are a few open source VHDL cordics. Goertzel uses the coefficient factor of the previous calculation stage to calculate the coefficient factor currently required i.e rotate the previous

Re: [casper] Can't update link of adc083000x2

Hi I did not commit this change because it's not backwards compatible. I have noticed more and more instances of backward compatibility issues lately as I am using older versions of the tools. At some point soon we are going to be forced to make everyone upgrade to the latest tools if they are

Re: [casper] Problem setting parameters in fft blocks using mlib_devel

Hi Ken There were some fixes that had not yet been pushed to the main casper git repository (mostly to do with stale blocks). I have pulled them in (commits 9940104 and 778d19f). Please check out the latest library and see if that helps you. Regards Andrew

Re: [casper] Problem setting parameters in fft blocks using mlib_devel

post back if you're still having trouble. Regards Paul On 18 January 2013 17:02, Andrew Martens and...@ska.ac.za wrote: Hey Ken Problem is a bit hard to get my head around, I don't seem to be getting the same results. It may be a version problem, I still am

Re: [casper] Problem setting parameters in fft blocks using mlib_devel

Hey Ken Problem is a bit hard to get my head around, I don't seem to be getting the same results. It may be a version problem, I still am (rather ashamedly) using a very old Matlab version. It would be cool if someone with similar versions to you could try to replicate your results... I will

Re: [casper] Problem setting parameters in fft blocks using mlib_devel

Hi Kenneth I get the following simulink error if I place a new fft block from the library and try to set parameters. Error:Error invoking object method Error due to multiple causes. -- Error in 'new_adc_test/fft': Initialization commands cannot be evaluated. -- Invalid object name:

Re: [casper] 1Gbe Correlator

Hi Arturo It is possible to generate a correlator with data otuput through 1Gbit RJ45 Ethernet? We have 1 ROACH and 1 computer with no 10Gbe. It is possible. You can write some software on the computer (look at the python CORR package) that checks to see when the accumulator is done, copies

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