hi wan,
in case you haven't seen this,
there are some sync pulse guidelines in casper memo 24:
Sync Pulse Usage - July 2008 (Henry Chen, et al)
http://casper.berkeley.edu/wiki/Memos
best wishes,
dan
wan.ch...@csiro.au wrote:
Hi:
After reading the memo of sync pulse, I still feel a little
hi howard,
you can help us hunt for ET
by downloading the s...@home screen saver at
http://seti.berkeley.edu
best wishes,
dan
Dan Werthimer
SETI Program Director
University of California, Berkeley
Howard Relles wrote:
Sir/Madam,
Can you tell me how I can help evaluate/process incoming
if it works with one ibob board (no chaining),
i suggest buying (or asking xilinx to donate)
four USB download cables.
dan
Rurik Primiani wrote:
Hi everyone,
Thanks for the replies! To clarify a little more, our system is now on
the summit of Mauna Kea so physically checking jumpers and
wan,
i strongly advising the standard bee_xps tools
that everyone in the casper collaboration
uses. if you use a different set of tools then
people won't be able to assist you, and your design
won't be able to be used by other people.
best wishes,
dan
wan.ch...@csiro.au wrote:
Hi Henry:
on the modules I will use in my
design if I could understand your library development process. But
unfortunately, there is less documents talking about the casper library
development process. I hope I could get some help at this point.
Thanks
Wan
-Original Message-
From: Dan Werthimer
G Jones wrote:
Hi John,
I have brought this up a few time on this and the BEE2 mailing lists
(archives???).
hi glenn,
be careful what you say on these mailings:
billy made a search-able archive of the casper mailing, and
he will put it on the web site soon.
dan
hi wan,
regarding your question on roach I/O:
in about a month, roach will be running BORPH,
a linux operating system for fpga's
(the operating system we use on the BEE2).
in BORPH, registers, block rams and fifo's
in your simulink design appear as linux files
which you can read and write.
hi wan,
sync should be zero on every clock except
it should go high for one clock every N cycles,
where N is in henry chen's memo on sync pulses.
for example simulink spectrometer designs and
examples on how to use sync pulse,
see design gallery at:
dear casper collaborators,
we now have five adc boards that can
plug into ibob's and roach's, and there
is some confusion about what to call them.
we had a discussion about ADC nomenclature yesterday,
and we suggest the following names:
ADC2x1000-8
is the casper dual iADC: 2 inputs,
I did get strange results when my sync pulse was too short, but that is
likely just the block resetting before the reorder finishes.
as laura points out, the FFT's minimum sync pulse period is tricky:
see casper memo #24
http://casper.berkeley.edu/memos/sync_memo_v1.pdf
btw, many people have
hi jonathan,
we expect roach boards will be about $2500 each, plus FPGA.
you'll need to add DRAM ($50 min), ATX enclosure ($100), and
ATX power supply ($50).
there are several ADC boards you can use, but only two ADC
board that can sample 1 Gsps currently available:
a) the Atmel/E2V dual
hi andrew,
i'm ccing aaron parsons on this, designer of the original fft blocks.
aaron might be able to comment on your email.
as far as i know, no one has ever used the overflow outputs
from the FFT blocks, so you may be the first person to debug
this.
best wishes,
dan
Andrew Martens
hi jan,
the ADC time domain data in your plots looks
like it might not be time ordered correctly.
time is perhaps swapped in groups of four:
eg: ADC outputs samples t0, t1, t2, t3, t4, t5
and you might be displaying and analysing in this order:
t3,t2,t1,t0,t7,t6,t5,t4,t11,t10,t9,t8
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