[casper] Setting DCM in CASPER

Hi, Is it possible to set the user clock to arbitrary frequencies using the DCM without venturing too far from the CASPER tool flow? Any examples would be appreciated, either for the BEE2 or iBOB Thanks, Glenn

Re: [casper] Work around for long FFTs/PFBs

that variable to get around the problem. -Terry On May 5, 2008, at 6:51 PM, G Jones wrote: Hello, Was a work around ever found for using the green blocks for long FFTs/PFBs? I am running into the problem where the initial value vector in a block ram is too long so it gets truncated

Re: [casper] ibob clkmeasure command

I am also interested in this. I see that the clock measure and reset functionality seems to be implemented in /pcores/opb_clockcontroller/hdl/user_logic.vhd All of the logic in there seems like it should work, but when you look at the system.mhs file, the relevant signals are connected to dcm_2 in

Re: [casper] BEE2 Build Times

I haven't had exactly this problem, but I have had designs meet timing and then changing just the slightest thing makes it miss timing by a lot. I think the place and route is sort of heuristic, so just by chance it gets an easy job some days and other days it spends hours going in the wrong

Re: [casper] XAUI sync problem

I think what must be happening is even though your iBOB and BEE2 are running on the same clock, the XAUI links have independent 156.25 MHz clocks, so even though the same data rate is going in as coming out, the data is available at the other end of the link at slightly different times, so they

[casper] LWIP in 10.1

Hello, I'm trying to start using the 10.1 tool flow. Compiling a simple design with the iBOB LWIP block yields this error: ERROR:MDT - IPNAME:opb_ethernetlite HW_VER:1.01.a - Can not find valid MPD I opened XPS and indeed it seems like the only version available is 2.00.a Is there any way to get

Re: [casper] LWIP in 10.1

19, 2008 at 11:46 AM, G Jones glenn.calt...@gmail.com wrote: (Replying to the list for the benefit of everyone once the archive is created.) I copied the previous version over, and everything went smoothly up until the CopyFiles part for generating the drivers. It seems to still be copying

Re: [casper] LWIP in 10.1

files are not being found. Does anyone know why this might be the case, or how I might fix this? I see the same behavior regardless if I run through bee_xps or just xps from the command line. Thanks, Glenn On Tue, Aug 19, 2008 at 1:48 PM, G Jones glenn.calt...@gmail.com wrote

[casper] Possible 10.1 FFT fix

Hello, I think I am seeing the problem with the 10.1 FFT that Terry told me about involving the Configurable Subsystems used for the twiddle generators. I think the solution may be in this paragraph from the MATLAB help about Configurable Subsystems: Note If you add or remove blocks from a

[casper] Behavioral HDL in 10.1

Hello again, Sorry for all the 10.1 related emails. Does anyone know if libraries in general should use the Behavioral HDL option or not? The register retiming parameter seems to have changed to Behavioral HDL in the delay block for instance. Do these really behave the same way? Thanks, Glenn

Re: [casper] Invalid setting in SubSystem 'casper_library/Correlator' for parameter 'Name' error still happening

I'm going to remove the reconfigurable blocks from the FFT blocks today. Glenn On Tue, Aug 19, 2008 at 9:40 AM, Jason Manley jasonman...@gmail.com wrote: Hey Andrew Terry, Mark and I were actually chatting about this yesterday. I think this might be due to the use of the reconfigurable

[casper] XAUI Slippage

Hello, I think I am seeing some strange XAUI slippage related to the OOB signal when sending data from an iBOB to a BEE2. It sounds similar to an effect that was seen at Green Bank. My iBOB is set up to send 64 bits of data on both XAUIs every other clock with the FPGA clocked at 250 MHz, so the

[casper] SOLVED Re: LWIP in 10.1

I finally found the problem. In the system.xmp file the line: LinkOpt: #IF# strcmp(get(b,'type'),'xps_lwip') #LinkOpt: -llwip4 should be: LFlags: #IF# strcmp(get(b,'type'),'xps_lwip') #LFlags: -llwip4 I have updated the SVN. Thanks for helping/letting me think out loud to solve this. Glenn

Re: [casper] SOLVED Re: LWIP in 10.1

dav...@astro.berkeley.eduwrote: Great sleuthing, Glenn! Do you whether LFlags works with earlier EDK versions or is that a 10.1 change? Thanks, Dave On Sep 3, 2008, at 11:13 , G Jones wrote: I finally found the problem. In the system.xmp file the line: LinkOpt: #IF# strcmp(get(b,'type

Re: [casper] SOLVED Re: LWIP in 10.1

' collect2: ld returned 1 exit status make: *** [Software/executable.elf] Error 1 ERROR:MDT - Error while running make -f system.make init_bram No changes to be saved in MSS file No changes to be saved in XMP file On Wed, Sep 3, 2008 at 2:13 PM, G Jones glenn.calt...@gmail.com wrote: I

Re: [casper] Temperature monitoring in the bee2s?

I looked into this a while ago, and it looked like there was support for the IIC in the BORPH source, but I couldn't get it to compile because I didn't know where the .h files I needed were or how to get the relevant memory locations. If anyone figures this out, I'd be interested to know. Glenn

[casper] Drawings for aluminum iBOB plates

Hello, Does anyone have drawings of the aluminum plates that iBOB and iADCs come mounted on that fit in 6U crates handy? Thanks, Glenn

[casper] reuse_block crashing Matlab w/ 10.1

Hello, I am finding that if I open a 10.1 design in MATLAB, I almost always get a segmentation fault which seems to be related to the find_system call in reuse_block. I can avoid the error by first creating a new simulink design and dragging some reconfigurable blocks from the CASPER DSP libraries

[casper] Running 10.1 designs on BEE2 user FPGAs

Hello, I am finally trying to run some of the designs I have compiled using the 10.1 toolflow on my BEE2 and am running into problems. When I run the bof file, it just hangs. If I check the proc directory, I see that the ioreg directory and contents are correct, but reading or writing the files

Re: [casper] Running 10.1 designs on BEE2 user FPGAs

I forgot to mention, the blinking LED design is running properly on the FPGA (the LEDs blink as expected) so it seems to be an issue with the selectmap or borph. Glenn On Wed, Sep 17, 2008 at 2:51 PM, G Jones glenn.calt...@gmail.com wrote: Hello, I am finally trying to run some of the designs

Re: [casper] Confusion/bug in green FFT block

outputs there as well, so this may be a very old bug, or it may be something flawed with my test. Glenn On Fri, Sep 19, 2008 at 12:58 AM, G Jones glenn.calt...@gmail.com wrote: Attached is a simple 7.1 model that illustrates the problem. The out0 from each fft is different even though the pol0

Re: [casper] User Error: Confusion/bug in green FFT block

they are anymore). Could you see if you can reproduce the problem in the FFT testbench design? On Fri, Sep 19, 2008 at 5:15 AM, G Jones glenn.calt...@gmail.com wrote: I just noticed a bug in the model I sent: I am unpacking a 18_17 complex number as an 8_7 complex number. However, this does

[casper] Problem with 10.1 digital down converter

Hi everyone, I just spent a long time struggling with this problem, so I wanted to warn others in case you run into it. It seems that the 10.1 DDC blocks simulate fine in simulink, but something goes wrong when building the design. The major symptom is that the filter does not have the expected

Re: [casper] Problem with 10.1 digital down converter

a feeling that these counters might not have resets, causing the two counters to come up at random times relative to one another, shifting the phases of the sin/cos and thus the real/imag components. This could be fixed by propagating a sync into these counters. On Wed, Sep 24, 2008 at 1:44 AM, G

Re: [casper] porting pink block map to 10.1

want me to just proceed with mine, and then we can converge in the future. Thanks, Henry G Jones wrote: For anyone who's interested, I've begun porting the map function used in the pink reorder blocks to 10.1. For complex reorderings, the green block seems to be inefficient since

Re: [casper] porting pink block map to 10.1

if you want me to wait so we standardize on yours, or if you want me to just proceed with mine, and then we can converge in the future. Thanks, Henry G Jones wrote: For anyone who's interested, I've begun porting the map function used in the pink reorder blocks to 10.1. For complex

Re: [casper] porting pink block map to 10.1

flip flops as expected since the latency was set to one. Glenn On Thu, Sep 25, 2008 at 3:37 PM, G Jones glenn.calt...@gmail.com wrote: I just threw together a quick design which has two roms, one with ''use placement information turned on and one with it off, and also my port of the espresso

Re: [casper] porting pink block map to 10.1

map. The espresso map ended up as simply flip flops as expected since the latency was set to one. Glenn On Thu, Sep 25, 2008 at 3:37 PM, G Jones glenn.calt...@gmail.com wrote: I just threw together a quick design which has two roms, one with ''use placement information turned on and one

[casper] 7.1 back porting

I'm in the process of back porting most of the improvements that have been made to the green blocks in 10.1. I am committing my changes to http://casper.berkeley.edu/svn/branches/backport_to_7_1/ for anyone who is still using 7.1 and would like to benefit from the improvements. Glenn

Re: [casper] Updated 7.1 library?

Hi John, I started a backport branch of the 7.1 library in http://casper.berkeley.edu/svn/branches/backport_to_7_1/ If you check that out with SVN you'll find the FFT block there uses the new (pink espresso style) reorder block. Eventually I'll expose a setting so you can choose between the logic

[casper] Easy way to rename bit files?

Hello, I often do the run init_bram thing on my designs after changing the powerPC software. Is there an existing, easy way to get the implementation/download.bit file to be moved to the bit_files directory with the design and timestamp name format? Thanks, Glenn

[casper] Question about fft_stage_n Maximum Coefficient Depth

Hello, I've made a spectrometer that uses a 2^11 point biplex (num inputs = 2^0) FFT block, and it works great. I then changed it to 2^12 points and it looks good except that when I put in a CW tone, I get the expected spike plus another spike 2048 channels away. I've checked everything I can

Re: [casper] GAVRT library

Hi John, That's strange, I am routinely using the GAVRT library with the backported 7.1 libraries. I will upload a snapshot of the GAVRT library to the SVN under the caltech directory right now. What sort of failures are you seeing? Glenn On Mon, Oct 20, 2008 at 8:05 AM, John Ford jf...@nrao.edu

Re: [casper] GAVRT library

Ah yes, I've had that happen to me. Unfortunately the superslice block seems to disconnect itself when it gets changed because it has to reassign the port numbers to keep the outputs sensible. I'm not sure why it reconfigures itself like that . I haven't had it happen to me inside another library

Re: [casper] PFB timing error

Hi John, I've definitely run into the same issue, but haven't had a chance to tackle it yet. It could be a pain, but I would try to hack the design to change the PFB coefficients by one LSB or something in one location so they can't be optimized together. It might also help to try and change

Re: [casper] PFB timing error

I think this makes a lot of sense, and now that you mention it I think I recall having similar experiences. Distributed RAM involves making up the coefficient memory, some few Kbytes, out of ~16x1 bit memory elements, so the address logic has to fan out to all of those tiny elements. The BRAM (I

Re: [casper] setting internal USRCLK on BEE2

Hi John, I have brought this up a few time on this and the BEE2 mailing lists (archives???). I would assume that the setting is volatile. I was unable to get enough information to try to bit-bang the IIC bus from the powerPC, despite going through the linux source. There is IIC code there, but I'm

Re: [casper] kurtosis spectrometer c program dumping data

Dave, I tried both things you suggest in my attempts to improve throughput. memcopy works well, and seems to attain ~ 10 Mbit/s. I also defined my own XIo_In32 as: #define XIo_In32(InputPtr) (*(volatile Xuint32 *)(InputPtr)) to avoid the eieio operand being executed. This certainly improved the

Re: [casper] kurtosis spectrometer c program dumping data

Dave, Some answers below. On Mon, Nov 17, 2008 at 11:49 AM, David MacMahon dav...@astro.berkeley.eduwrote: Thanks, Glenn! On Nov 17, 2008, at 11:33 , G Jones wrote: I tried both things you suggest in my attempts to improve throughput. memcopy works well, and seems to attain ~ 10 Mbit/s

[casper] iBOB to BEE2 XAUI cable length

Hello, I know this question comes up a lot, but is a 3 meter XAUI cable usable for transmitting data from an iBOB to a BEE2? I have ready Suraj's memo about testing the link integrity versus preemphasis and differential swing, in which he says packets were always lost eventually. Is this common in

Re: [casper] FW: How to use snap?

Wan, The simplest operation of the snap block is as follows: Write 0 to the snap_ctrl file/register Write 7 to the snap_ctrl file/register to force enable, trigger, and write enable to be true (look under the snap mask to see how it works) Read snap_addr and wait for it to be snaplength - 1 (2047

Re: [casper] FW: How to use snap?

wrote: HI Glenn: Thanks for your great help. By the way, what's the offset when I read from snap_bram? 1 or 4? Thanks Wan -- *From:* G Jones [mailto:glenn.calt...@gmail.com] *Sent:* Wednesday, 27 May 2009 11:31 AM *To:* Cheng, Wan (ATNF, Marsfield) *Cc

Re: [casper] Recipe for BEE2 10Gbe block?

This is documented on the CASPER wiki FAQ: http://casper.berkeley.edu/wiki/FAQ#Q:_I.27m_getting_a_brefclk_error_when_building_a_BEE2_design_with_10_GbE.3F Glenn On Wed, Jul 15, 2009 at 5:13 PM, William Chauncey Barott baro...@erau.eduwrote: Hi all- Can anyone point me to the magic for

Re: [casper] ROACH progress.

Dan, This sounds to me like the behavior I see with long transforms with the maximum coefficient depth setting, where the block tries to use the trick of storing only rounded roots of unity for the last stages. I can't look into it in detail right now, but I recommend looking under the masks to

Re: [casper] ROACH progress.

: Friday, 28 August 2009 10:51 AM To: G Jones Cc: Beresford, Ron (ATNF, Marsfield); casper@lists.berkeley.edu Subject: Re: [casper] ROACH progress. thanks glenn, the trick of using a small number of coefficients for a large transform should work. we've done million point transforms using

[casper] BRAM Constraint

Hello, I'm compiling a design for the BEE2 which uses 240 of the 328 BRAMs. Sometimes when I compile the design, I run into error messages like this: Phase 8.9 WARNING:Place:119 - Unable to find location. BLOCKRAM component

Re: [casper] xlUpdateModel

John, I think the shortcomings of xlUpdateModel are what made the transition from 7.1 to 10.1 so painful. Dynamically drawn blocks like the vacc will not be handled correctly in general. Therefore, I think it will be much easier and reliable to simply redraw the diagram block for block in 10.1.

[casper] hold time

Hello, I've finally started compiling some ROACH designs under 11.3. One thing that I noticed is that the PAR phase now reports both setup and hold timing metrics while routing. I also noticed hold times being critical paths in the timing reports now. I don't remember ever seeing anything like

[casper] Reference to non-existent field 'clock_loc'

Hello, I'm suddenly having trouble with my linux 11.3 machine. Whenever I update a diagram containing the yellow MSSGE block, matlab crashes because of a segfault in an S-function of one of the xilinx blocks in the design. For example, a design with nothing but a counter, MSSGE token and XSG

Re: [casper] Reference to non-existent field 'clock_loc'

On Thu, Dec 10, 2009 at 5:56 PM, G Jones glenn.calt...@gmail.com wrote: Hello, I'm suddenly having trouble with my linux 11.3 machine. Whenever I update a diagram containing the yellow MSSGE block, matlab crashes because of a segfault in an S-function of one of the xilinx blocks in the design

[casper] component switching limit timing error

Hello, I'm getting started using the quadADC with ROACH so I made a simple design to simply catch the ADC data into a snap block. I set the ADC clock to 200 MHz and the system clock source to adc0, also at 200 MHz. When I run the compilation, I get a few timing violations, all saying that the

[casper] Silly NFS problem

Hello, Sorry to bother you all with this, but I'm having trouble getting my ROACH to mount the network file system. I followed the guide, and the DHCP seems to work as well as the TFTP portion. However, when it's time to mount the root file system, I get: Sending DHCP requests ., OK IP-Config:

Re: [casper] Silly NFS problem

All, Thanks for the help, the /24 solved the problem. This is missing from the guide, so I'll update the wiki. Next problem: what's the login for the etch file image? I downloaded the 2009-11-30 image. trying to log in as root yields: Login incorrect without prompting for a password. I looked at

Re: [casper] Silly NFS problem

My mistake, this was a side effect from trying to chmod -R 777 the roach_boot directory. Logging in as root works now. Glenn On Fri, Dec 11, 2009 at 6:58 PM, G Jones glenn.calt...@gmail.com wrote: All, Thanks for the help, the /24 solved the problem. This is missing from the guide, so I'll

Re: [casper] component switching limit timing error

compile before falling-over with cryptic (read: unrelated) error messages. Jason On 11 Dec 2009, at 20:32, G Jones wrote: Hello, I'm getting started using the quadADC with ROACH so I made a simple design to simply catch the ADC data into a snap block. I set the ADC clock to 200 MHz

[casper] Missing parameter in auto_tap_init.m

Hello, The auto_tap_init.m script has a clause that references use_bram_delay, but this variable is not present in the block mask, so an error is generated when the block is updated. Fixing this is going to require updating the casper_library.mdl file. Since I'm not an expert on the correlator

Re: [casper] error compiling fft

Hi Terry, I came across something like this before... it almost looks like 11.3 is doing too good of a job of reducing the map logic to wires, because it looks like it's optimizing away the wires. I haven't found a solution, but maybe this is something Xilinx would be able to fix. I think a test

Re: [casper] ROACH-based pulsar machine?

Hi Tom, One of the main bandwidth limitations in pulsar processing is the length of the dedispersion chirp function, which goes down quadratically with increasing frequency. Generally people split the band up into several ~4 MHz channels and coherently dedisperse each one separately. Each of these

Re: [casper] F engine for Packetized correlator

Keep in mind that the sync input has a 50 ohm termination resistor, so you need a signal generator capable of providing at least a ~3 V pulse across 50 ohms. You definitely do not want to drive this input with a square wave because the 50 ohm termination resistor is small (0603 or so) so with a

Re: [casper] ibob lwip on 10.1

These messages mean that your PowerPC code is too large. This a common occurrence when using LWIP. You need to reduce your code size some how. One way I've done this is by removing verbose error messages from the .c files in the drivers directory. If you haven't added any PowerPC code, make sure

Re: [casper] iADC clocking woes in 11.4 toolflow

is. Cheers Danny On 23/09/2010 17:11, G Jones wrote: Hi Danny, What exactly are you plotting there? It looks like you have 4 simultaneous ADC samples concatenated into a 32 bit word going into your snap block. Your plot scales are 1e8, so it seems like you may be trying to plot the raw 32

Re: [casper] 10gbe to PC

Could it be a route problem since it works when you bind to the interface but not to the IP? What does your routing table show? On Thu, Oct 28, 2010 at 3:47 PM, mch...@physics.ucsb.edu wrote: Hi Dave, Good eye.  Sorry, I corrected that recent blunder, but I still have the same problem.  I

Re: [casper] IBOB Hardware problem

Hi Dale, The first thing I would check is connecting an RS-232 cable to see if you can talk to the FPGA via tiny shell that way. This will also let you run the ifconfig command to see what the iBOB thinks it's IP address is, to make sure there's nothing funny with that. Are you programming the

[casper] X-engine resource requirements

Hello, I am trying to understand the resource requirements for the CASPER X-engine. To reduce confusion, I'm going to consider dual polarization antennas Looking at the xeng block in simulink, it appears that an X engine with no demux will require about acc_len * ceil(Nant/2 + 1) memory

[casper] ADF4350 as sampling clock generator for CASPER projects

Hi, I saw this new product from Analog Devices http://www.analog.com/en/clock-and-timing/pll-synthesizersvcos/adf4350/products/product.html which seems like it may be a good choice for a flexible sampling clock for CASPER projects. The evaluation board is cheaper than the Valon boards at $175 and

Re: [casper] ADF4350 as sampling clock generator for CASPER projects

for this. Dave, Valon does not give a jitter spec, they just point to online phase noise to jitter calculations. I'll calculate it sometime later. Glenn On Fri, Jun 17, 2011 at 1:55 PM, G Jones glenn.calt...@gmail.com wrote: Hi, I saw this new product from Analog Devices http://www.analog.com/en/clock

[casper] Bad 1.5V regulator on iBOB

Hi, One of our iBOBs stopped working recently after going strong for almost 4 years. I found that the 1.5 V rail is at 0 V, implicating the TI PTH05010 regulator. Has anyone else seen one of these fail? I'm going to try swapping it for a new part to see if the iBOB comes back to life. Glenn

Re: [casper] Difficulty in reading BRAMs

Hi, What exactly is happening when the command does not work? Is the read not completing or does the data not look correct? What does happen? Glenn On Fri, Sep 23, 2011 at 3:41 PM, Vikas Asthana vikasf...@gmail.com wrote: Hi, We have a spectrometer giving out 256 FFT channels. But I am having

[casper] Dynamic MMCM settings for ADC83000x2 on ROACH 2

Hi, I'm working on getting the ADC83000x2 yellow block working with ROACH 2. I found that there is some issue with the automatic translation of the legacy DCM parameters specified by that block to the new MMCM, so I have made a new version that explicitly invokes an MMCM. I have used the clock

Re: [casper] toolflow/libraries/firmware update from CASPER workshop 2011

These goals all look very good. Regarding the test suite, one thing I've been thinking of that could help a lot with designing test benches is to invest in some code (or blocks) for the tedious boiler plate that is often needed for this work. One extremely useful function would automatically

Re: [casper] roach adc sampling rate

Hi Louis, The problem is probably that the DCM/MMCM has various configuration parameters which have default values for the clock speeds most commonly used for CASPER designs. To run at lower speeds, you'll need to tweak these values. I thought they can be found in the

Re: [casper] roach adc sampling rate

generation with bee_xps. hope it helps Marco Il giorno 23/gen/2012, alle ore 23.57, G Jones ha scritto: Hi Louis, The problem is probably that the DCM/MMCM has various configuration parameters which have default values for the clock speeds most commonly used for CASPER designs. To run at lower

Re: [casper] missing python modules

Also note that probably all that's needed in corr is katcp_wrapper (is the original failing line something like from corr import katcp_wrapper?). So I have gotten around installing all of the dependencies that corr has (which are not needed for 99% of applications) by looking at the

Re: [casper] Shared BRAM yellow block

Hi Nimish, If the time required to load the coefficients is not critical, you could consider using explicit dual port BRAMs with one fo the ports connected to a shared register for data and a shared register for address. This may give you more control in meeting timing. We've also been

Re: [casper] Matlab Crashing wiht CASPER Library

Hi Ron, I've seen and complained about this problem under ISE/EDK 13 where blocks that contain yellow blocks (such as the snap block) cause such crashes. My suspicion is that the yellow block (xps_library) keeps getting ported without modification from version to version of matlab, and the mdl

Re: [casper] Roach1 uboot network curiosity

Glen, The problem you describe sounds like an issue we had during testing at Green Bank last December where the NRAO DHCP server would release the DHCP entry if the client did not renew it at regular intervals. It turns out that the ROACH linux was not renewing the DHCP entries. I think the final

Re: [casper] 1-2 GHz sampler

I wouldn't be surprised if Ryan has a more clever way to do it, but one option is to use an extension of the method that Matt Morgan and Rick Fisher (i.e. http://www.gb.nrao.edu/electronics/edir/edir320.pdf) developed for I/Q imbalance compensation. Basically you make a filterbank with each of the

Re: [casper] ROACH hardware failures

Jason R. and John, Was the roach running a particularly intensive design at the time around the failure? Just wondering why this part would be failing. Is the current limit somehow being exceeded? Thanks, Glenn On Tue, Jun 19, 2012 at 9:52 AM, Jason Ray j...@nrao.edu wrote: The first time I was

Re: [casper] ibob CX4 with 15m cable?

Hi Ian, This is a known problem. The solution is to use CX4 optical cables. I'm sure someone will chime in with manufacturers and part numbers. Glenn On Wed, Jun 20, 2012 at 2:36 PM, O'Dwyer, Ian J (382G) ian.j.o'dw...@jpl.nasa.gov wrote: Is anyone successfully using 15m long cables with the

[casper] CLKIN1_PERIOD error when building for ROACH II

Hello, I am running into a problem (error message below) when trying to build simple designs for the ROACH II. I am using the ska-sa/mlib_devel freshly cloned from github. I have double checked that my paths only point to this version. I am using ISE 13.4 and MATLAB 2011a. The design is very

Re: [casper] CLKIN1_PERIOD error when building for ROACH II

, how's life? I haven't seen you in awhile--don't I still owe you a beer? :-) --Ryan On 07/20/2012 01:51 PM, G Jones wrote: Hello, I am running into a problem (error message below) when trying to build simple designs for the ROACH II. I am using the ska-sa/mlib_devel freshly cloned from

Re: [casper] CLKIN1_PERIOD error when building for ROACH II

, by 'log file', I meant 'HDL file'. On 07/20/2012 02:13 PM, G Jones wrote: I agree, but the mystery is how that crazy binary value is getting in there... I should also note that I was able to build ROACH II designs with the casper-astro/mlib_devel, but the resulting boffiles caused a kernel

Re: [casper] CLKIN1_PERIOD error when building for ROACH II

100 In the data/roach_infrastructure_v2_1_0.mpd, CLK_FREQ is set to 100. The data type is indicated as integer which is a bit suspicous, but it's the same in the working casper-astro/mlib_devel Glenn On Fri, Jul 20, 2012 at 2:17 PM, G Jones glenn.calt...@gmail.com wrote: Yep, I agree again

[casper] Strange behavior with sys_clk/sys_clk2x on ROACH II

Hi, We're working on some calibration logic for a new ADC for the ROACH II. The logic needs an always available clock, so we're trying to use sys_clk. Using ROACH II, when we have something like this in our system.mhs file: BEGIN calibration_block ... PORT clk = sys_clk ... It compiles OK, but

Re: [casper] Corr python package

Hi, For anyone who runs into these dependency problems: Please note that you can simply install the katcp_wrapper.py file into your python path and it will work independently of the rest of corr (you'll still need katcp installed of course). You can then use the functions simply by doing: import

Re: [casper] xilinx glibc issues

I suggest using ISE 13 if that's an option for you. On Thu, Aug 9, 2012 at 4:47 PM, Alex Zahn avzah...@gmail.com wrote: I've been trying to get all the mssge toolflow stuff running on a new SL 5.8 machine. Everything works except that compilation fails at xst synthesis for even the simplest

Re: [casper] Patch for windows with cygwin

Hi, I strongly recommend not having cygwin installed on a windows system with the toolflow. Xilinx EDK includes its own version of cygwin and the two will conflict with inexplicable errors and failures. Glenn On Wed, Aug 22, 2012 at 1:44 PM, Gopal Narayanan go...@astro.umass.edu wrote: Hello,

Re: [casper] Patch for windows with cygwin

, outside of this issue with gen_xps_files.m, I have not seen any problems with having cygwin installed on my windows machine. I run Xilinx ISE 13.4, perhaps some of the issues you mention are solved for this version? Gopal On 08/22/2012 02:18 PM, G Jones wrote: Hi, I strongly recommend

Re: [casper] Which OS for 10.1

32-bit XP is your best (only?) choice. The ISE/EDK part of the tools will run on linux, but not the simulink part. On Fri, Sep 7, 2012 at 2:03 AM, Andrea Mattana a.matt...@med.ira.inaf.it wrote: Hi old caspers ;) I'm going to install the dear old friend toolflow 10.1 for my IBOBs and Bee2 on

[casper] gpuocelot

Hi, Someone just pointed this gpuocelot project out to me: http://code.google.com/p/gpuocelot/ It looks pretty interesting, particularly if the AMD/ATI cards are really able to beat the NVIDIA cards and if this code can really make existing CUDA code run at full speed on the AMD cards. I'm a bit

Re: [casper] Correlator using the National ADC card

Hi Pedro, The VEGAS 1024 channel National ADC design works fine. There is an issue with the ADC yellow block at such high speeds where it sometimes requires reprogramming the FPGA 2-3 times to get the data properly in synch, but otherwise the design works fine. Glenn On Fri, Oct 26, 2012 at 8:36

Re: [casper] building tcpborphserver3

. make clean make should build katcp ppc_4xx-gcc Regards Adam On Mon, Dec 3, 2012 at 10:13 PM, G Jones glenn.calt...@gmail.com wrote: Hi, We need to add some commands to tcpborphserver3 to support communication commands over the external I2C bus. We did this previously

[casper] ROACH 2 PPC I2C

Hi, I'm trying to migrate some code from the ROACH to ROACH 2 which uses the PPC I2C bus. On the ROACH we used linux/i2c-dev.h and accessed /dev/i2c-0. The same code compiles on the ROACH 2 but does not seem to work: the fopen call on /dev/i2c-0 fails. To trace down the problem, I tried using the

Re: [casper] snapshot block with external trigger

Hi, I seem to be running into this same problem. Will tcpborphserver2 run on the same linux kernel or do I need to change to a borph specific kernel? Thanks, Glenn On Fri, Dec 7, 2012 at 2:41 AM, Henno Kriel he...@ska.ac.za wrote: Hi Dave I think Andrews point 3 is relevant. We have picked

[casper] uImage for ROACH 2 with no USB and tcpborphserver2

Hi, In light of the possible issues we're having with tcpborphserver3, we're trying to revert to tcpborphserver2. To do so, we tried the uImage-r2borph2 but it is freezing at boot at ppc-soc-ohci ppc-soc-ohci.0: USB Host Controller ppc-soc-ohci ppc-soc-ohci.0: new USB bus registered, assigned bus

Re: [casper] uImage for ROACH 2 with no USB and tcpborphserver2

To answer my own question, it appears the uImage-nousb is also setup for tcpborphserver3. Is there a uImage that has USB disabled and works with tcpborphserver2? We really need this... Thanks, Glenn On Fri, Dec 7, 2012 at 11:45 AM, G Jones glenn.calt...@gmail.com wrote: Hi, In light

Re: [casper] uImage for ROACH 2 with no USB and tcpborphserver2

logical, but I don't see any USB related changes in the last several months... Where is the code needed to produce a uImage file? Thanks, Glenn On Fri, Dec 7, 2012 at 1:10 PM, G Jones glenn.calt...@gmail.com wrote: To answer my own question, it appears the uImage-nousb is also setup

Re: [casper] snapshot block with external trigger

So far, the wordwrite workaround does not appear to be working for me, but I'm still investigating. Glenn On Mon, Dec 10, 2012 at 2:12 PM, Alec Rust alec.r...@ska.ac.za wrote: Dave if the wordwrite workaround works lets stick to that for now. The workaround Marc compiled is not really good for

[casper] Access to ROACH 2 10 GbE ARP table from PPC?

Hi, Is it possible to access the ARP table from the PPC on ROACH2? I'd like to see what entries it contains and if possible populate it. Thanks, Glenn

Re: [casper] ROACH 2 ARP

, and the 02:02:0A... MAC is this ROACH2 itself. So it seems like it is receiving and interpreting ARPs OK. It's just not sending them itself... Any ideas? Thanks, Glenn On Tue, Dec 18, 2012 at 10:58 AM, G Jones glenn.calt...@gmail.com wrote: Hi, In the last couple of days our ROACH2's have decided

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