> On Apr 29, 2024, at 1:59 AM, Steve Lewis via cctalk
> wrote:
>
> After learning more about the PALM processor in the IBM 5100, it has a
> similarity to the 6502 in that the first 128 bytes of RAM is a "register
> file." All its registers (R0 to R15, across 4 interrupt "layers") occupy
>
After learning more about the PALM processor in the IBM 5100, it has a
similarity to the 6502 in that the first 128 bytes of RAM is a "register
file." All its registers (R0 to R15, across 4 interrupt "layers") occupy
those first addresses. In addition, they are physically on the processor
itself
On Mon, Apr 22, 2024 at 02:45:50PM -0500, Mike Katz via cctalk wrote:
> Cycle accurate emulation becomes impossible in the following circumstances:
>
> * Branch prediction and pipelining can cause out of order execution
>and the execution path become data dependent.
> * Cache memory. It
Fred Cisin via cctalk [24/04/2024 02.06]:
Did the Dimension 68000 (a multi-processor machine) have Z80 and 6502?
Commodore 128 had Z80 and 6502
Z80 and 8502, actually.
--
Hilsen Harald
On 4/24/24 13:10, David Brownlee via cctalk wrote:
> Typically the second processor would run as primary, using the
> original 6502 to handle input, display and I/O (and on 32016 you
> *really* wanted someone else to deal with anything time critical like
> interrupts :)
Thats the way we did it
On 2024-04-24 2:55 p.m., Gordon Henderson via cctalk wrote:
On Wed, 24 Apr 2024, David Brownlee via cctalk wrote:
If we're talking about machines with a Z80 and 6502, it would be
remiss not to link back to the machine mentioned in the original
message - the BBC micro, with its onboard 6502 and
On Wed, 24 Apr 2024, David Brownlee via cctalk wrote:
If we're talking about machines with a Z80 and 6502, it would be
remiss not to link back to the machine mentioned in the original
message - the BBC micro, with its onboard 6502 and "Tube" interface
which could take a second processor option,
On Wed, 24 Apr 2024 at 01:18, Bill Gunshannon via cctalk
wrote:
>
> On 4/23/2024 8:06 PM, Fred Cisin via cctalk wrote:
> > Did the Dimension 68000 (a multi-processor machine) have Z80 and 6502?
> >
>
> What about the Tandy 16 and 6000. M68K and Z80.
If we're talking about machines with a Z80
On 4/24/24 11:34, Fred Cisin wrote:
Did the Dimension 68000 (a multi-processor machine) have Z80 and 6502?
>
> On Tue, 23 Apr 2024, Chuck Guzis via cctalk wrote:
>> Couldn't Bill Godbout's CPU-68K board co-exist with other CPU boards?
>
> Did he, or anybody else, make an S100 6502 CPU
Did the Dimension 68000 (a multi-processor machine) have Z80 and 6502?
On Tue, 23 Apr 2024, Chuck Guzis via cctalk wrote:
Couldn't Bill Godbout's CPU-68K board co-exist with other CPU boards?
Did he, or anybody else, make an S100 6502 CPU board?
On 4/24/24 10:54, Robert Feldman via cctalk wrote:
> The Otrona Attache 8:16 had a Z80A and an 8086 on a daughter card.
Of course, Godbout offered the S100 85/88 board in the same vein.
--CHuck
The Otrona Attache 8:16 had a Z80A and an 8086 on a daughter card.
Bob
On 4/23/24 21:06, ben via cctalk wrote:
>>
> I remember Bill Godbout's PACE ads. Now I got the $$$ and time I can't
> find any chips.
National was handing the chips with manuals out for free at on WESCON--I
got mine there, built up an S100 board with all of the interface logic
(I think the PACE
On 2024-04-23 8:40 p.m., Chuck Guzis via cctalk wrote:
On 4/23/24 17:18, Bill Gunshannon via cctalk wrote:
On 4/23/2024 8:06 PM, Fred Cisin via cctalk wrote:
Did the Dimension 68000 (a multi-processor machine) have Z80 and 6502?
Couldn't Bill Godbout's CPU-68K board co-exist with other CPU
On 4/23/24 17:18, Bill Gunshannon via cctalk wrote:
>
>
> On 4/23/2024 8:06 PM, Fred Cisin via cctalk wrote:
>> Did the Dimension 68000 (a multi-processor machine) have Z80 and 6502?
Couldn't Bill Godbout's CPU-68K board co-exist with other CPU boards?
--Chuck
On Tue, 23 Apr 2024, Van Snyder via cctalk wrote:
I had a "Magic Sac" thing-y that plugged into the ROM port of my Atari
1040. When I put a Mac ROM into its socket, I could run most Mac
programs that I had.
That was pretty cool
The developer of it said that when he met with Apple's lawyers,
On Tue, 2024-04-23 at 17:06 -0700, Fred Cisin via cctalk wrote:
> a significant portion (I remember at one time, somebody at Apple said 20%)
> > > of Apple users had the Microsoft SoftCard Z80, or imitations thereof.
I had a "Magic Sac" thing-y that plugged into the ROM port of my Atari
1040.
Did the Dimension 68000 (a multi-processor machine) have Z80 and 6502?
On Tue, 23 Apr 2024, Bill Gunshannon via cctalk wrote:
What about the Tandy 16 and 6000. M68K and Z80.
Yes.
But the original comment that I was responding to was asking Z80 and 6502.
Cromemco also had a 68000 and Z80
On 4/23/2024 8:06 PM, Fred Cisin via cctalk wrote:
Did the Dimension 68000 (a multi-processor machine) have Z80 and 6502?
What about the Tandy 16 and 6000. M68K and Z80.
bill
Did the Dimension 68000 (a multi-processor machine) have Z80 and 6502?
Commodore 128 had Z80 and 6502
On Tue, 23 Apr 2024, Mike Katz wrote:
I think Ohio Scientific made a computer called the 3B or something like that
that had a 6502, a Z-80 and a 6800 in it. If my memory serves.
On
I think Ohio Scientific made a computer called the 3B or something like
that that had a 6502, a Z-80 and a 6800 in it. If my memory serves.
On 4/23/2024 7:00 PM, Fred Cisin via cctalk wrote:
On Tue, 23 Apr 2024, Van Snyder via cctalk wrote:
I shared an office with a lady who got a computer
On Tue, 23 Apr 2024, Van Snyder via cctalk wrote:
I shared an office with a lady who got a computer from Ohio Scientific
that had both a Z80 and a 6502. It also had two 5/25" floppy drives.
She also got a tee-shirt that said "I have two floppies." Except she
didn't.
aside from her floppies, .
> I shared an office with a lady who got a computer from Ohio Scientific
> that had both a Z80 and a 6502.
The Commodore 128 says hi.
--
personal: http://www.cameronkaiser.com/ --
Cameron Kaiser * Floodgap Systems * www.floodgap.com * ckai...@floodgap.com
On Tue, 2024-04-23 at 13:27 +0200, Peter Corlett via cctalk wrote:
> The Z80 takes three or four memory cycles to perform a memory access versus
> the 6502 accessing memory on every cycle,
I shared an office with a lady who got a computer from Ohio Scientific
that had both a Z80 and a 6502. It
On Monday (04/22/2024 at 08:55PM -0700), Chuck Guzis wrote:
> On 4/22/24 20:36, Chris Elmquist wrote:
> > Hey, I did that on Sunday afternoons on the Star-100 with Lincoln and his
> > son PD when I was in 8th grade. I never became a manager though :-)
> >
> > Chris
>
> Trying to remember, was
On Mon, Apr 22, 2024 at 01:06:42AM +0100, Peter Coghlan via cctalk wrote:
[...]
> This was implemented by a humble 6502 running at (mostly) 2MHz, with one 8
> bit arithmetic register, two 8 bit index registers, one 8 bit stack
> pointer, a 16 bit program counter and a few flag bits.
> I would
On 4/22/24 20:36, Chris Elmquist wrote:
> Hey, I did that on Sunday afternoons on the Star-100 with Lincoln and his son
> PD when I was in 8th grade. I never became a manager though :-)
>
> Chris
Trying to remember, was the star the same as the 6000 as far as wiring?
That is, twisted pair and
Hey, I did that on Sunday afternoons on the Star-100 with Lincoln and his son
PD when I was in 8th grade. I never became a manager though :-)
Chris
--
Chris Elmquist
> On Apr 22, 2024, at 3:22 PM, Chuck Guzis via cctalk
> wrote:
>
> On 4/22/24 13:02, Wayne S wrote:
>> I read somewhere that
On 4/22/24 19:14, Bill Gunshannon via cctalk wrote:
On 4/22/2024 2:30 PM, Paul Koning wrote:
On Apr 22, 2024, at 2:09 PM, Bill Gunshannon via cctalk
wrote:
Following along this line of thought but also in regards
all our
other small CPUs
Would it not be possible to use
On 4/22/24 17:35, Paul Koning wrote:
> What about the coincidence that a lot of today's logic runs on 3.3 volts,
> just about the same as the first generation of IC logic (RTL).
I think I still have some survivors from the Motorola HEP mwRTL kit.
TO-100, I think. RTL was pretty cool--slow,
> On Apr 22, 2024, at 8:14 PM, Bill Gunshannon
> wrote:
>
> On 4/22/2024 2:30 PM, Paul Koning wrote:
>>> ...
>> Of course the VAX started out as a modified PDP-11; the name makes that
>> clear. And I saw an early document of what became the VAX 11/780, labeled
>> PDP-11/85. Perhaps that
> On Apr 22, 2024, at 7:03 PM, Chuck Guzis via cctalk
> wrote:
>
> On 4/22/24 14:34, dwight via cctalk wrote:
>
>> For those that don't know what a UV(UX)201 was, it was most commonly used
>> for audio amplification in early battery powered radios. These used a lot of
>> filament current,
On 4/22/2024 2:30 PM, Paul Koning wrote:
On Apr 22, 2024, at 2:09 PM, Bill Gunshannon via cctalk
wrote:
Following along this line of thought but also in regards all our
other small CPUs
Would it not be possible to use something like a Blue Pill to make
a small board (small enough
On 4/22/24 16:06, Paul Berger via cctalk wrote:
On 2024-04-22 5:21 p.m., Chuck Guzis via cctalk wrote:
On 4/22/24 13:02, Wayne S wrote:
I read somewhere that the cable lengths were expressly
engineered to provide that signals arrived to chips at
nearly the same time so as to reduce chip
On 4/22/24 14:34, dwight via cctalk wrote:
> For those that don't know what a UV(UX)201 was, it was most commonly used for
> audio amplification in early battery powered radios. These used a lot of
> filament current, not like later miniature tubes.
> They had a UV(UX)200 tube for RF detections
Well, it was beyond the PC's and Sparc stations we had access to at the
time.
On 4/22/2024 3:28 PM, Christian Kennedy via cctalk wrote:
On 4/22/24 13:12, Fred Cisin via cctalk wrote:
On Mon, 22 Apr 2024, Mike Katz via cctalk wrote:
[Big snip -- hopefully I managed to get attribution right,
From: ben via cctalk
Sent: Monday, April 22, 2024 12:43 PM
To: cctalk@classiccmp.org
Subject: [cctalk] Re: Z80 vs other microprocessors of the time.
On 2024-04-22 1:02 p.m., Chuck Guzis via cctalk wrote:
> I'd like to see a Z80 implemented with UV-201 vac
On 4/22/24 14:04, Paul Koning wrote:
> I never had my hands on a 6600, only a 6400 which is a single unit machine.
> So I had to do some thinking to understand why someone would do a register
> transfer with L (shift operation) rather than B (boolean operation) when I
> first saw that in my
They sure do now, but not back in 1964. :-)
paul
> On Apr 22, 2024, at 5:13 PM, Mike Katz via cctalk
> wrote:
>
> Compilers do that with what is called loop rotation optimization.
>
> On 4/22/2024 3:59 PM, Chuck Guzis via cctalk wrote:
>> On 4/22/24 13:53, Paul Koning via cctalk
True, if 1 cycle per second or minute is an acceptable emulation speed.
For that kind of emulation to work the emulator needs to be fed the same
tasks in the same order and for the same core. This is even more true
when the CPU is waiting on internal or external resources. If you can
Compilers do that with what is called loop rotation optimization.
On 4/22/2024 3:59 PM, Chuck Guzis via cctalk wrote:
On 4/22/24 13:53, Paul Koning via cctalk wrote:
In COMPASS:
MORESA1 A1+B2 (B2 = 2)
SA2 A2+B2
BX6 X1
LX7 X2
SB3
On 2024-04-22 5:21 p.m., Chuck Guzis via cctalk wrote:
On 4/22/24 13:02, Wayne S wrote:
I read somewhere that the cable lengths were expressly engineered to provide
that signals arrived to chips at nearly the same time so as to reduce chip
“wait” times and provide more speed.
That
> On Apr 22, 2024, at 4:59 PM, Chuck Guzis via cctalk
> wrote:
>
> On 4/22/24 13:53, Paul Koning via cctalk wrote:
>> In COMPASS:
>>
>> MORE SA1 A1+B2 (B2 = 2)
>> SA2 A2+B2
>> BX6 X1
>> LX7 X2
>> SB3 B3-2
>> SA6 A6+B2
>> SA7
On 4/22/24 13:53, Paul Koning via cctalk wrote:
> In COMPASS:
>
> MORE SA1 A1+B2 (B2 = 2)
> SA2 A2+B2
> BX6 X1
> LX7 X2
> SB3 B3-2
> SA6 A6+B2
> SA7 A7+B2
> PL b3,MORE
My recollection is that putting the stores
On 4/22/24 13:53, Paul Koning via cctalk wrote:
> In COMPASS:
>
> MORE SA1 A1+B2 (B2 = 2)
> SA2 A2+B2
> BX6 X1
> LX7 X2
> SB3 B3-2
> SA6 A6+B2
> SA7 A7+B2
> PL b3,MORE
> On Apr 22, 2024, at 3:31 PM, ben via cctalk wrote:
>
>
> >One other factor is that RISC machines rely on simple operations >carefully
> >arranged by optimizing compilers (or, in some cases, >skillful programmers).
> > A multi-step operation can be encoded in a >sequence of RISC
On Mon, Apr 22, 2024 at 2:30 PM Paul Koning via cctalk
wrote:
> Anyway, I would think such a small microprocessor could emulate a PDP-11 just
> fine, and probably fast enough. The issue isn't so much the instruction set
> emulation but rather the electrical interface. That's what would be
> On Apr 22, 2024, at 4:21 PM, Mike Katz via cctalk
> wrote:
>
> Once CPUs became faster than memory the faster the memory the faster the CPU
> could run.
>
> That is where CACHE came in. Expensive small high speed ram chips would be
> able to feed the CPU faster except in case of a
> On Apr 22, 2024, at 4:24 PM, Mike Katz via cctalk
> wrote:
>
>> Again, not impossible, but very likely not feasable.
>
> Well not possible with the hardware available at the time.
>
> If one cycle per minute or less is acceptable then I guess it was possible.
>
> That is why we used in
> On Apr 22, 2024, at 4:21 PM, Chuck Guzis via cctalk
> wrote:
>
> On 4/22/24 13:02, Wayne S wrote:
>> I read somewhere that the cable lengths were expressly engineered to provide
>> that signals arrived to chips at nearly the same time so as to reduce chip
>> “wait” times and provide more
Again, not impossible, but very likely not feasable.
On Mon, 22 Apr 2024, Mike Katz wrote:
Well not possible with the hardware available at the time.
Some stuff is getting faster, . . .
Can you estimate how much faster it would need to be?
(perhaps then, log(2) of that, times 18 months?
On 4/22/24 13:12, Fred Cisin via cctalk wrote:
On Mon, 22 Apr 2024, Mike Katz via cctalk wrote:
[Big snip -- hopefully I managed to get attribution right, apologies in
advance if I borked it]
When I was working for a 6800 C compiler company we could simulate
all 68000 CPUs before the
Again, not impossible, but very likely not feasable.
Well not possible with the hardware available at the time.
If one cycle per minute or less is acceptable then I guess it was possible.
That is why we used in circuit emulators to do cycle accurate counting
on more complex machines. This
Once CPUs became faster than memory the faster the memory the faster the
CPU could run.
That is where CACHE came in. Expensive small high speed ram chips would
be able to feed the CPU faster except in case of a cache miss and then
the cache had to reload from slow memory. That is why
On 4/22/24 13:02, Wayne S wrote:
> I read somewhere that the cable lengths were expressly engineered to provide
> that signals arrived to chips at nearly the same time so as to reduce chip
> “wait” times and provide more speed.
That certainly was true for the 6600. My unit manager, fresh out
On Mon, 22 Apr 2024, Mike Katz via cctalk wrote:
Cycle accurate emulation becomes impossible in the following circumstances:
* Branch prediction and pipelining can cause out of order execution
and the execution path become data dependent.
* Cache memory. It can be very difficult to predict a
Cycle accurate emulation becomes impossible in the following circumstances:
* Branch prediction and pipelining can cause out of order execution
and the execution path become data dependent.
* Cache memory. It can be very difficult to predict a cache flush or
cache miss or cache look
I read somewhere that the cable lengths were expressly engineered to provide
that signals arrived to chips at nearly the same time so as to reduce chip
“wait” times and provide more speed.
So that begs a question. Older chips like the Z80 and 8080 lines required other
support chips that added
> On Apr 22, 2024, at 3:45 PM, Mike Katz wrote:
>
> Cycle accurate emulation becomes impossible in the following circumstances:
> • Branch prediction and pipelining can cause out of order execution and
> the execution path become data dependent. ...
I disagree. Clearly a logic model
On 4/22/24 12:31, ben via cctalk wrote:
>
>
> Classic cpu designs like the PDP-1, might be better called RISC.
> Back then you matched the cpu word length to data you were using.
> 40 bits made a lot of sense for real computing, even if you
> had no RAM memory at the time, just drum.
I'd call
On 2024-04-22 1:02 p.m., Chuck Guzis via cctalk wrote:
I'd like to see a Z80 implemented with UV-201 vacuum tubes... :) --Chuck
On Mon, 22 Apr 2024, ben via cctalk wrote:
Real computers use glow tubes like the NE-2 or the NE-77.:)
I thought that real computers use gears
On 2024-04-22 1:02 p.m., Chuck Guzis via cctalk wrote:
I'd like to see a Z80 implemented with UV-201 vacuum tubes... :)
--Chuck
Real computers use glow tubes like the NE-2 or the NE-77.:)
>One other factor is that RISC machines rely on simple operations
>carefully arranged by optimizing compilers (or, in some cases,
>skillful programmers). A multi-step operation can be encoded in a
>sequence of RISC operations run through an optimizing scheduler more
>effectively than the
On 4/22/24 11:46, Paul Koning wrote:
>
> Probably not. Cycle accurate simulation is very hard. It's only rarely been
> done for any CPU, and if done it tends to be incredibly slow. I remember
> once using a MIPS cycle-accurate simulator (for the SB-1, the core inside the
> SB-1250, later
> On Apr 22, 2024, at 2:34 PM, Chuck Guzis via cctalk
> wrote:
>
> On 4/22/24 11:09, Bill Gunshannon via cctalk wrote:
>
>>
>> Following along this line of thought but also in regards all our
>> other small CPUs
>>
>> Would it not be possible to use something like a Blue Pill to make
On 4/22/24 14:09, Bill Gunshannon via cctalk wrote:
Would it not be possible to use something like a Blue Pill to make
a small board (small enough to actually fit in the CPU socket) that
emulated these old CPUs? Definitely enough horse power just wondered
if there was enough room for the
On 4/22/24 11:09, Bill Gunshannon via cctalk wrote:
>
> Following along this line of thought but also in regards all our
> other small CPUs
>
> Would it not be possible to use something like a Blue Pill to make
> a small board (small enough to actually fit in the CPU socket) that
> emulated
> On Apr 22, 2024, at 2:09 PM, Bill Gunshannon via cctalk
> wrote:
>
>
>
> Following along this line of thought but also in regards all our
> other small CPUs
>
> Would it not be possible to use something like a Blue Pill to make
> a small board (small enough to actually fit in the
Following along this line of thought but also in regards all our
other small CPUs
Would it not be possible to use something like a Blue Pill to make
a small board (small enough to actually fit in the CPU socket) that
emulated these old CPUs? Definitely enough horse power just wondered
if
A bit of a postscript: The ALU on the 8085 according to Ken is 8 bits wide.
https://www.righto.com/2013/01/inside-alu-of-8085-microprocessor.html
--Chuck
On 4/22/24 09:54, Lamar Owen via cctalk wrote:
> On 4/22/24 12:18, Chuck Guzis via cctalk wrote:
>> I don't know if this applies to the Z80, but on the 8080, 16-bit
>> increment/decrement is handled by a separate increment block (also used
>> to advance the P-counter and stack operations).
On 4/22/24 12:18, Chuck Guzis via cctalk wrote:
I don't know if this applies to the Z80, but on the 8080, 16-bit
increment/decrement is handled by a separate increment block (also used
to advance the P-counter and stack operations). Probably one of the
reasons that INX/DCX doesn't set any
On Mon, Apr 22, 2024 at 9:18 AM Chuck Guzis via cctalk
wrote:
>
> On 4/22/24 08:36, Lamar Owen via cctalk wrote:
>
> > Die real estate forced the design to do without a full 8-bit ALU. When
> > you have a 4-bit ALU, and you are doing 16-bit math, you will need 4
> > cycles through the ALU.
>
> I
On 4/22/24 08:36, Lamar Owen via cctalk wrote:
> Die real estate forced the design to do without a full 8-bit ALU. When
> you have a 4-bit ALU, and you are doing 16-bit math, you will need 4
> cycles through the ALU.
I don't know if this applies to the Z80, but on the 8080, 16-bit
> The Z80 is dead; long live the Z80.
They said that about the UX-201A...and every year hundreds or
thousands of new ones show up.
--
Will
On 4/21/24 20:06, Peter Coghlan via cctalk wrote:
Why is that? Did the Z80 take more cycles to implement it's more complex
instructions? Is this an early example of RISC vs CISC?
Z80 is blessed with a 4-bit ALU, verified by reverse engineering dieshots (
> On Apr 21, 2024, at 9:17 PM, Will Cooke via cctalk
> wrote:
>
>
>
>> On 04/21/2024 7:06 PM CDT Peter Coghlan via cctalk
>> wrote:
>>
>>
>>
>> Why is that? Did the Z80 take more cycles to implement it's more complex
>> instructions? Is this an early example of RISC vs CISC?
>>
>>
> On 04/21/2024 7:06 PM CDT Peter Coghlan via cctalk
> wrote:
>
>
>
> Why is that? Did the Z80 take more cycles to implement it's more complex
> instructions? Is this an early example of RISC vs CISC?
>
> Regards,
> Peter Coghlan
I'm certainly no authority, but I have programmed both
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