[clang] [clang] Introduce `SemaRISCV` (PR #92682)

https://github.com/kito-cheng approved this pull request. LGTM as the original author of `SemaRISCVVectorLookup.cpp` :) It's great to see we can put all RISC-V related stuff within same place rather than many different files. https://github.com/llvm/llvm-project/pull/92682

[clang] [RISCV] Remove unneeded multiply in RISCV CodeGenTypes (PR #92644)

https://github.com/kito-cheng approved this pull request. https://github.com/llvm/llvm-project/pull/92644 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add smstateen extension (PR #90818)

https://github.com/kito-cheng commented: Don't forgot `llvm/docs/RISCVUsage.rst`, otherwise LGTM :P https://github.com/llvm/llvm-project/pull/90818 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

@@ -138,6 +155,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { /// initializeProperties(). RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; } + RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; } + kito-cheng

[clang] [clang][RISCV] Support RVV bfloat16 C intrinsics (PR #89354)

https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/89354 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Support RVV bfloat16 C intrinsics (PR #89354)

kito-cheng wrote: > Oh, I forgot to remove them. Or do you think they should be moved to bfloat > folder to make them consistent? Remove files from this PR, that should be a separated NFC PR for moving those files, but I am fine to keep those file in same place :)

[clang] [clang][RISCV] Support RVV bfloat16 C intrinsics (PR #89354)

kito-cheng wrote: vfncvtbf16.c, vfwcvtbf16.c and vfwmaccbf16.c already in the LLVM repo, so I think those files could removed from this PR? https://github.com/llvm/llvm-project/pull/89354 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/88474 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

@@ -119,6 +119,7 @@ on support follow. ``Za128rs`` Supported (`See note <#riscv-profiles-extensions-note>`__) ``Za64rs``Supported (`See note <#riscv-profiles-extensions-note>`__) ``Zacas`` Supported (`See note <#riscv-zacas-note>`__) +

[clang] [llvm] [RISCV] Support Zama16b1p0 (PR #88474)

kito-cheng wrote: `llvm/docs/RISCVUsage.rst` need update https://github.com/llvm/llvm-project/pull/88474 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add B extension (PR #76893)

kito-cheng wrote: Jeff told me it's still need wait TSC vote for the ratification, anyway it will ratify this month. https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [llvm] [RISCV] Add B extension (PR #76893)

kito-cheng wrote: Could you add `B` into CombinedExtsEntry and added a test for that? https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add B extension (PR #76893)

kito-cheng wrote: It passed public review[1] and merged into riscv-isa-manual[2], so I think it's time to mark it as 1.0 and moving forward :) [1] https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/KetVUCQkfK4/m/Y3Dbd2pvAAAJ?utm_medium=email_source=footer [2]

[clang] [llvm] [RISCV] Zimop/Zcmop are ratified (PR #87966)

https://github.com/kito-cheng approved this pull request. LGTM :) https://github.com/llvm/llvm-project/pull/87966 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Disallow target attribute use in multiversioning (PR #85899)

https://github.com/kito-cheng approved this pull request. LGTM :) https://github.com/llvm/llvm-project/pull/85899 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Disallow target attribute use in multiversioning (PR #85899)

kito-cheng wrote: Add a testcase like AArch64 https://reviews.llvm.org/D150867 ? https://github.com/llvm/llvm-project/pull/85899 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] Revert "[Driver] Default riscv*- triples to -fdebug-default-version=4" (PR #84119)

https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/84119 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [Driver] Default -msmall-data-limit= to 0 and clean up code (PR #83093)

kito-cheng wrote: There is some discussion in last (2024/2/29) LLVM sync up meeting: We all agree that might not useful in linux target and those platforms disable GP relaxation, like Android and fuchsia; However it's still useful for embedded toolchain, so this change may surprise those

[clang] [lld] [llvm] [RISCV] Support .note.gnu.property for enable Zicfiss and Zicfilp extension (PR #77414)

https://github.com/kito-cheng edited https://github.com/llvm/llvm-project/pull/77414 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [clang][RISCV] Reorder sema check for RVV type (PR #83553)

https://github.com/kito-cheng commented: Could you add a testcase? https://github.com/llvm/llvm-project/pull/83553 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Disable generation of asynchronous unwind tables for RISCV baremetal (PR #81727)

https://github.com/kito-cheng closed https://github.com/llvm/llvm-project/pull/81727 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Disable generation of asynchronous unwind tables for RISCV baremetal (PR #81727)

kito-cheng wrote: RISC-V GCC has enabled `-fasynchronous-unwind-tables` and `-funwind-tables` by default for Linux target, and disabled by default for baremetal, so generally LGTM since it align the behavior with GCC, but I would like to wait @asb's response. NOTE: The patch[1] is come from

[clang] [Clang][RISCV] Add assumptions to vsetvli/vsetvlimax (PR #79975)

kito-cheng wrote: Also I guess most of RVV intrinsic could add `const` too, that could help some generic optimization work better like CSE. https://github.com/llvm/llvm-project/pull/79975 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [Clang][RISCV] Add assumptions to vsetvli/vsetvlimax (PR #79975)

kito-cheng wrote: I guess we need add that at RVVEmitter::createbuilt...@riscvvemitter.cpp? [1] https://github.com/llvm/llvm-project/blob/main/clang/utils/TableGen/RISCVVEmitter.cpp#L418 [2] https://github.com/llvm/llvm-project/blob/main/clang/include/clang/Basic/Builtins.h#L122-L124 [3]

[llvm] [clang] [RISCV] Support constraint "s" (PR #80201)

https://github.com/kito-cheng approved this pull request. Just one minor comment, otherwise LGTM :) https://github.com/llvm/llvm-project/pull/80201 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[llvm] [clang] [RISCV] Support constraint "s" (PR #80201)

@@ -0,0 +1,76 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc -mtriple=riscv32 -relocation-model=static < %s | FileCheck %s --check-prefix=RV32 +; RUN: llc -mtriple=riscv64 -relocation-model=pic < %s | FileCheck %s

[llvm] [clang] [RISCV] Support constraint "s" (PR #80201)

https://github.com/kito-cheng edited https://github.com/llvm/llvm-project/pull/80201 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Add assumptions to vsetvli/vsetvlimax (PR #79975)

kito-cheng wrote: Does it possible to add testcases to demonstrate that can improve optimization? https://github.com/llvm/llvm-project/pull/79975 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[llvm] [clang] [RISCV] RISCV vector calling convention (1/2) (PR #77560)

https://github.com/kito-cheng edited https://github.com/llvm/llvm-project/pull/77560 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [llvm] [RISCV] Add B extension (PR #76893)

kito-cheng wrote: It tagged with 0.1 now :) https://github.com/riscv/riscv-b/releases/tag/v0.1 https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[llvm] [clang] [RISCV] Relax march string order constraint (PR #78120)

kito-cheng wrote: I am working on GCC part[1], and it's still under review, also @bemg is working very closely with me :) [1] https://gcc.gnu.org/pipermail/gcc-patches/2024-January/642151.html https://github.com/llvm/llvm-project/pull/78120 ___

[clang] [RISCV][clang] Optimize memory usage of intrinsic lookup table (PR #77487)

@@ -463,7 +464,7 @@ void RISCVIntrinsicManagerImpl::CreateRVVIntrinsicDecl(LookupResult , bool RISCVIntrinsicManagerImpl::CreateIntrinsicIfFound(LookupResult , IdentifierInfo *II,

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

kito-cheng wrote: @wangpc-pp did you have interested on helping psABI side? it would be great if you can help since I suspect I don't have enough bandwidth to deal with that soon. https://github.com/llvm/llvm-project/pull/76777 ___ cfe-commits

[llvm] [clang] [RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (PR #76777)

kito-cheng wrote: Hmmm, RISC-V ISA is growth after https://github.com/riscv-non-isa/riscv-elf-psabi-doc/pull/257 again, I mean...we have zfinx and zdinx, which is also valid combination with rv32e/rv64e, so we may need to revise ilp32e ABI again on the psABI side, but my intention is not to

[llvm] [clang] [RISCV] Add B extension (PR #76893)

kito-cheng wrote: Issue created at riscv-b: https://github.com/riscv/riscv-b/issues/3 https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[llvm] [clang] [RISCV] Add B extension (PR #76893)

kito-cheng wrote: And forgot to say: thanks for raise this issue! I didn't aware b extension is back again until this PR created. https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[llvm] [clang] [RISCV] Add B extension (PR #76893)

kito-cheng wrote: I would suggest set it as 0.1 rather than 1.0, and I gonna to ask Ved to add version info as well... https://github.com/llvm/llvm-project/pull/76893 ___ cfe-commits mailing list cfe-commits@lists.llvm.org

[clang] [llvm] [RISCV][MC] Add support for experimental Zcmop extension (PR #76395)

@@ -693,6 +693,13 @@ def HasStdExtZimop : Predicate<"Subtarget->hasStdExtZimop()">, AssemblerPredicate<(all_of FeatureStdExtZimop), "'Zimop' (May-Be-Operations)">; +def FeatureStdExtZcmop :

[clang] [llvm] [clang][RISCV] Change default abi when only have f extension but no d extension (PR #73489)

kito-cheng wrote: short version: GCC isn't change. long version: GCC's configure script isn't change, it's configure script in riscv-gnu-toolchain But I don't have strong opinion on this change since I believe user should explicitly specify that, otherwise it's really to screw up to select

[clang] [clang] Enable --gcc-install-dir for RISCV baremetal toolchains (PR #71803)

https://github.com/kito-cheng approved this pull request. Checked with `Generic_GCC::GCCInstallationDetector::init` to make sure clang will use that to search gcc toolchain, so LGTM. https://github.com/llvm/llvm-project/pull/71803 ___ cfe-commits

[clang] [llvm] Remove experimental from Vector Crypto extensions (PR #69000)

@@ -106,6 +106,8 @@ static const RISCVSupportedExtension SupportedExtensions[] = { {"zdinx", RISCVExtensionVersion{1, 0}}, +{"zexperimental", RISCVExtensionVersion{1, 0}}, + kito-cheng wrote: I guess we don't really need this dummy extension in

[clang] [Clang][RISCV] Add vundefine intrinsics for tuple types (PR #70354)

https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/70354 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [Clang][RISCV] Add vundefine intrinsics for tuple types (PR #70354)

@@ -1,4 +1,4 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 3 kito-cheng wrote: Does this cause those

[clang] [Clang][RISCV] Add vundefine intrinsics for tuple types (PR #70354)

@@ -7,534 +7,2189 @@ #include -// CHECK-RV64-LABEL: define dso_local @test_vundefined_f16mf4 -// CHECK-RV64-SAME: () #[[ATTR0:[0-9]+]] { +// CHECK-RV64-LABEL: define dso_local @test_vundefined_f16mf4( +// CHECK-RV64-SAME: ) #[[ATTR0:[0-9]+]] { // CHECK-RV64-NEXT:

[clang] [Driver] Reject unsupported -mcmodel= (PR #70262)

kito-cheng wrote: LGTM for the RISC-V bits, thanks :) https://github.com/llvm/llvm-project/pull/70262 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)

@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction , MachineBasicBlock , CSI, [&](CalleeSavedInfo ) { return CSR.getReg() == RAReg; })) return; + const RISCVInstrInfo *TII = STI.getInstrInfo(); + if (STI.hasFeature(RISCV::FeatureStdExtZicfiss))

[clang] [RISCV] Implement shadow stack on shadow stack mode with Zicfiss. (PR #68075)

@@ -106,9 +111,14 @@ static void emitSCSEpilogue(MachineFunction , MachineBasicBlock , CSI, [&](CalleeSavedInfo ) { return CSR.getReg() == RAReg; })) return; + const RISCVInstrInfo *TII = STI.getInstrInfo(); + if (STI.hasFeature(RISCV::FeatureStdExtZicfiss))

[clang] [Clang][RISCV] Handle RVV tuple types correctly as OutputOperands for inline asm (PR #67018)

@@ -2524,11 +2551,32 @@ void CodeGenFunction::EmitAsmStmt(const AsmStmt ) { ResultRegIsFlagReg.push_back(IsFlagReg); llvm::Type *Ty = ConvertTypeForMem(QTy); + ResultTruncRegTypes.push_back(Ty); + + // Expressing the type as a structure in inline asm

[clang] [RISCV] Support floating point VCIX (PR #67094)

https://github.com/kito-cheng edited https://github.com/llvm/llvm-project/pull/67094 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] [RISCV] Support floating point VCIX (PR #67094)

https://github.com/kito-cheng commented: The target is support LLVM IR part only, we would like to prevent expose that on the C intrinsic level if possible, because that's intentionally to expose vector with unsigned integer only. https://github.com/llvm/llvm-project/pull/67094

[clang] [RISCV] Support floating point VCIX (PR #67094)

@@ -2441,11 +2441,11 @@ define void @test_sf_vc_fvv_se_e16mf4( %vd, ; CHECK-NEXT:sf.vc.fvv 1, v8, v9, fa0 ; CHECK-NEXT:ret entry: - tail call void @llvm.riscv.sf.vc.fvv.se.iXLen.nxv1i16.f16.iXLen(iXLen 1, %vd, %vs2, half %fs1, iXLen %vl) + tail call void

[clang] [NFC][Clang][RISCV] Remove trailing whitespaces in riscv_vector.td (PR #65762)

https://github.com/kito-cheng approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/65762 ___ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits

[clang] da4fcb0 - [RISCV][Driver] Allow the use of CPUs with a different XLEN than the triple.

Author: Kito Cheng Date: 2023-04-27T14:46:01+08:00 New Revision: da4fcb0c0b281746067f92d8804c18dbce4269bd URL: https://github.com/llvm/llvm-project/commit/da4fcb0c0b281746067f92d8804c18dbce4269bd DIFF: https://github.com/llvm/llvm-project/commit/da4fcb0c0b281746067f92d8804c18dbce4269bd.diff

[libunwind] 9b488ac - [libunwind][RISC-V] Rewrite testcase with C as possible.

Author: Kito Cheng Date: 2023-03-15T17:30:16+08:00 New Revision: 9b488ace17e6be64e61bf20f8ddc3eb563848bde URL: https://github.com/llvm/llvm-project/commit/9b488ace17e6be64e61bf20f8ddc3eb563848bde DIFF: https://github.com/llvm/llvm-project/commit/9b488ace17e6be64e61bf20f8ddc3eb563848bde.diff

[clang] be437f3 - [clang][RISCV] Enable -fasynchronous-unwind-tables by default on Linux

Author: Kito Cheng Date: 2023-03-03T16:13:53+08:00 New Revision: be437f3bb8b657f4d2de4603734f24daa624d204 URL: https://github.com/llvm/llvm-project/commit/be437f3bb8b657f4d2de4603734f24daa624d204 DIFF: https://github.com/llvm/llvm-project/commit/be437f3bb8b657f4d2de4603734f24daa624d204.diff

[clang] f601039 - [Driver][RISCV] Adjust the priority between -mcpu, -mtune and -march

Author: Kito Cheng Date: 2023-01-13T23:58:31+08:00 New Revision: f601039e8165cb2a49c783ccf4aafd1f7b326a63 URL: https://github.com/llvm/llvm-project/commit/f601039e8165cb2a49c783ccf4aafd1f7b326a63 DIFF: https://github.com/llvm/llvm-project/commit/f601039e8165cb2a49c783ccf4aafd1f7b326a63.diff

[clang] f4c887c - [RISCV] Add H extension

Author: Kito Cheng Date: 2023-01-10T09:52:03+08:00 New Revision: f4c887c3a8406d85f4f942c8350f10026994f4d8 URL: https://github.com/llvm/llvm-project/commit/f4c887c3a8406d85f4f942c8350f10026994f4d8 DIFF: https://github.com/llvm/llvm-project/commit/f4c887c3a8406d85f4f942c8350f10026994f4d8.diff

[clang] 3fe89be - [clang][RISCV][NFC] Prevent data race in RVVType::computeType

Author: Kito Cheng Date: 2022-11-23T16:59:19+08:00 New Revision: 3fe89be8015955f2e8403f8b7d7580db13cedb2c URL: https://github.com/llvm/llvm-project/commit/3fe89be8015955f2e8403f8b7d7580db13cedb2c DIFF: https://github.com/llvm/llvm-project/commit/3fe89be8015955f2e8403f8b7d7580db13cedb2c.diff

[clang] ae116f4 - [RISCV] Drop single letter b extension support

Author: Kito Cheng Date: 2022-10-27T23:53:32+08:00 New Revision: ae116f43ff140edfae166370ab6bc9ae3f556710 URL: https://github.com/llvm/llvm-project/commit/ae116f43ff140edfae166370ab6bc9ae3f556710 DIFF: https://github.com/llvm/llvm-project/commit/ae116f43ff140edfae166370ab6bc9ae3f556710.diff

[clang] 7a5cb15 - [RISCV] Lazily add RVV C intrinsics.

Author: Kito Cheng Date: 2022-07-26T15:47:47+08:00 New Revision: 7a5cb15ea6facd82756adafae76d60f36a0b60fd URL: https://github.com/llvm/llvm-project/commit/7a5cb15ea6facd82756adafae76d60f36a0b60fd DIFF: https://github.com/llvm/llvm-project/commit/7a5cb15ea6facd82756adafae76d60f36a0b60fd.diff

[clang] 1b8cde9 - [RISCV][NFC] Move static global variables into static variable in function.

Author: Kito Cheng Date: 2022-06-30T10:30:01+08:00 New Revision: 1b8cde9b633841c7199b345132423dd3d6bdf3e7 URL: https://github.com/llvm/llvm-project/commit/1b8cde9b633841c7199b345132423dd3d6bdf3e7 DIFF: https://github.com/llvm/llvm-project/commit/1b8cde9b633841c7199b345132423dd3d6bdf3e7.diff

[clang] b166aa8 - [RISCV][NFC] Change interface of RVVIntrinsic::getSuffixStr

Author: Kito Cheng Date: 2022-05-24T17:24:32+08:00 New Revision: b166aa833e44a5af6d6f39c34b79fe21b443e424 URL: https://github.com/llvm/llvm-project/commit/b166aa833e44a5af6d6f39c34b79fe21b443e424 DIFF: https://github.com/llvm/llvm-project/commit/b166aa833e44a5af6d6f39c34b79fe21b443e424.diff

[clang] 1467e01 - [RISCV][NFC] Rename variable in RISCVVEmitter.cpp

Author: Kito Cheng Date: 2022-05-18T23:14:29+08:00 New Revision: 1467e01f8f699fa2a69937dd07e51325ba71a93b URL: https://github.com/llvm/llvm-project/commit/1467e01f8f699fa2a69937dd07e51325ba71a93b DIFF: https://github.com/llvm/llvm-project/commit/1467e01f8f699fa2a69937dd07e51325ba71a93b.diff

[clang] 5bc469f - [RISCV][NFC] Fix build issue

Author: Kito Cheng Date: 2022-05-16T16:00:23+08:00 New Revision: 5bc469fd96192039bafe4bb9f74c85b37f63212e URL: https://github.com/llvm/llvm-project/commit/5bc469fd96192039bafe4bb9f74c85b37f63212e DIFF: https://github.com/llvm/llvm-project/commit/5bc469fd96192039bafe4bb9f74c85b37f63212e.diff

[clang] 7ff0bf5 - [RISCV][NFC] Refactor RISC-V vector intrinsic utils.

Author: Kito Cheng Date: 2022-05-16T15:13:05+08:00 New Revision: 7ff0bf576b841d5418c0fb1c4b94f16c6205e7d9 URL: https://github.com/llvm/llvm-project/commit/7ff0bf576b841d5418c0fb1c4b94f16c6205e7d9 DIFF: https://github.com/llvm/llvm-project/commit/7ff0bf576b841d5418c0fb1c4b94f16c6205e7d9.diff

[clang] 41b951c - [RISCV] Fix int16 -> __fp16 conversion code gen

Author: Kito Cheng Date: 2022-04-30T11:10:44+08:00 New Revision: 41b951c92931b65c25485b224901d8cb00163b8e URL: https://github.com/llvm/llvm-project/commit/41b951c92931b65c25485b224901d8cb00163b8e DIFF: https://github.com/llvm/llvm-project/commit/41b951c92931b65c25485b224901d8cb00163b8e.diff

[clang] 02c7de3 - [RISCV] Precommit test for D124509

Author: Kito Cheng Date: 2022-04-30T11:09:12+08:00 New Revision: 02c7de3a4c32f2456df09df07e473bb95c85529c URL: https://github.com/llvm/llvm-project/commit/02c7de3a4c32f2456df09df07e473bb95c85529c DIFF: https://github.com/llvm/llvm-project/commit/02c7de3a4c32f2456df09df07e473bb95c85529c.diff

[clang] f26c41e - [RISCV] Moving RVV intrinsic type related util to clang/Support

Author: Kito Cheng Date: 2022-04-20T21:13:13+08:00 New Revision: f26c41e8dd28d86030cd0f5a6e9c11036acea5d2 URL: https://github.com/llvm/llvm-project/commit/f26c41e8dd28d86030cd0f5a6e9c11036acea5d2 DIFF: https://github.com/llvm/llvm-project/commit/f26c41e8dd28d86030cd0f5a6e9c11036acea5d2.diff

[clang] f922dbb - Revert "Reland "[RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support""

Author: Kito Cheng Date: 2022-04-08T16:20:19+08:00 New Revision: f922dbb7923f73bab058d09346a2ec0b40ae3cb2 URL: https://github.com/llvm/llvm-project/commit/f922dbb7923f73bab058d09346a2ec0b40ae3cb2 DIFF: https://github.com/llvm/llvm-project/commit/f922dbb7923f73bab058d09346a2ec0b40ae3cb2.diff

[clang] fc2d832 - Reland "[RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support"

Author: Kito Cheng Date: 2022-04-08T15:09:03+08:00 New Revision: fc2d8326ae4d6e05c1aa2db7e7dbd8e759bf4d51 URL: https://github.com/llvm/llvm-project/commit/fc2d8326ae4d6e05c1aa2db7e7dbd8e759bf4d51 DIFF: https://github.com/llvm/llvm-project/commit/fc2d8326ae4d6e05c1aa2db7e7dbd8e759bf4d51.diff

[clang] ad57e10 - [RISCV][NFC] Moving RVV intrinsic type related util to llvm/Support

Author: Kito Cheng Date: 2022-03-28T14:35:28+08:00 New Revision: ad57e10dbca2fdeff1448afc0aa1cf23d6df8736 URL: https://github.com/llvm/llvm-project/commit/ad57e10dbca2fdeff1448afc0aa1cf23d6df8736 DIFF: https://github.com/llvm/llvm-project/commit/ad57e10dbca2fdeff1448afc0aa1cf23d6df8736.diff

[clang] 071a9b7 - [NFC][RISCV] Fix path checking issue if default sysroot is given

Author: Kito Cheng Date: 2022-02-21T20:43:51+08:00 New Revision: 071a9b751a46205dc276069dfbc0d38582736990 URL: https://github.com/llvm/llvm-project/commit/071a9b751a46205dc276069dfbc0d38582736990 DIFF: https://github.com/llvm/llvm-project/commit/071a9b751a46205dc276069dfbc0d38582736990.diff

[clang] c1f17b0 - [RISCV] Fix the include search path order between sysroot and resource folder (Recommit again)

Author: Kito Cheng Date: 2022-02-21T15:25:21+08:00 New Revision: c1f17b0a9ea0d467eaa9589cc28db2787efe3ebf URL: https://github.com/llvm/llvm-project/commit/c1f17b0a9ea0d467eaa9589cc28db2787efe3ebf DIFF: https://github.com/llvm/llvm-project/commit/c1f17b0a9ea0d467eaa9589cc28db2787efe3ebf.diff

[clang] cc27952 - Revert "[RISCV] Fix the include search path order between sysroot and resource folder (Recommit)"

Author: Kito Cheng Date: 2022-02-21T14:56:58+08:00 New Revision: cc279529e8317301492f9625b6acc9a0bf52db56 URL: https://github.com/llvm/llvm-project/commit/cc279529e8317301492f9625b6acc9a0bf52db56 DIFF: https://github.com/llvm/llvm-project/commit/cc279529e8317301492f9625b6acc9a0bf52db56.diff

[clang] 47b1fa5 - [RISCV] Fix the include search path order between sysroot and resource folder (Recommit)

Author: Kito Cheng Date: 2022-02-21T14:39:43+08:00 New Revision: 47b1fa5fc48821eefefd157ed4af2f2cf3bacef4 URL: https://github.com/llvm/llvm-project/commit/47b1fa5fc48821eefefd157ed4af2f2cf3bacef4 DIFF: https://github.com/llvm/llvm-project/commit/47b1fa5fc48821eefefd157ed4af2f2cf3bacef4.diff

[clang] 0a17ee1 - Revert "[RISCV] Fix the include search path order between sysroot and resource folder"

Author: Kito Cheng Date: 2022-02-21T14:25:49+08:00 New Revision: 0a17ee1ebe0c3384520ea14fdc1d33e38217341a URL: https://github.com/llvm/llvm-project/commit/0a17ee1ebe0c3384520ea14fdc1d33e38217341a DIFF: https://github.com/llvm/llvm-project/commit/0a17ee1ebe0c3384520ea14fdc1d33e38217341a.diff

[clang] 079d136 - [RISCV] Fix the include search path order between sysroot and resource folder

Author: Kito Cheng Date: 2022-02-21T14:06:47+08:00 New Revision: 079d13668bf1b7f929f1897af90f64caae41c81d URL: https://github.com/llvm/llvm-project/commit/079d13668bf1b7f929f1897af90f64caae41c81d DIFF: https://github.com/llvm/llvm-project/commit/079d13668bf1b7f929f1897af90f64caae41c81d.diff

[clang] 8efa651 - [RISCV][NFC] Fix build error

Author: Kito Cheng Date: 2021-10-17T16:38:53+08:00 New Revision: 8efa6512e0662b813ab783ed937768cef28e5a8b URL: https://github.com/llvm/llvm-project/commit/8efa6512e0662b813ab783ed937768cef28e5a8b DIFF: https://github.com/llvm/llvm-project/commit/8efa6512e0662b813ab783ed937768cef28e5a8b.diff

[clang] ff13189 - [RISCV] Unify the arch string parsing logic to to RISCVISAInfo.

Author: Kito Cheng Date: 2021-10-17T16:25:23+08:00 New Revision: ff13189c5d0d96d0f955e9b1e951cf0ddc9e1d92 URL: https://github.com/llvm/llvm-project/commit/ff13189c5d0d96d0f955e9b1e951cf0ddc9e1d92 DIFF: https://github.com/llvm/llvm-project/commit/ff13189c5d0d96d0f955e9b1e951cf0ddc9e1d92.diff

[clang] 5635d2a - [RISCV] Pass -u to linker correctly.

Author: Kito Cheng Date: 2021-07-14T14:25:02+08:00 New Revision: 5635d2a56dab6dc64d3a3f185d68f676b81dc736 URL: https://github.com/llvm/llvm-project/commit/5635d2a56dab6dc64d3a3f185d68f676b81dc736 DIFF: https://github.com/llvm/llvm-project/commit/5635d2a56dab6dc64d3a3f185d68f676b81dc736.diff

[clang] b46a1b1 - [doc] Fix description of _Float16

Author: Kito Cheng Date: 2021-03-04T14:17:54+08:00 New Revision: b46a1b129f684a230dd680341d198d8b11731812 URL: https://github.com/llvm/llvm-project/commit/b46a1b129f684a230dd680341d198d8b11731812 DIFF: https://github.com/llvm/llvm-project/commit/b46a1b129f684a230dd680341d198d8b11731812.diff

[clang] cfa7094 - [RISCV] Add -mtune support

Author: Kito Cheng Date: 2020-10-16T13:55:08+08:00 New Revision: cfa7094e49cfb7e37a84c0aa57c85c64c0581d17 URL: https://github.com/llvm/llvm-project/commit/cfa7094e49cfb7e37a84c0aa57c85c64c0581d17 DIFF: https://github.com/llvm/llvm-project/commit/cfa7094e49cfb7e37a84c0aa57c85c64c0581d17.diff

r372080 - [RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow

Author: kito Date: Tue Sep 17 01:19:17 2019 New Revision: 372080 URL: http://llvm.org/viewvc/llvm-project?rev=372080=rev Log: [RISCV] Add option aliases: -mcmodel=medany and -mcmodel=medlow RISC-V GCC use -mcmodel=medany and -mcmodel=medlow, but LLVM use -mcmodel=small and -mcmodel=medium. Add

r372078 - [RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly

Author: kito Date: Tue Sep 17 01:09:56 2019 New Revision: 372078 URL: http://llvm.org/viewvc/llvm-project?rev=372078=rev Log: [RISCV] Define __riscv_cmodel_medlow and __riscv_cmodel_medany correctly RISC-V LLVM was only implement small/medlow code model, so it defined __riscv_cmodel_medlow

r340595 - [RISCV] RISC-V using -fuse-init-array by default

Author: kito Date: Thu Aug 23 20:05:08 2018 New Revision: 340595 URL: http://llvm.org/viewvc/llvm-project?rev=340595=rev Log: [RISCV] RISC-V using -fuse-init-array by default Reviewers: asb, apazos, mgrang Reviewed By: asb Differential Revision: https://reviews.llvm.org/D50043 Modified: